RBL paper _Design_of_MIGFET_based_junctionless_transistor
1. Design of MIGFET Based Junctionless Transistor
1
Hema.N
SENSE Department, VIT University
Tamil Nadu, India
1
hema.n2013@vit.ac.in
Abstract— This paper describes about a novel device called
junctionless transistor. The properties of junctionless transistor
is analysed using TCAD tool. ID-VG characteristics of junctonless
transistor is obtained and analysed. ID-VG characteristics of
MIGFET based junctionless transistor is finally analysed with
various curves by fixing one of the gate voltage and varying
voltage in other gate. Mixer output is taken from mixer in
MIGFET based junctionless transistor. Designing of MIGFET
based junctionless transistor is done using TCAD tool.
Keywords— Junction-less, MIGFET, TCAD
I. INTRODUCTION
The semiconductor world is now focusing on to the scaling
down of transistor sizes. But mainly designers know how
difficult it is to fabricate a transistor with such a low
nanometre scale, since its having different doping levels
which form source and drain junctions. So they have to be
very specific and accurate while designing which makes the
whole fabrication process very complex. [1] Here comes the
role of the novel device called Junctionless transistors that too
with multiple independent gates. The multigate device
employing independent gate electrodes at times is called
as Multiple Independent Gate Field Effect
Transistor (MIGFET).
Junctionless transistor is a heavily doped silicon nanowire
with independent gate electrodes. The semiconductor layer
must be thin and narrow enough to allow for full depletion of
carriers when the device is turned off and the semiconductor
layer needs to be heavily doped to allow for a reasonable
amount of current flow when the device is turned on. [2] N-
channel accumulation –mode devices have N+ -N –N+ doping
for the source, channel and drain region, respectively. Similar
is the case for P-channel devices. In junction transistor, the
major carriers in channel region make itself a barrier to carrier
scattering. But, here junctionless transistor does not have this
problem. With every technology node scaling is getting
challenging.[3]
The advantages of juntionless transistor includes lack of
abrupt junctions that can be hardly controlled at the nanometer
scale and has simpler fabrication process. It has a channel
region which is highly doped and of same carrier type as that
of source and drain regions and is turned off by body
depletion using a suitable gate work function.[4]
At nanometre sizes it is very hard to control the sharp
source/drain-channel junctions from the device fabrication
point of view. The use of channel with corners leads to
another effect called corner effect. In inversion mode devices
lightly doped channel is used to avoid this.
Moore’s law tells the number of transistors on integrated
circuits doubles approximately every two years. The period is
often quoted as eighteen months. Gordon E. Moore, the Intel
co-founder, after whom this law is named, described the trend
in his 1965 paper. [5] He predicted that this trend would
continue for atleast ten years. But for doubling the number of
transistors,we have to reduce the size of the transistors.
A. Scaling
The device performance has been steadily improved by
scaling to smaller physical dimensions. When we scale down
the power supply by increasing channel doping, then that will
cause the width of the depletion region to scale with the
device dimensions. Oxide thickness and depletion widths are
decreased by the same factor. [6] So all the electric fields
within the device remain constant. It is difficult to design the
board level design for chips to operate at different voltages.
Also scaling the power supply hurts the performance. So the
chip foundries avoid the power supply scaling as long as
possible. In inversion mode transistors, as we move the source
and drain physically together, it becomes more and more
difficult to electrically isolate them. Thus the problem of
scaling arises. They are short channel effects and Drain
Induced Barrier Lowering (DIBL). To a great extend this
problems are resolved while we use junctionless transistors.
[2]
B. Short Channel Effects
Short-channel effects are predicted to be less important in
junctionless devices. In inversion mode transistor, as channel
length is reduced, the device threshold becomes dependent on L
and VDS. This deviations from the ideal threshold model in L is
called as short channel effect and that in VDS is called as DIBL.
In an inversion mode transistor, with physical gate length L
physical the effective gate length is Leff when the device is on,
and the effective gate length is LSCE when the device is off.
Now, LSCE < Leff, which means that the effective channel length
when the device is off is shorter than when it is on. In the
junctionless transistor, we know that the doping concentration is
constant across the device. [7] The electrostatic squeezing of the
channel in the off device propagates into the source and drain and
as a result, Leff > Lphysical when the device is off. When the device
is on, the squeezing effect is removed, and then it becomes Leff
= Lphysical. As a result, Leff is larger on the off state than in the on
state, which improves the short-channel effects. But it is worth
noting that the longer effective gate length of junctionless device
is not the reason for it’s better short channel characteristics.
2. C. DIBL
Drain Induced Barrier Lowering (DIBL) is a short channel
effect which causes the reduction of threshold voltage of the
transistor at higher drain voltages. This reduction of threshold
voltage is taking place as a consequence of charge neutrality.
The combined charge in the depletion region of the device and
that in the channel of the device is balanced by three electrode
charges. [8] They are the gate, the source and the drain. As
drain voltage is increased, the depletion region of the pn-
junction between the drain and the substrate increases in size
and it extends under the gate. So the drain assumes a greater
portion of the burden of balancing depletion region charge,
leaving a smaller burden for the gate. As a result, the charge
on the gate retains charge balance by attracting more carriers
into the channel, which causes the reduction of threshold
voltage. Thus the potential energy barrier for electrons in the
channel is lowered. Thus it’s called as Drain Induced Barrier
Lowering.
D. Working
The simple fabrification of junctionless transistor is due to
the elimination of junction implantation and annealing. So this
simple process results in a reduced cost. Since here for
junctionless transistor, the channel is having N-type doping,
The simple fabrification of junctionless transistor is due to the
elimination of junction implantation and annealing.[3] So this
simple process results in a reduced cost. Since here for
junctionless transistor, the channel is having N-type doping,
an N-channel junctionless device requires a gate material with
a high work function, so as to achieve a suitable threshold
voltage value. Thus use of a metal as a gate material is
preferable for gate resistance reduction purposes.Working
Entire Si nanowire is heavily n-doped excellent conductor.
Gate is P-doped. It deplete the number of electrons in the
region of nanowire under the gate. Voltage is applied across
the nanowire. Current will get squeezed at depletion region
below the gate. This squeezing effect is reduced when we
apply voltage to gate and then the current starts flowing.[9]
Energy which is necessary to extract an electron from the
valance band of the metal is called the work function, m.
Similarly the work function in semiconductor is denoted as
sc.. To make the electrons leave from the semiconductor the
work function of gate is made higher than the work function
of semiconductor. Thus in N-type, m > sc and in P-type, m
< sc.
II. TCAD SIMULATOR
TCAD simulator refers to the performance of all the
simulations. The modeling of the fabrication is termed
Process TCAD, while the modeling of the device operation is
termed Device TCAD. [10] Modules of TCAD used here are
the following.
Sentaurus structure editor (SDE) : To create 2D and 3D
device structures, to import structures from a prior process
simulation step and to generate mesh structures.
Sentaurus device simulator (SDEVICE) : To perform all
DC, AC simulations.
Sentaurus visual & inspect : To view the structures and
results generated from the process and device simulations.
[11]
The TableI below shows the dimension of junctionless
transistor.[1]
TABLE I
PARAMETERS OF JUNCTIONLESS TRANSISTOR
Process/device parameters Junctionless transistor
Channel doping 8×1019
/cm3
Gate oxide thickness 1nm
Gate work function 5.5eV
Wfin 10nm
Lg 30nm
Structure of junctionless transistor is viewed using TCAD
tool. This is illustrated in Fig1.
Fig. 1 SDE structure of Junctionless transistor in TCAD
Upper and lower parts show the source, channel and drain
of junctionless transistor. The portion between the source and
drain forms the channel .Interfaces are given fine meshing to
get more accurate characteristics. Either parts of channel has
silicon dioxide and over that gate metal. Channel length is
taken as 30nm with a gate of work function 5.5eV.
The use of junctionless does not direct source-to-drain
tunnelling in very short channel devices. The use of additional
source and drain doping concentration structure improves the
current drive significantly in junctionless devices. This is done
because in accumulation mode devices a reduction of channel
doping concentration is required to achieve suitable threshold
and sub threshold values when the fin width is increased. So
that source and drain resistance increases which reduces the
current drive. This is corrected by classical spacer formation
and by an additional source and drain implantation.
The fin width of junctionless devices must be small
enough for the channel region to be completely depleted of
carriers when a gate voltage is applied to turn the device off.
The actual minimum fin size value of junctionless devices is
dependentant of the channel doping concentration. In
accumulation mode the influence of fin width variation on
threshold voltage is larger.
3. In MIGFET, the thin silicon channel is controlled by
multiple gate electrodes, that are separated from each other.
For designing MIGFET based junctionless transistor, two
gates with independent voltages are applied to the junctionless
transistor.
Fig. 2 SDE structure of junctionless transistor with independent gate
voltages in TCAD
Here one of the gate voltage is kept fixed and other
varies.Fig.1 represents the schematic view of junction less
transistor with independent gates. This independently controls
the channel region of the transistor.
Mixer mixes two input signals, here sine and square, such
that the output frequency is either the sum frequency or
difference frequency of inputs. Signal should not get clipped
from the channel while mixing, because that may lead to the
loss of information.
III. RESULTS AND DISCUSSION
Fig.3 shows the simulated ID-VG characteristic of junctionless
device.
Fig. 3 ID-VG plot
The Ion and Ioff values are calculated from curve data and
are obtained as,
Ion = 982µA
Ioff = 4.22nA
Ion/Ioff = 232.70 × 103
In MIGFET based junctionless transistor, as in Fig.2 two
gates with independent voltages are given. In this, one of the
gate is kept fixed and other gate is varied from -1V to
1V.Then following graph Fig . 4 is obtained. Here from top to
bottom curve varies from -1V to 1V.
Fig. 4 ID-VG graph of MIGFET based junctionless transistor (log scale)
Fig. 5 ID-VG graph of MIGFET based junctionless transistor (linear
scale)
From this graph threshold voltages(Vth),
transconductances(gm) and subthreshold slopes(ss) were
calculated and compared. Subthreshold slope was calculated
by using the formula.
![Design of MIGFET Based Junctionless Transistor
1
Hema.N
SENSE Department, VIT University
Tamil Nadu, India
1
hema.n2013@vit.ac.in
Abstract— This paper describes about a novel device called
junctionless transistor. The properties of junctionless transistor
is analysed using TCAD tool. ID-VG characteristics of junctonless
transistor is obtained and analysed. ID-VG characteristics of
MIGFET based junctionless transistor is finally analysed with
various curves by fixing one of the gate voltage and varying
voltage in other gate. Mixer output is taken from mixer in
MIGFET based junctionless transistor. Designing of MIGFET
based junctionless transistor is done using TCAD tool.
Keywords— Junction-less, MIGFET, TCAD
I. INTRODUCTION
The semiconductor world is now focusing on to the scaling
down of transistor sizes. But mainly designers know how
difficult it is to fabricate a transistor with such a low
nanometre scale, since its having different doping levels
which form source and drain junctions. So they have to be
very specific and accurate while designing which makes the
whole fabrication process very complex. [1] Here comes the
role of the novel device called Junctionless transistors that too
with multiple independent gates. The multigate device
employing independent gate electrodes at times is called
as Multiple Independent Gate Field Effect
Transistor (MIGFET).
Junctionless transistor is a heavily doped silicon nanowire
with independent gate electrodes. The semiconductor layer
must be thin and narrow enough to allow for full depletion of
carriers when the device is turned off and the semiconductor
layer needs to be heavily doped to allow for a reasonable
amount of current flow when the device is turned on. [2] N-
channel accumulation –mode devices have N+ -N –N+ doping
for the source, channel and drain region, respectively. Similar
is the case for P-channel devices. In junction transistor, the
major carriers in channel region make itself a barrier to carrier
scattering. But, here junctionless transistor does not have this
problem. With every technology node scaling is getting
challenging.[3]
The advantages of juntionless transistor includes lack of
abrupt junctions that can be hardly controlled at the nanometer
scale and has simpler fabrication process. It has a channel
region which is highly doped and of same carrier type as that
of source and drain regions and is turned off by body
depletion using a suitable gate work function.[4]
At nanometre sizes it is very hard to control the sharp
source/drain-channel junctions from the device fabrication
point of view. The use of channel with corners leads to
another effect called corner effect. In inversion mode devices
lightly doped channel is used to avoid this.
Moore’s law tells the number of transistors on integrated
circuits doubles approximately every two years. The period is
often quoted as eighteen months. Gordon E. Moore, the Intel
co-founder, after whom this law is named, described the trend
in his 1965 paper. [5] He predicted that this trend would
continue for atleast ten years. But for doubling the number of
transistors,we have to reduce the size of the transistors.
A. Scaling
The device performance has been steadily improved by
scaling to smaller physical dimensions. When we scale down
the power supply by increasing channel doping, then that will
cause the width of the depletion region to scale with the
device dimensions. Oxide thickness and depletion widths are
decreased by the same factor. [6] So all the electric fields
within the device remain constant. It is difficult to design the
board level design for chips to operate at different voltages.
Also scaling the power supply hurts the performance. So the
chip foundries avoid the power supply scaling as long as
possible. In inversion mode transistors, as we move the source
and drain physically together, it becomes more and more
difficult to electrically isolate them. Thus the problem of
scaling arises. They are short channel effects and Drain
Induced Barrier Lowering (DIBL). To a great extend this
problems are resolved while we use junctionless transistors.
[2]
B. Short Channel Effects
Short-channel effects are predicted to be less important in
junctionless devices. In inversion mode transistor, as channel
length is reduced, the device threshold becomes dependent on L
and VDS. This deviations from the ideal threshold model in L is
called as short channel effect and that in VDS is called as DIBL.
In an inversion mode transistor, with physical gate length L
physical the effective gate length is Leff when the device is on,
and the effective gate length is LSCE when the device is off.
Now, LSCE < Leff, which means that the effective channel length
when the device is off is shorter than when it is on. In the
junctionless transistor, we know that the doping concentration is
constant across the device. [7] The electrostatic squeezing of the
channel in the off device propagates into the source and drain and
as a result, Leff > Lphysical when the device is off. When the device
is on, the squeezing effect is removed, and then it becomes Leff
= Lphysical. As a result, Leff is larger on the off state than in the on
state, which improves the short-channel effects. But it is worth
noting that the longer effective gate length of junctionless device
is not the reason for it’s better short channel characteristics.](https://image.slidesharecdn.com/9d9906bc-01af-4211-84be-245b19d1ccb5-151019100018-lva1-app6891/85/RBL-paper-_Design_of_MIGFET_based_junctionless_transistor-1-320.jpg)
![C. DIBL
Drain Induced Barrier Lowering (DIBL) is a short channel
effect which causes the reduction of threshold voltage of the
transistor at higher drain voltages. This reduction of threshold
voltage is taking place as a consequence of charge neutrality.
The combined charge in the depletion region of the device and
that in the channel of the device is balanced by three electrode
charges. [8] They are the gate, the source and the drain. As
drain voltage is increased, the depletion region of the pn-
junction between the drain and the substrate increases in size
and it extends under the gate. So the drain assumes a greater
portion of the burden of balancing depletion region charge,
leaving a smaller burden for the gate. As a result, the charge
on the gate retains charge balance by attracting more carriers
into the channel, which causes the reduction of threshold
voltage. Thus the potential energy barrier for electrons in the
channel is lowered. Thus it’s called as Drain Induced Barrier
Lowering.
D. Working
The simple fabrification of junctionless transistor is due to
the elimination of junction implantation and annealing. So this
simple process results in a reduced cost. Since here for
junctionless transistor, the channel is having N-type doping,
The simple fabrification of junctionless transistor is due to the
elimination of junction implantation and annealing.[3] So this
simple process results in a reduced cost. Since here for
junctionless transistor, the channel is having N-type doping,
an N-channel junctionless device requires a gate material with
a high work function, so as to achieve a suitable threshold
voltage value. Thus use of a metal as a gate material is
preferable for gate resistance reduction purposes.Working
Entire Si nanowire is heavily n-doped excellent conductor.
Gate is P-doped. It deplete the number of electrons in the
region of nanowire under the gate. Voltage is applied across
the nanowire. Current will get squeezed at depletion region
below the gate. This squeezing effect is reduced when we
apply voltage to gate and then the current starts flowing.[9]
Energy which is necessary to extract an electron from the
valance band of the metal is called the work function, m.
Similarly the work function in semiconductor is denoted as
sc.. To make the electrons leave from the semiconductor the
work function of gate is made higher than the work function
of semiconductor. Thus in N-type, m > sc and in P-type, m
< sc.
II. TCAD SIMULATOR
TCAD simulator refers to the performance of all the
simulations. The modeling of the fabrication is termed
Process TCAD, while the modeling of the device operation is
termed Device TCAD. [10] Modules of TCAD used here are
the following.
Sentaurus structure editor (SDE) : To create 2D and 3D
device structures, to import structures from a prior process
simulation step and to generate mesh structures.
Sentaurus device simulator (SDEVICE) : To perform all
DC, AC simulations.
Sentaurus visual & inspect : To view the structures and
results generated from the process and device simulations.
[11]
The TableI below shows the dimension of junctionless
transistor.[1]
TABLE I
PARAMETERS OF JUNCTIONLESS TRANSISTOR
Process/device parameters Junctionless transistor
Channel doping 8×1019
/cm3
Gate oxide thickness 1nm
Gate work function 5.5eV
Wfin 10nm
Lg 30nm
Structure of junctionless transistor is viewed using TCAD
tool. This is illustrated in Fig1.
Fig. 1 SDE structure of Junctionless transistor in TCAD
Upper and lower parts show the source, channel and drain
of junctionless transistor. The portion between the source and
drain forms the channel .Interfaces are given fine meshing to
get more accurate characteristics. Either parts of channel has
silicon dioxide and over that gate metal. Channel length is
taken as 30nm with a gate of work function 5.5eV.
The use of junctionless does not direct source-to-drain
tunnelling in very short channel devices. The use of additional
source and drain doping concentration structure improves the
current drive significantly in junctionless devices. This is done
because in accumulation mode devices a reduction of channel
doping concentration is required to achieve suitable threshold
and sub threshold values when the fin width is increased. So
that source and drain resistance increases which reduces the
current drive. This is corrected by classical spacer formation
and by an additional source and drain implantation.
The fin width of junctionless devices must be small
enough for the channel region to be completely depleted of
carriers when a gate voltage is applied to turn the device off.
The actual minimum fin size value of junctionless devices is
dependentant of the channel doping concentration. In
accumulation mode the influence of fin width variation on
threshold voltage is larger.](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)