This document outlines the key concepts covered in the first lecture of an introduction to CMOS VLSI design course, including: 1) The design of basic CMOS logic gates using nMOS pull-down and pMOS pull-up networks along with the concept of conduction complements. 2) The use of pass transistors and transmission gates to implement multiplexers and tristate buffers. 3) The design and operation of basic latches and flip-flops using D latches and a master-slave flip-flop configuration to prevent race conditions between clock signals.

1. Introduction to
CMOS VLSI
Design
Lecture 1:
Circuits & Layout
Manoel E. de Lima – CIn – UFPE
David Harris
Harvey Mudd College
Spring 2004

2. CMOS VLSI Design
1: Circuits & Layout Slide 2
Outline
 CMOS Gate Design
 Pass Transistors
 CMOS Latches & Flip-Flops
 Standard Cell Layouts
 Stick Diagrams

3. CMOS VLSI Design
1: Circuits & Layout Slide 3
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NAND gate

4. CMOS VLSI Design
1: Circuits & Layout Slide 4
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y

5. CMOS VLSI Design
1: Circuits & Layout Slide 5
Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)

6. CMOS VLSI Design
1: Circuits & Layout Slide 6
Series and Parallel
 nMOS: 1 = ON
 pMOS: 0 = ON
 Series: both must be ON
 Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
1
1 0 1
a
b
0 0
a
b
0
a
b
1
a
b
1
1 0 1
a
b
g1 g2

7. CMOS VLSI Design
1: Circuits & Layout Slide 7
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
A
B
Y

8. CMOS VLSI Design
1: Circuits & Layout Slide 8
Compound Gates
 Compound gates can do any inverting function
 Ex: A.B+C.D
00 01 11 10
00 1 1 0 1
01 1 1 0 1
11 0 0 0 0
10 1 1 0 1
AB
CD
nMOS
pMOS
nMOS+pMOS

9. CMOS VLSI Design
 Y = (A+B+C).D
Vcc
1: Circuits & Layout Slide 9
Example: O3AI

10. CMOS VLSI Design
1: Circuits & Layout Slide 10
Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network

11. CMOS VLSI Design
1: Circuits & Layout Slide 11
Pass Transistors
 Transistors can be used as switches
g
s d
g
s d

12. CMOS VLSI Design
1: Circuits & Layout Slide 12
Pass Transistors
 Transistors can be used as switches
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0

13. CMOS VLSI Design
1: Circuits & Layout Slide 13
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

14. CMOS VLSI Design
1: Circuits & Layout Slide 14
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0

15. CMOS VLSI Design
1: Circuits & Layout Slide 15
Tristates
 Tristate buffer produces Z when not enabled
EN A Y
0 0
0 1
1 0
1 1
A Y
EN
A Y
EN
EN

16. CMOS VLSI Design
1: Circuits & Layout Slide 16
Tristates
 Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN

17. CMOS VLSI Design
1: Circuits & Layout Slide 17
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors
• Noise on A is passed on to Y
A Y
EN
EN

18. CMOS VLSI Design
1: Circuits & Layout Slide 18
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
Y
EN
EN

19. CMOS VLSI Design
1: Circuits & Layout Slide 19
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN

20. CMOS VLSI Design
1: Circuits & Layout Slide 20
Multiplexers
 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0
0 X 1
1 0 X
1 1 X
0
1
S
D0
D1
Y

21. CMOS VLSI Design
1: Circuits & Layout Slide 21
Multiplexers
 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1
Y

22. CMOS VLSI Design
1: Circuits & Layout Slide 22
Gate-Level Mux Design

 How many transistors are needed?
1 0 (too many transistors)
Y SD SD
 

23. CMOS VLSI Design
1: Circuits & Layout Slide 23
Gate-Level Mux Design

 How many transistors are needed?
1 0 (too many transistors)
Y SD SD
 
20

24. CMOS VLSI Design
1: Circuits & Layout Slide 24
Inverting Mux
 Inverting multiplexer
– Pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter

25. CMOS VLSI Design
1: Circuits & Layout Slide 25
Transmission Gate Mux
 Two transmission gates
– Only 4 transistors
S
S
D0
D1
Y
S

26. CMOS VLSI Design
1: Circuits & Layout Slide 26
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects

27. CMOS VLSI Design
1: Circuits & Layout Slide 27
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates
S0
D0
D1
0
1
0
1
0
1
Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0

28. CMOS VLSI Design
1: Circuits & Layout Slide 28
D Latch
 When CLK = 1, latch is transparent
– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 Transparent latch or level-sensitive latch
CLK
D Q
Latch
D
CLK
Q

29. CMOS VLSI Design
1: Circuits & Layout Slide 29
D Latch Design
 Multiplexer chooses D or old Q

30. CMOS VLSI Design
1: Circuits & Layout Slide 30
D Latch Operation

31. CMOS VLSI Design
1: Circuits & Layout Slide 31
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 Positive edge-triggered flip-flop, master-slave flip-
flop
Flop
CLK
D Q
D
CLK
Q

32. CMOS VLSI Design
1: Circuits & Layout Slide 32
D Flip-flop Design
 Built from master and slave D latches
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latch
Latch
D Q
QM
CLK
CLK
Master Slave

33. CMOS VLSI Design
1: Circuits & Layout Slide 33
D Flip-flop Operation
Master on
Slave off
Master of
Slave on

34. CMOS VLSI Design
1: Circuits & Layout Slide 34
Race Condition
 Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
D
Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2

35. CMOS VLSI Design
1: Circuits & Layout Slide 35
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
– Industry manages skew more carefully instead
1
1
1
1
2
2
2
2
2
1
QM
Q
D