Polkadot JAM Slides - Token2049 - By Dr. Gavin Wood
Intro (Distributed computing)
1. Introduction Paul Krzyzanowski [email_address] [email_address] Distributed Systems Except as otherwise noted, the content of this presentation is licensed under the Creative Commons Attribution 2.5 License.
2. What can we do now that we could not do before?
4. Networking: Ethernet - 1973, 1976 June 1976 : Robert Metcalfe presents the concept of Ethernet at the National Computer Conference 1980 : Ethernet introduced as de facto standard (DEC, Intel, Xerox)
9. Storage: disk 131,000x cheaper in 20 years 30,000x more capacity Recording density increased over 60,000,000 times over 50 years 1977: 310KB floppy drive – $1480 1987: 40 MB drive for – $679 2008: 750 GB drive for – $99 $0.13 / GB
17. Bus-based multiprocessors SMP : Symmetric Multi-Processing All CPUs connected to one bus (backplane) Memory and peripherals are accessed via shared bus. System looks the same from any processor. Bus CPU A CPU B memory Device I/O
18. Bus-based multiprocessors Dealing with bus overload - add local memory CPU does I/O to cache memory - access main memory on cache miss Bus memory Device I/O CPU A cache CPU B cache
19. Working with a cache CPU A reads location 12345 from memory Bus 12345:7 Device I/O CPU A 12345: 7 CPU B
20. Working with a cache CPU A modifies location 12345 12345: 7 Bus 12345:7 Device I/O CPU A CPU B 12345: 3
21. Working with a cache CPU B reads location 12345 from memory Gets old value Memory not coherent! Bus 12345:7 Device I/O CPU A 12345: 3 CPU B 12345: 7
22. Write-through cache Fix coherency problem by writing all values through bus to main memory 12345:7 12345: 7 CPU A modifies location 12345 – write-through main memory is now coherent Bus Device I/O CPU A CPU B 12345: 3 12345:3
23. Write-through cache … continued CPU B reads location 12345 from memory - loads into cache Bus 12345:3 Device I/O CPU A 12345: 3 CPU B 12345: 3
24. Write-through cache CPU A modifies location 12345 - write-through 12345:3 12345: 3 Cache on CPU B not updated Memory not coherent! Bus Device I/O CPU A CPU B 12345: 3 12345:0 12345: 0
25. Snoopy cache Add logic to each cache controller: monitor the bus 12345: 3 12345: 3 12345: 3 write [12345] 0 12345: 3 Virtually all bus-based architectures use a snoopy cache Bus Device I/O CPU A CPU B 12345: 0 12345: 0 12345: 0
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27. Switched multiprocessors Divide memory into groups and connect chunks of memory to the processors with a crossbar switch n 2 crosspoint switches – expensive switching fabric CPU CPU CPU CPU mem mem mem mem
28. Crossbar alternative: omega network Reduce crosspoint switches by adding more switching stages CPU CPU CPU CPU mem mem mem mem
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33. Bus-based multicomputers Collection of workstations on a LAN Interconnect CPU memory LAN connector CPU memory LAN connector CPU memory LAN connector CPU memory LAN connector
34. Switched multicomputers Collection of workstations on a LAN CPU memory LAN connector CPU memory LAN connector CPU memory LAN connector CPU memory LAN connector n-port switch
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36. You know you have a distributed system when the crash of a computer you’ve never heard of stops you from getting any work done. – Leslie Lamport
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