1. Massively Parallel Architectures Colin Egan, Jason McGuiness and Michael Hicks (Compiler Technology and Computer Architecture Research Group)
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23. Logical View of the Cyclops64 Chip Architecture On-chip Memory (SRAM) : 160 x 28KB = 4480 KB Off-chip Memory (DDR2) : 4 x 256MB = 1GB Hard Drive (IDE) : 1 x 120GB = 120 GB SP is located in the memory banks and is accessed directly by the TU and via the crossbar network by the other TUs. Processors : 80 / chip Thread Units (TU) : 2 / processor Floating-Point Unit (FPU) : 1 / processor Shared Registers (SR) : 0 / processor Scratch-Pad Memory (SP) : n KB / TU Processor Chip Board Crossbar Network TU TU TU … SP SP SP FPU SR TU TU TU … SP SP SP FPU SR TU TU TU … SP SP SP FPU SR … MEMORY BANK MEMORY BANK MEMORY BANK MEMORY BANK MEMORY BANK MEMORY BANK MEMORY BANK MEMORY BANK … 6 * 4 GB/sec 4 GB/sec 50 MB/sec 1 Gbits/sec Off-Chip Memory Other Chips via 3D mesh Off-Chip Memory Off-Chip Memory Off-Chip Memory IDE HDD 4 GB/sec 6 * 4 GB/sec SP SP SP SP SP SP SP SP
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30. Jason’s Work with DIMES Shortly after program start Shortly before work stealing Just after work stealing More work stealing