Computer architecture and organization

1. INTERRUPTS
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COMPUTER ARCHITECTURE AND ORGANIZATION
MS SAIMA AMBER
Presented By:
Zara Tariq 2011/comp/BSCS/12537 1112639
Yumna Furqan 2011/comp/BSCS/12535 1112637

2. INTERRUPTS
 A signal from a device attached to a computer or from a program within the
computer which causes the main program that operates the computer to stop
and figure out what to do next.
 Almost all personal (or larger) computers today are interrupt-driven
 Mechanism by which other modules(e.g I/O) may interrupt normal sequence
of processing.
 Forced transfer of control to a procedure(handler) due to the external
events(interrupts) or due to an erroneous(exceptions).
Presented to Ms. Saima Amber

3. INTERRUPT HANDLING
 Mechanism
 Allows interrupts/exceptions to be handled transparently to the executing
process (application programs and operating system)
 Procedure
 When an interrupt Is received or an exception condition detection, the
current task is suspended and transfer automatically goes to a handler
 After the handler is complete, the interrupted task resumes without loss of
continuity, unless recovery is not possible or the interrupt causes the
currently running task to be terminated.
Presented to Ms. Saima Amber

4. TYPES OF INTERRUPTS
 Program – Something that occurs as a result of program execution
such as illegal instructions, arithmetic overflow, divide by zero, or
memory handling error
 Timer – Generated by one of the processor's internal timers so that
the processor can perform some time-scheduled task
 I/O – Generated by an I/O controller to request service from the
processor such as keyboard, mouse, NIC, disk drive
 Hardware failure – signifies some error condition with the
hardware
Presented to Ms. Saima Amber

5. INTERRUPT HANDLING
 CPU receives the interrupt request (IRQ) when running a program;
 CPU save its state of execution via a context switch;
 Begin execution of an interrupt handler/interrupt service routine
(ISR);
 When ISR finishes, CPU switch state back and continue the original
program.
Presented to Ms. Saima Amber

6. PROGRAM FLOW CONTROL
Presented to Ms. Saima Amber

7. INTERRUPT CYCLE
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler routine
 Process interrupt
 Restore context and continue interrupted program
Presented to Ms. Saima Amber

8. INSTRUCTION CYCLE (WITH INTERRUPTS)
STATE DIAGRAM
Presented to Ms. Saima Amber

9. MULTIPLE INTERRUPTS
 Disable interrupts
 Processor will ignore further interrupts while processing one interrupt.
 Interrupts remain pending and are checked after first interrupt has been
processed.
 Interrupts handled in sequence as they occur.
 Define priorities
 Low priority interrupts can be interrupted by higher priority interrupts.
 When higher priority interrupt has been processed, processor returns to
previous interrupt.
Presented to Ms. Saima Amber

10. MULTIPLE INTERRUPTS (SEQUENTIAL)
Presented to Ms. Saima Amber

11. MULTIPLE INTERRUPTS (NESTED)
Presented to Ms. Saima Amber

12. Thank You All For Your Kind Attention
Your Presenters: Zara Tariq & Yumna Furqan