timing and ittreupt

1. SEMINAR
ON
TIMING AND INTERRUPTS
SUBMITTED TO :
DR. LINI MATHEW
PROFESSOR & HOD
ELECTRICAL ENGINEERING DEPARTMENT
NITTTR, CHANDIGARH
SUBMITTED BY :
MALAY RANJAN MALLIK
Roll No.191505
BATCH-2019

2. CONTENTS
 Introduction of Timing
 Timing Diagram
 Different cycles
 What is interrupt?
 Interrupts Pin on 8085
 Interrupt Process
 Classification of interrupts
 Interrupts Priority
 References

3. TIMING
 Timing Diagram
 Instruction Cycle
 Machine Cycle
 T-State

4. CLOCK PULSE

5. Timing diagrams
• The 8085 microprocessor has 7 basic machine
cycle. They are
1. Op-code Fetch cycle(4T or 6T).
2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle(6T or 12T)
7. Bus idle cycle

6. 1.Opcodefetch cycle(4Tor 6T)

7. OPCODEFETCH
• TheOpcode fetch cycle, fetches the instructions from memory
and delivers it to the instruction register of the microprocessor
• Opcode fetch machine cycle consists of 4T-states.
T1State:
During the T1state, the contents of the program counter are
placed on the 16 bit address bus.Thehigher order 8 bits are
transferred to address bus (A8-A15) and lower order 8 bits are
transferred to multiplexed A/D (AD0-AD7)bus.
ALE(address latch enable) signal goes high. As soon as
ALEgoes high, the memory latches the AD0-AD7bus. At
the middle of the Tstate the ALEgoeslow

8. OPCODE FETCH
T2State:
During the beginning of this state, the 𝑅𝐷 signalgoeslow
to enable memory. It is during this state, the selected
memory location is placed on D0-D7of the Address/Data
multiplexed bus.
T3State:
In the previous state the Opcode is placed in D0-D7of the A/D
bus. Now the 𝑅𝐷 goeshighafter this action and thus
disables the memory from A/Dbus.
T4State:
In this state the Opcode which was fetched from the memory
is decoded.

9. 2. Memory Read Cycle
(3T)

10. Memory Read Cycle (3T)
T1state:
The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALEgoes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
Themp identifies the memory read machine cycle from the
status signals IO/𝑀 =
0
, S1=1,S0=0.Thiscondition indicates
the memory read cycle.
T2state:
Selected memory location is placed on the (D0-D7) ofthe A/D
multiplexed bus. RD’goes LOW
T3State:
Thedata which wasloaded on the previous state istransferred
to the microprocessor. In the middle of the T3state 𝑅𝐷goes
high and disables the memory read operation. Thedata which
wasobtained from the memory is thendecoded.
•
•
•

11. 3. Memory Write Cycle
(3T)

12. •
Memory Write Cycle
T1state:
• The higher order address bus (A8-A15) and lower order address and
data multiplexed (AD0-AD7) bus. ALEgoes high so that the memory
latches the (AD0-AD7)sothat complete 16-bit address are available.
Themp identifies the memory read machine cycle from the status
signals IO/ 𝑀 =
0
, S1=0,S0=1.Thiscondition indicates the memory
read cycle.
T2state:
Selected memory location is placed on the (D0-D7) ofthe A/D
multiplexed bus. 𝑊𝑅 goesLOW
T3State:
• In the middle of the T3 state 𝑊𝑅 goes high and disables the
memory write operation. The data which was obtained from the
memory is thendecoded.

13. 4.I/O read cycle(3T)

14. 5.I/O write cycle(3T)

15. WHAT IS INTERRUPT?
It is a signal when it occurs it stops the
currently executing program and
executes interrupt service routine
(ISR/ISS).

16. There are 5 interrupt inputs:
1) TRAP (non-maskable)
2) RST7.5
3) RST6.5
4) RST5.5
5) INTR
INTERRUPTS PIN ON IC

17. PROCESS
The I/O unit issues an interrupt signal to the
processor.
The processor finishes execution of the current
instruction before responding to the interrupt.
The processor test for an interrupt, determines that
there is one, and sends an acknowledgement signal
to the device that issued the interrupt.
The processor then begins to transfer its control to
the ISR which serves a interrupt request from the
device. ISR resides at a specified location.

18. PROCESS
Processor saves the information needed to resume
the current program at the point of interrupt.
The minimum information required is the status of
the processor and location of the next instruction to
be executed.
The processor then loads the program counter with
the entry location of the ISR that will responds to
this interrupt.
Once the PC has loaded, the control is transferred to
the interrupt handler program.

19. PROCESS
The fundamental requirement of the ISR is that it
should begin by saving the contents of all the
registers on the stack
The interrupt handler then proceeds to process the
interrupt.
When the interrupt processing is completed, the
saved registers value are retrieved from the stack and
restored to the register.
The final function is to restore the PSW and PC value
from the stack.

20. CLASSIFICATION OF INTERRUPTS
Interrupts
Hardware Software
 RST0
 RST1
 RST2
 RST3
 RST4
 RST5
 RST6
 RST7
Maskable
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
Non-maskeble
• TRAP

21. Maskable Interrupt
Enables/Disabled by executing instructions such as
EI (Enable Interrupt) and DI (Disable Interrupt).
If microprocessor’s Interrupt Enable Flip-Flop is
disabled, it ignores a maskable interrupt.
In 8085, the 1-byte instruction EI sets the interrupt
enable flip-flop and enable the interrupt process.
Similarly, 1-byte instruction DI resets the interrupt
flip-flop and disables the interrupt process

22. Non-Maskable Interrupt
Can’t be enabled/disabled by instructions.
Higher priority over the maskable interrupt.
When both the maskable and non-maskable
interrupt are activated at the same time, then the
processor will service the non-maskable interrupt
first.
In 8085, TRAP is an example of non-maskable
interrupt.

23. INTERNAL INTERRUPT
Arises from illegal or erroneous use of an instruction
or data.
Causes may be:
Register overflow
Divide by zero
An invalid operation code
Stack overflow, etc.
These error conditions usually occur as a result of
premature termination of the instruction execution
termed as exception.

24. Software Interrupt
This instruction provides means for switching from a
CPU user mode to the supervisor mode.
Certain operations in the computer may be assigned
to the supervisor mode only, as for example, a
complex input or output transfer procedure.
In 8085 the instruction like RST0, RST1, RST2,
RST3, RST4, RST5, RST6, RST7 causes software
interrupt.

25. Interrupt Priority
The first task of the interrupt system is to identify the
source of the interrupt.
There is also the possibility that several sources will request
service simultaneously.
In this case the system must also decide which device to
service first.
An interrupt priority is a system that establishes a priority
over the various sources to determine which condition is to
be serviced first when two or more requests arrive
simultaneously.
The system may also determine which conditions are
permitted to interrupt the computer while another interrupt
is being serviced.

26. Interrupt Priority
Higher-priority interrupt levels are assigned to request
which, if delayed or interrupted, could have serious
consequence.
Devices with higher speed transfers such as magnetic
disks are given high priority, and slow devices such as
keyboards receive low priority.
When two devices interrupt the processor at the same
time, the processor services the device, with the higher
priority first.

27. Interrupt Priority
Based on priority, it has five interrupts:
1. TRAP
2. RST7.5
Priority Decreasing
3. RST6.5
4. RST5.5
5. INTR
The four interrupts TRAP, RST7.5, RST6.5, RST5.5 are
automatically vectored to specific location without any
external hardware.
They do not require INTA signal or an input port, the
necessary hardware is already implemented inside the
8085.

28. INTR
Maskable interrupt
Can be enabled by instruction EI and can be disabled by
instruction DI.
Requires external hardware to transfer program
sequence to specific call locations.
There are 8 numbers of call locations for INTR interrupt.
The hardware circuit generates RST codes for this
purpose and places that on the data bus externally.
When the microprocessor is executing a program, it
checks the INTR line ( when interrupt enable flipflop is
enabled using EI instruction) during the execution of
each instruction.

29. INTR
If the line is high and the interrupt is enabled, the
microprocessor completes the current instruction,
disables the interrupt enable flipflop and sends a
INTA signal.
The processor does not accept any interrupt requests
until the interrupt flipflop is enabled again.

30. REFERENCES
www.slideshare.net
https://www.youtube.com/watch?v=oS5EchLKcmk
www.nptel.ac.in
http://www.pptsearchengine.net
https://www.youtube.com/watch?v=hyCGjvbMVz0