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1. Organisasi dan Arsitektur
Komputer
Ajeng Savitri Puspaningrum, M.Kom
Pertemuan 6

2. Central Processing Unit
(CPU) – Part 2

3. Explaining how the CPUs works
Explaining the CPUs cycle

4. Computer
Components:
Top Level View

5. 1. Instruction fetcher take
instruction/data from memory
2. Instruction decoder decodes the
instruction/data and save it to
Register or bring it to ALU to be
processed
3. ALU execute arithmetic or logic
instruction
4. ALU saves the result on register or
memory
How The CPU
Works

6. Instruction Cycle
Two steps:
Fetch
Execute

7. Fetch Cycle
Program Counter (PC) holds address of next
instruction to fetch
Processor fetches instruction from memory location
pointed to by PC
Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs
required actions

8. Execute Cycle
Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
Combination of above

9. Instruction Cycle State Diagram

10. Interrupts
Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
Program : e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O : from I/O controller
Hardware failure : e.g. memory parity error

11. Program Flow Control

12. Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt : Indicated by an
interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler routine
 Process interrupt
 Restore context and continue interrupted program

13. Instruction Cycle with Interrupts

14. Instruction Cycle (with Interrupts) - State
Diagram

15. Multiple Interrupts
 Disable interrupts
 Processor will ignore further interrupts whilst processing one interrupt
 Interrupts remain pending and are checked after first interrupt has been
processed
 Interrupts handled in sequence as they occur
 Define priorities
 Low priority interrupts can be interrupted by higher priority interrupts
 When higher priority interrupt has been processed, processor returns to
previous interrupt

16. Refference
Stalling, William, Computer Organization
and Architecture, 10th Edition, Pearson,
2015
Abdurohman, Maman, Organisasi dan
Arsitektur Komputer revisi ke-4, Penerbit
Informatika, 2017

17. Terima Kasih
ajeng.savitri@teknokrat.ac.id
https://teknokrat.ac.id/en/
https://spada.teknokrat.ac.id/