Genetic Programming in Automated Test Code Generation
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This document discusses using genetic programming to generate automated test code for multi-threaded microprocessors. It presents an experiment applying genetic programming to test code generation for the XMOS multi-threaded microprocessor. The results showed test code generated by the genetic programming approach significantly outperformed both human-generated and randomly generated test code, improving line coverage to 94% while reducing simulation cycles by up to 50%.
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1. The document discusses methodologies for hardware verification and developing an efficient verification flow.
2. It recommends defining a conceptual framework for the flow to standardize some aspects while allowing for diversity and innovation.
3. Using transaction level modeling and assertions in early stages like the specification model can help validation before the RTL design stage. Assertions can be written at different levels from the specification to the RTL and testbench.
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Verification In A Global Design Community
Verification teams at chip design companies now work globally, presenting communication challenges. Time zone differences make real-time collaboration difficult, and documentation through tools like TWiki can suffer if not well-organized. However, global teams also provide benefits by making more people and creative ideas available. Companies like AMD are addressing these issues through centers of expertise that standardize methodologies, tools, and components to facilitate collaboration across sites, while still allowing projects flexibility and innovation. Regular reviews help continuously improve processes as new techniques are adopted or abandoned.
Design Verification Using SystemC
Greg Tierney of Avid presented on their experiences using SystemC for design verification. Some key points:
1) Avid chose SystemC to enhance their existing C++ verification code and take advantage of its built-in verification capabilities like randomization and multi-threading.
2) SystemC helped Avid solve problems like connecting entire HDL modules to their testbench and monitoring foreign signals.
3) While SystemC provided benefits, Avid also encountered issues with its compile/link performance and large library size. Overall, Avid found SystemC reliable for design verification over three years of use.
Verification Strategy for PCI-Express
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SystemVerilog Assertions (SVA) in the Design/Verification Process
1) Visual SVA tools like Zazz allow designers to create complex SystemVerilog assertions through a graphical interface, addressing issues with SVA syntax.
2) Zazz also enables debugging assertions as they are created by generating constrained random tests, improving assertion quality before use in verification.
3) Using assertions improved the author's verification and debugging process, identifying errors sooner and in corner cases, and provided additional value to IP customers through early fault detection.
Efficiency Through Methodology
The document discusses methodologies for improving efficiency in verification testing at Cisco, including using reusable components from other projects, avoiding duplicate specifications, providing flexible testbenches, and automating tasks. It provides examples used at Cisco such as separating testbench creation into three stages, using testflow to synchronize component behavior, reusing unit-level checkers, linking transactions between checkers, and generating common infrastructure from templates to reduce designer effort. The biggest efficiency gains come from methodologies that push shared behavior into reusable components and standardize common elements.
Pre-Si Verification for Post-Si Validation
1) Pre-silicon verification is increasingly important for post-silicon validation as design complexity grows and schedules shrink. Bugs that escape pre-silicon verification can significantly impact post-silicon schedules and effort.
2) Mixed-signal effects, power-on/reset sequences, and design-for-testability features need to be verified pre-silicon to avoid difficult to reproduce bugs during post-silicon validation.
3) Case studies demonstrate how low investment in pre-silicon verification of areas like power-on/reset sequences and design-for-testability features can lead to longer post-silicon schedules due to unexpected bugs.
OpenSPARC T1 Processor
The document discusses Sun Microsystems' UltraSPARC T1 processor. It provides an overview of the processor's features, including its implementation of chip multi-threading with up to 8 cores and 32 threads. It describes the processor's design choices such as shared caches and memory controllers. It also discusses Sun's strategy for verifying the processor's architecture and microarchitecture through directed testing, coverage metrics, and other techniques. Finally, it notes some of the benefits of chip multi-threading for performance, cost, reliability, and power efficiency.
Intel Atom Processor Pre-Silicon Verification Experience
This document discusses the verification methodology and results for the Intel Atom processor. It describes the challenges of verifying a new microarchitecture with power management features on an aggressive schedule. The methodology involved cluster-level validation with functional coverage, architectural validation using an instruction set generator, and power management validation. Verification metrics like coverage and bug rates were tracked. The results included booting Windows and Linux 10 hours after receiving silicon, with few functional bugs found post-silicon that weren't corner cases. Debug and survivability features helped reduce escapes.
Using Assertions in AMS Verification
This document discusses using assertions in analog mixed-signal (AMS) verification. It describes how assertions can be used to check interface assumptions, power mode transitions, and timing relationships for AMS blocks. Assertions provide compact and precise checks that can be reused across different verification methodologies. The document also provides an example of using Verilog-AMS monitors to digitize continuous signals from an AMS model so they can be checked using SystemVerilog assertions.
Low-Power Design and Verification
This document discusses challenges and requirements for low-power design and verification. It begins with an overview of how leakage is significantly increasing due to process scaling and how active power is now a major portion of power budgets. New strategies are needed to address process variations and enhance scaling approaches. The verification flows must support multi-voltage domain analysis and rule-based checking across voltage states while capturing island ordering and microarchitecture sequence errors. Low-power implementation introduces challenges for design representation, implementation across tools, and verification. Methodologies and design flows must be adapted to account for power and ground nets becoming functional signals.
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- 1. Genetic Programming in automated test code generation for a multi-threaded microprocessor. Neow Way Yuh MSc. Machine Learning and Data Mining. Supervised by Dr. Kerstin Eder and Mr. Peter Hedinger
- 2. Introduction • The complexity of modern microprocessors makes verification difficult. • Recent research on Coverage-Directed test Generation (CDG) uses machine learning approaches. • Genetic Programming (GP) is one of the machine learning methods used in CDG. • Initial experiments with GP in multi-threaded microprocessor verification show potential. • Presentation starts with introduction to GP and a case study with the XMOS multi-threaded microprocessor.
- 3. • GP is based on the natural evolution process. • Darwin Theorem: Natural selection promotes favourable heritable traits in successive generations. • In GP, each individual in a population is given a quantitative measurement to reflect the quality of an individual relative to the environment. Fundamentals of Genetic Programming (GP)‫‏‬
- 4. GP in test code generation • Selection algorithm samples two individuals from the population based on their fitness values (e.g. Higher fitness value individuals get sampled more often). • The parents are merged using genetic operators to produce new individuals. • An external simulator is used to evaluate the fitness of the new individuals. • GP implementation in Coverage-Directed test Generation requires less expert knowledge compared to other methods (e.g. Bayesian Network).
- 5. Case study: XMOS multi- threaded microprocessor • Software Defined Silicon (SDS). • Up to 8 threads running simultaneously in one single core. • Experiment focuses on channel communication. • Channel communication design requires a number of threads to exercise the corner cases. However, the timing window to trigger corner cases, such as race conditions, is very narrow.
- 6. Implemented CDG loop • The experiment extends the existing MicoGP* program. • Expert knowledge is encoded in an instruction library. • An individual is a graph; the nodes in a graph are constructed from the basic building blocks in the library. • The extended MicroGP includes 2 crossover and 5 mutation operators. • A double looped system is used to enhance the performance of MicroGP. * MicroGP research group http://www.cad.polito.it/research/microgp.html
- 7. Encoding multi-threaded test code in GP • A test program can be represented by a graph; a node in a graph maps to a channel operation and a branch represents the content of a new thread.
- 8. Feedback measurements • Improves basic coverage measurements such as line coverage and branch coverage. • Minimises simulation cycles. • Minimises the main graph to encourage more threads in test code. • Balances the distribution of operations among the threads. • Increases operation on channel IO. • All feedback measurements are optimised together with different priority.
- 9. Experiment Results • Test code generated by MicroGP method is significantly better than human engineer and randomly generated sequences. • Actual line coverage improved to 94% and up to 50% cycle reduction. 12 345 678 901 234 567 890 123 456 789 65 70 75 80 Line Coverage Random Seed Percentage(%) 12 345 678 901 234 567 890 123 456 789 0 5000 10000 15000 20000 25000 30000 35000 Simulation Cycle Human Random MicroGP Random Seed UnitCycle