STM32 MCU Family
•
3 likes•2,060 views
The document provides an overview of the STM32 MCU family from STMicroelectronics. It discusses the key features such as an ARM Cortex-M3 core, Flash memory up to 512KB, SRAM up to 64KB, low power modes, timers, and communication peripherals. It also outlines the applications for industrial equipment, appliances, low power devices, and consumer electronics. Finally, it gives a high-level description of the system architecture and various peripherals including DMA, ADC, DAC, communication interfaces, and watchdogs.
![STM32 MCU Family ,[object Object]](https://image.slidesharecdn.com/ststm32mcufamily-110315001905-phpapp02/85/STM32-MCU-Family-1-320.jpg)
![Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
Recommended
More Related Content
What's hot
What's hot (20)
Similar to STM32 MCU Family
Similar to STM32 MCU Family (20)
More from Premier Farnell
More from Premier Farnell (20)
Recently uploaded
Recently uploaded (20)
STM32 MCU Family
- 3. The World of STM32
Editor's Notes
- Welcome to this module on STM32 MCU family from ST. This module will overview the STM32 MCU family and discuss the key features and applications of STM32 products.
- The ARM Cortex™-M3 processor is the generation of ARM processors for embedded systems. The advanced architectural features of the Cortex-M3 processor reduce memory size while delivering industry-leading performance in a small, power-efficient RISC core. It thus provides an ideal platform for the migration of many different applications around the world from legacy devices to the 32-bit microcontroller world.
- The STM32 family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at up to 72 MHz frequency, high-speed embedded Flash memories and SRAM, and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces, such as I2Cs, SPIs, and USARTs, one 12-bit ADC and the general-purpose timers. STM32 has two complete lines, Performance line and Access line. Both lines are pin-to pin and software-compatible.
- These features make the STM32 microcontroller family suitable for a wide rage of applications.
- STM32 has two complete lines, Performance line and Access line. Both lines are pin-to pin and software-compatible and offer excellent connectivity and control. The Performance line, STM32F103, operates at 72 MHz, with more on-chip RAM and peripherals. The Access line, STM32F101, operates at 36 MHz. With its Cortex-M3 core at 72 MHz, it is able to perform high-end computation. The Access line is the entry point of the STM32 family. It has the power of the 32-bit MCU but at a 16-bit MCU cost.
- The main system consists of five masters and three slaves. The five masters include Cortex-M3 core ICode bus, DCode bus, System bus and two general-pupose DMA. The three slaves include internal SRAM, internal Flash memory and AHB to APB bridges which connect all the APB peripherals.
- The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power. The voltage regulator is always enabled after Reset. To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
- The backup registers are implemented in the backup domain that remains powered on by VBAT when the VDD power is switched off. They are not reset when the device wakes up from Standby mode or by a system reset or power reset. In addition, the BKP control registers are used to manage the Tamper detection feature and RTC calibration.
- There are three types of reset, defined as system Reset, power Reset and backup domain Reset. A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain. A power reset is generated when PRO/PDR reset or existing standby mode occurs. Backup domain reset is generated when software is reset or V DD or V BAT power on, if both supplies have previously been powered off. Three different clock sources can be used to drive the system clock, HIS clock, HSE clock, and PLL clock. Each clock source can be switched on or off independently when it is not used, to optimize power consumption. After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.
- The RTC consists of two main units. The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode. The APB1 interface is clocked by the APB1 bus clock in order to interface with the APB1 bus. The RTC provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt.
- The STM32 has two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both Watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (40 kHz) and thus stays active even if the main clock fails. The window watchdog (WWDG) clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior.
- Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
- Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.
- The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.
- The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation.
- The SPI allows half/ full-duplex, synchronous, serial communication with external devices. The interface can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration. I 2 C bus Interface serves as an interface between the microcontroller and the serial I 2 C bus. It provides multimaster capability, and controls all I 2 C bus-specific sequencing, protocol, arbitration and timing. It supports standard and fast speed modes. It is also SMBus 2.0 compatible. The USART offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator.
- Thank you for taking the time to view this presentation on STM32 MCU family . If you would like to learn more or go on to purchase some of these devices, you can either click on the link embedded in this presentation, or simple call our sales hotline. For more technical information you can either visit the ST site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.