Paul Barcelona is an electrical engineer with over 20 years of experience in project management, digital design, systems design, and circuit card design. He has experience leading projects in commercial, military, and space applications. Currently, he is a senior engineer at Honeywell International where he has received awards for his leadership as a project manager.

1. PAUL BARCELONA
2457 Clubside Ct. #215, Palm Harbor, Fl. 34683
443.789.4455 • pbarcelona62 @ g m ail.com
Summary
Electrical Engineer with a varied background in digital electronics design, systems design and
circuit card design. Project Manager with experience and ability oversee and participate in projects
ranging in size from small to medium size projects while ensuring timely completion of project
deadlines all while remaining on or under budget.
Highlights
• Project Management experience.
• Commercial, Military and Space design
experience.
• Systems/CCA design experience.
• HDL design experience, DSP
implementations.
• ASIC/FPGA Design/Verification experience.
• PMP Certification Candidate
Accomplishments
Nominated for Outstanding Engineers Award and received Project Leadership Award for leading a
development team during an obsolescence upgrade program. The Project Leadership Award is a
result of exceeding cost and schedule goals, and delighting the customer while maintaining
technical performance for multiple programs.
Professional Experience
Honeywell Intl, Clearwater Florida,
Sr. Engineer , June 2000 – Present
Project Manager for V22 VFG GCU FPGA Upgrade, a conversion project due to obsolescence. Lead
the Design and Verification team to success by meeting or exceeding all milestones on time and
within budget. Developed project operating system to track and report status on a weekly basis.
Developed product using SystemVerilog for design and UVM based verification. Mentored
engineers by guiding them through the Department processes as well as Design and Verification
processes.
Project Manager for SBIRS STE GDC FPGA. Lead the design and verification teams to success
meeting all milestones on time and on budget. Developed product using SystemVerilog for design
and UVM based verification. Mentored engineers by guiding them through the Department
processes for design and verification.
Project Manager to convert RI4000 Graphics Processor ASIC into a FPGA implementation. A two
phase approach was used by resurrecting and validating the procured IP from vendor followed by
upgrading design replacing obsolete interfaces. Statement of Work creation for subcontractor
procurement, developed coding guidelines, maintained schedule, setting priorities to both
verification and design engineers to maintain forward progress on all fronts. Program was
discontinued due to original IP issues to be migrated into FPGA to meet performance, cost and
schedule milestones.
Verification Lead Engineer for multiple FPGA verification environments for the CH47 program.
Challenges presented were the lack of requirements and minimal schedule commitments such
that the functional designers could use the verification environment for their respective
development. Met all functional and schedule goals for program deliverables.
Designed DSP applications for a radiation hardened FPGA device, Patent awarded. Breakdown of
customer requirements, partitioning, and the design and verification of the design. Generated
and presented training material for customers for the use of the FPGA based on lessons learned.

2. TTC Inc , Gaithersburg, Maryland
Contractor , January 2000 – May 2000
Developed VC3/VC12 Mapper FPGA for SDH application. Targeted for Altera APEX device, the
design performs both mapping and de-mapping for a VC3 container, DS3 and E3 tributaries, and
VC12 container, E1 tributary. Written in Verilog HDL an intelligent test bench wrapped the design
to automatically check functionality.
BitCom Inc , Gaithersburg, Maryland
Contractor , July 1999 – December 1999
Supported the final development of a quad port DS3 network card. Tested and debugged design
for operational characteristics leading to factory acceptance. Testing and debugging consisted
of extensive in lab testing with DS3 test equipment supported by simulation of code
enhancements to meet operational and performance requirements.
Hughes Network Systems , Gaithersburg, Maryland
Contractor, December 1998 – July 1999
Designed an eight-port OC-3c physical layer interface card for BX5000. Interfacing between 50
MHz Level 2 Utopia ports and optical transceivers the design incorporated proprietary
redundancy switching along with automatic protection switching implemented in a Xilinx Virtex
FPGA. Verilog HDL was used to develop the Xilinx device containing an I960 interface in support
of other ancillary functions required.
Orbital Sciences Corporation , Gaithersburg, Maryland
Senior Principal Engineer , July 1998 – November 1998
Lead Engineer for the upgrade of a TMS320C31 based controller. Upgrade included selection
and incorporation of new high density memory devices along with additional serial interfaces.
Schematic conversion to VHDL with required upgrades, simulated behaviorally and structurally.
Supported other programs debugging hardware and software related problems for platforms
containing the TMS320C31/2 processors.
Watkins- Johnson Company , Gaithersburg, Maryland
Product Development Section Head , September 1997 - June 1998
Section Head/Project Manager responsible for all aspects of existing product, upgrades,
enhancements, bug fixes, production issues. Generated process guidelines/checklists for:
Development of ASIC and FPGA designs using High Level Design Processes; Engineering Design
Reviews, and Engineering to PCB design transition. Supported multiple proposal efforts
capturing NRE enhancing the company's product offering.
Kaiser Electronics , San Jose, California
Principal Analog/Digital Engineer , September 1996 - September 1997
Project Manager for the development of a Video Processor for the F18E/F fighter jet. Responsible
for requirements flow down and implementation from specification to design of multiple devices.
RMS Technologies, Greenbelt, Maryland
Senior Systems Engineer , July 1995 - September 1996
Supported NASA Goddard Space Flight Center, systems and hardware lead for the development
of the Packet Data Analyzer System in a VME environment. The system receives spacecraft and
space station telemetry frame data in CCSDS compliant format. Designed the Data Comparison
circuit card which receives two data streams, synchronizes them and compares them in real time
capable of sustaining over 150Mbit per second data rates. Interfaces include serial links, CPU
and custom backplane. Verilog HDL and the Cadence CAE tools.
Lockheed Martin Services, Greenbelt, Maryland
Design and Development Section Head , September 1991- June 1995
Supported NASA Goddard Space Flight Center as Project Manager developing a high density,
space qualified, Multi-Chip Memory Modules developed by Texas Instruments, a two million dollar
development program. Responsible for outlining and tracking of subcontract technical and
Continued...

3. Paul Barcelona (cont.)
financial requirements. Designer of a space qualified bulk memory circuit card, using the Multi-
Chip Memory Modules, for the SMEX-SWAS Mission. Designed the downlink section for the SWAS
Spacecraft in accordance with CCSDS Recommendations. The experiment flew successfully on
STS-53. Lead engineer for the development of a ground support test station for the Space Shuttle
Special Payloads Hitchhiker Avionics Interface Assembly (AIA). System and digital designer, test
engineer for a test station development. Supervised all efforts for the writing of C test code and
hardware design and assembly. Supervised all efforts from design to assembly, testing and final
acceptance qualification for space flight.
Allied- Signal Aerospace, Bendix Communication Division , Towson, Maryland
Engineer , June 1989 - February 1991
ASIC designer for Identification Friend or Foe (IFF) system.
Hazeltine Corp./Emerson Electric , Greenlawn, New York
Engineer , March 1985 - June 1989
Designed and supported various Identification Friend or Foe (IFF) systems based on customer
specific requirements.
E DUCATION & CREDENTIALS
Associate of Applied Science, Electrical Engineering Technology (AASEET) , 1982
SUNY FARMINGDALE UNIVERSITY, Huntington, New York
Bachelor of Science, Electrical Engineering (BSEE) , 1985
MANHATTAN COLLEGE, Bronx, New York
Patent: Two-Dimension Digital Ratiometric Decoder, Patent No: 7,126,521 B2