1. RAJENDRA BARETO
Contact: +918123014199 | Email: raj_baretto@hotmail.com; rajendra.bareto@gmail.com
PROFILE SUMMARY
Versatile and result oriented professional with proven 16-years’ experience in Digital Signal Processing for Wireless and Wireline
product development. Experience in creating digital signal-processing algorithms using programs such as MatLab to exploit and
analyze digital signals. High level of technical experience in digital signal processing with the ability to work with low-level APIs,
hardware interface code, and embedded software and interrupts. Proven expertise in discussing with the sales and pre-sales
teams for feature enhancement and feasibility of the features in the product.
Excels in providing feasibility reports to the sales and management team regarding the new features customer and in-house
requirements. Possess in-depth understanding of the G-fast standard to implement on the new board. Displayed excellence in
assembly level implementation, optimization and debugging. Engaged in new product architecting in terms of hardware and
software. Innate experience in driver programming AFE, PA, ADC and DAC.
Core Competencies: Requirements Specifications, Feasibility Study, Memory & Code Optimizations, Debugging & Bugs Fixing,
New Product Architecting, Algorithms Design and Implementation, Driver Programming, Optimization and Debugging, Digital
Communication, Matlab Simulation, DSL State Machine Changes, Messages Sending, SBX Processor Instruction and Coding.
WORK EXPERIENCE
Qualcomm (Ikanos Communications ) Since May 2013
Fast Standard Implementation
Key Responsibilities:
 Serving as key DSP developer as part of a software development team that performs collaborative software development
tasks with other teams
 Researching, designing, developing, and deploying audio compression. Developing DSP algorithms and software for modem
in response to new signalsrequirements.
 Thriving in a collaborative environment and clearly communicating while confidently driving multiple projects across many
teams. Developing state-machinefor various phases of the standard.
 Shouldering accountability to develop and validate various stages using loopbacks and hardware equipment’s. Entrusting
with the accountability to debug and obtain system run to different phases and states of the DSL standard.
 Engaging in New AFE interface handling and establishing IFEand other hardwarerelated settings from the new processors.
 Measuring line noise during show-time and handling error failure handling during training. Handling AGC during various
states of the training.
 Evaluating new architecture, porting code on to the new processor and downloading code of the MIPS and SBX through
host. Verifying the FPGA functionality.
Projects in VNL Jul 2008 to May 2013
Sr. Technical Architect
Key Responsibilities:
 Headed the baseband Base-band & DSP controller team. Entrusted with the accountability to provide technical guidance to
the junior team members.
 Tracked the project development on weekly and monthly basis. Participated in technical discussions on the product
development with the overseas and domestic team members.
 Enhanced information architecture team accomplishments and competence by planning delivery of solutions. Identified
user requirements by researchingand analyzinguser needs, preferences, objectives,and workingmethods .
 Planned information architecture by studying the site concept, strategy, and target audience. Envisioned architectural
scheme, information structureand features, functionality,as well as user-interfacedesign.
 Validated information delivery by developing and completing usability test plans, evaluated traffic patterns, studied user
feedback and coordinated with Usability Specialists.
PROJECT UNDERTAKEN
 Extended cell development

2.  Scope: Provide detail design to receive signal upto 70 kms. Product architecture changes definition and impacts. RACH, TCH
and Packet data handling is done. Interface definition with the BSC to incorporate the extended users. Test using SMU and
CMU tool.
 Power Amplifier Handling for EPSK
 Scope: The power amplifier provided was mainly for the GMSK handling which works on constant envelope type. The
feedback loop was design such that the PA output received gets adjust for non-linearity of the EPSK signal and RMS value is
taken for calculation which then sets the PA to appropriategain.3-dB back-off was done to handlethe PAPR of 8-PSK.
 EGPRS Development
 Scope: Designing and implementing channel coding and modulation & DSP-Controller for scheduling. Reviewing RLC-MAC
design specs. Regression test as per specifications, with CMU300 for loop-back, with TEMS mobile for end-to-end testing
with RLC-MAC.
 Field Issues Handling
 Scope: Monitored signal not available at the BTS, Paging low success rate, SDCCH drop rates low, TCH drop rates, BTS
reboots and crashes.
 Customer Requirements
 Scope: Entrusted with the accountability to CSD feasibility, cell feasibility and design, FACCH and Repeated SACCH.
 AMR-FR Development
 Scope: Design AMR-FR codec’s. MIPs utilization of the AMR-FR. Integration of the channel coding feature with the BTS.
Testing of the feature using the CMU300 for loopback tests.
 Interference Cancellation Feasibility
 Scope: Studied various interference cancellation methods from IEEE- papers. Provide requirement specification to the team..
Detail analysis of the SAIC and constant envelope type of interferers.
 Multicarrier BTS
 Scope: Complexity analysis of multicarrier BTS. Evaluate complexity of DPD (Digital pre-distorters), IMD (intermodulation
distortions) for ACI (Adjacent channel Interference) in the Wideband system. Understanding of the LTE system for common
multicarrier platforms like GSM and WCDMA.
 GSM AMR HR and FR development, Senior Technical Lead, C, Matlab, TS201, Blackfin 543, Wincvs
 Scope: Testing the integration code on simulator platform and in-house simulation code with regression scripts for
conformance test as per the specs.
 GSM Performance improvements
 Scope: Tuning for improvement of Equalizer, Channel decoding, FACCH decoding, band filter to the best possible gain in FER
and BER under ACI/CCI.
 Cycles Optimization
 Scope: Optimization of DFSE algorithms on Tiger-Shark and Blackfin DSP. Optimize of DTX, interleave, De-inter-leaver and
puncturing & de-puncturing.
Projects in Ikanos communications
 Encapsulation and bring up of New AFE Chip, Senior Lead Firmware Engineer, Assembly, Unix, Matlab
 Scope: Worked on multi-core engines of xDSL product line. Porting of new AFE and bring-up- ADC, DAC, hybrid, initialization,
power up process, AFE clock & AGC gains.
 CPE Performance Improvement (Annex – A & M)
 Scope: AFE tuning at various levels in thehardware to improve the performance or data rates.
DELT (Dual Ended Line Testing)
 QLN: Quiet line noise to find the calibration factors required to achieve theoretical results as per the specifications.
 Hlog: proving compensation factor and front-end parameters tuning to get the compensation factor which achieved results
as per the specifications.
Projects in Ikanos Communications

3.  SELT (Single Ended line testing), Senior Design Engineer, C, Matlab MS VC, CVS, UNIX, VxWorks, Tornado IDE, Nucleus and
Tera-term, DLS 414
 LDM (Loop diagnostics mode) & DELT (dual ended loop transmission) for ADSL2+ & VDSL2
 Scope: C on MS Visual Studio, CVS & UNIX, Tera-term, DLS 414,Agilent spectrum analyzer.
 RFI-PSD masks: Increased the total PSD mask for VDSL2 from 28 to 128 on O-SIG & O-update messaging. Various RFIs were
introduced to suppress the carrier atpredefined frequencies.
 17-z Profile for VDSL2: Added profile to in the Vdsl2 standard based on the loop-length connected during GHS. This covers
the VDSL2 mode 17MHz based transmission and receptions.
Projects in Sasken
 UMTS Layer-1 Development, Client: Nortel Networks, Senior Design Engineer, C62xx TI DSP, C coding, Visual BBS, Clear
Case, TM100
 Scope: Adding features to the CEM and Designing, Implementing, Testing
 Epigon Media systems, WORLDSPACE Satellite Radio Receive, Matlab, C, VDSP3.0, May 2002 to May 2003
 Scope: The physical layer included Channel Decoding (). Multiplexing of the channel data. Descrambling, LPF, Decimation and
interpolation, Receive Filtering – simulation and implementation.
 Nuntius Systems: Algorithms & Design Engineer, Dec 2000 to June 2002
 Scope: Design, simulate and implement the baseband algorithms of WLAN-802.11b & WCDMA-UE.
 UMTS - Physical Layer Development, C, Matlab, TMS320C55xx
 Scope: Baseband design and implementation of the various below modules: Convolution Encoder, Viterbi Decoder of
Constraint Length 9, Block Inter-leaver and De-inter-leaver, Radio Frame Equalization and Segmentation, Rate Matching,
Cyclic encoder and decoder, Scrambler and Descrambler, Spreader/De-spreader, Simulation using matlab.
 Nuntius Systems Inc, USA, WLAN - 802.11b –PHY, C, Matlab
 Scope: Implementation and simulation of the below modules; DBPSK/DQPSK coding, 5.5 Mbps/11Mbps CCK modem, Symbol
Tracking,Carrier Synchronization,DFE-Decision feedback Equalizer,FWT,Spreader-De-spreaderand scramblerDescrambler.
EDUCATION
 B.E (Electronics & Communications Engineering), MIT-Manipal (MangaloreUniversity),1999
Technical Skills:
 C
 Matlab,Simulink,SPW
 Assembly
 xDSL, FAST
 W-CDMA
 WLAN
 MobileRadio
 MPEG/Voice Codec’s
 GSM/GPRS/EDGE
Product Architecture:
 Assembly: Blackfin, 532/535 TS201, ADSP2189 (16-bits), ASTEL DSP 2000(24-bits), TI - c62xx and Conexant dNova DSPs,
TCI64xx and SBX