1. EMS Solutions, Moving from Mind to Market
Contact: Arvind Kumar, Business Development Manager, arvind_kumar@pactroninc.com
2. EMS Solutions, Moving from Mind to Market
Profile
Pactron is a preeminent provider of engineering and
manufacturing services to the electronics industry. With
established expertise in the design and manufacture of
board level solutions, Pactron services a broad range
of industries including semiconductor, medical
devices, telecom, aerospace and defense. Pactron’s
integrated approach from design engineering through
manufacturing, all under one roof, yields dramatic
compression in time to market coupled with lowest total
cost of ownership for projects and programs to its
customers.
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About Pactron
Established in 1988
Headquarters in Santa Clara, CA
Engineering, Design & Manufacturing in Santa Clara
Support centers in Texas, China
Design & Manufacturing Support Centers in India
Employee Headcount : ~300
Registered to ISO9001 & ISO13485
System Level Solutions: Engineering, Design & Manufacturing
Long standing customer base
Semiconductor : Intel, Marvell, Texas Instruments, Cypress, LSI….
OEM’s : Hughes, DRS, Smith & Nephew, Avantis, Asante, Zonare
Medical….
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Pactron’s End to End Service
Board Level
Design & Engineering
Simulation
Analysis
PCBA Test
•Schematic Engineering
•Board Layout
•High Speed Simulation
•Mechanical Design
•FPGA, Firmware Development
•Ansoft HFSS - 3D
Modeling
•Sigrity Power SI and
Power DC
•HSPICE
•SpectraQuest
•PowerPlane Analysis
•Material Management
•Complex PCB Mfg.
•High Density Assembly
•Integrated Rework
•Functional
•Boundary Scan
•Flying Probe
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Design & Engineering Manufacturing
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Pactron Sample Designs
System/Evaluation
Boards
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System Design Expertise
Schematic Engineering Based on a Block Diagram or requirements from customer
Experience with the following interfaces:
DDR3/2/1, NAND, QDRII/II+, SDRAM, DRAM,SRAM, FIFOs, Intel’s QPI, PCIe Gen2/3, SATA
2.0/3.0, USB2/3 host and device implementation, Gigabit Ethernet, PCI, DVI, Display Port, VGA,
HDMI, LCD Interfaces, SPI, I2C, eMMC, SD, MMC, and etc
Power Supply Design
Design a power distribution system based on the requirements
Switching and Linear Regulators
Battery Charging and Monitoring Circuit
FPGA expertise
Experience with different FPGA implementation like Altera, Xilinx, Lattice and Actel
Ability to account for clock management, power requirement and I/O level setting for various
interfaces
Firmware/FPGA program development
Windows and Linux operating system firmware development
Low Level Device Driver Development for UBoot and Linux Kernel
Porting of Uboot, Linux Kernel, and rootFS into an embedded ARM processor
Boundary Scan Implementation
Design for testability by implementing boundary scan chain
Test Development and Debug
Validate customer BSDL file
Board Design and Signal Integrity Analysis
Constrained driven manual routing
Simulation of high speed buses using IBIS/HSpice models and recommend termination and routing
topology. Perform 3D modeling for any 3D structures on the board (via, connector)
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Enterprise Solid State Hard Drive
Marvell’s Flash Controller
2.5 inch Enterprise SSD
Power Hold-up circuitry using Tantalum Caps
Power Back-up circuitry using Super Caps
SATA Interface – 6 Gb/s
On-Board Discrete DDR3 Devices
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PCI–Ex8 HBA
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• Hardware Architecture,
Schematic & Component
Engineering
• Power Supply/Distribution
Design
• Super Cap Back up
Design
• SI ,PI & Thermal Analysis
• MTBF
• E-DVT
• M-DVT
• Protocol Compliance :
PCI-E, SAS, SATA
• FCC, CE Compliance
• DFM, DFA
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High Speed Transceivers 6.4 gbps
per pair
Altera Stratix IV GX FPGAs
CPLD to support PFL programming
3D Modeling using HFSS for high
speed channel
Hybrid Material – Rogers 4350 and
Nelco
28 layers with blind via technology
because of back to back BGAs
High Dense Placement with 0201
components
5% impedance tolerance on high
speed traces
High Speed I/O Board
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XAUI 3.125 gbps per pair, PCIe, Gigabit Ethernet, DDR2 SODIMM
Broadcom Switch for XAUI Interface, Cavium and Power PC
Processor, PCIe Switch, Altera CPLD for system management
Boundary Scan Implementation for testability
High Voltage Translation
Line Card
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PCIe Form-Factor Video Protocol Board
PCIe Gen-2 x1 Form Factor
2 DVI Ports
2 Display Ports
2 HDMI Ports
Gigabit Ethernet
Video Out BNC
Discrete DDR3
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Birchwood Development Kit
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The Birchwood System is a low power development/evaluation platform based on the high performance Marvell’s
Armada 300 88F6282 ARMv5TE compliant core with integrated 16 KB L1 Cache and 256 KB L2 cache that can run up
to 2.0 GHz. The system enables users to design and develop innovative embedded products based on the Marvell’s
88F6282 processor. The system has 512 MB (128 MB x 4) DDR3 RAM and 512 MB NAND Flash. The System can be
used by developers as is or Pactron can provide customized industrial designs, hardware and software for your
specific needs.
Features:
The system supports the following features:
•Linux-2.6.31.8 ARM Linux Kernel
•Ubuntu 9.04 Root File System
•16 bit DDR3 SDRAM running at 533 MHz clock rate
•8-bit 512 MB NAND flash boot support
•eSATA 3 Gbps data rate
•SATA 2.5” Hard Drive Interface 3 Gbps Data Rate
•4-bit SD Card Interface
•Two Gigabit Ethernet (10/100/1000 Mbps) ports
•Two PCIe x1 Interface (Standard and Mini-PCIe)
•Seven USB 2.0 Ports
•DVI Video Output
•2x16 Character LCD
•JTAG/UART0 Interface using Mini USB
•RS232/RS485 for UART1 and SMB Bus
Applications:
Single Board Computer
Proxy Server
Security
Point of Sale (PoS)
Industrial controller
Access Point
Routers
VPN
Storage
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Platform CustomizationPlatform Customization
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System Level design
The Ironwood is a low cost router based on Birchwood
.
07/10/13 Pactron Corporation 14
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VRM
Load (DUT) Top Side
Power Plane Noise Amplitude Plot
Noise @ 80MHz
Noise @ 310 MHz
Noise @ 420 MHz
Challenges
Layers - 32 layers
Thickness - 217 mil
Material – Rogers 4350 & FR4 (Hybrid)
SERDES 11Gbps
High Di/Dt and switching freq
Power Integrity Analysis
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Capacitors to be
optimized
Noise
Suppressing
Cap
Noise
Suppressing
Cap
Decoupling capacitor of BGA is
optimized for its location and
value to achieve target power
plane impedance.
Before Optimization
After Optimization
Decoupling Capacitor Optimization
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24 SERDES @ 10GHz
16 to SMA & 8 loopback
RO4350 & FR4
Return Loss > 10db @ 10 GHz
Challenges
Signal Integrity Analysis
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BGA Antipad Optimization in
inner layers for high speed
channels
SMA connector footprint optimization
TDR of the high speed channel
Simulation
Impedance discontinuity minimized at the
press fit connector side
DUT (BGA)
HighSpeedlanes@25GBps
HighSpeedlanes@25GBps
DUT (BGA footprint optimized)
Char Board to verify Interlaken Interface
DUT (BGA)
Serdes lanes to verify
10.3125Gbps operation
Airmax connector
footprint optimization to
minimize impedance
discontinuity
Contactor/Connector Footprint & Via Optimization
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Time Domain Analysis HSPICE by inputting the channel
s-parameter model and driver/reciever IBIS model.
Eye Diagram Analysis for High speed digital lines.
Time Domain & Eye Analysis
TDR of High speed traces
DDR DQ lane Voltage vs. Time plot with input PRBS pattern
To analyze reflection and ground bounce.
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Tools Used
•Ansoft HFSS
•Sigrity Power SI
•Synopsys HSPICE
•Cadence Sigxplorer
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Pactron Manufacturing
and Test Capability
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Capabilities
ISO 9001:2008 & ISO13485:2003
ESD controlled facility
4 fully automated SMT lines
• Rigid, Flex and Rigid Flex assemblies
• Board thickness ranging from 30 to 330 mils (52 layers max)
• Max board size 22 X 24”
• Fine pitch component down to 12 mils, 0201s
• BGA, uBGA re-ball and rework
Automated Optical Inspection & 3D X-Ray
Wave and Selective Wave solder
Aqueous and chemistry based closed loop wash systems
In house BGA/ CSP rework and re-ball capabilities
Cabelling / Box build and Mechanical Enclosures
Flying probe and function test capabilities
DFM/DFT
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Pactron - Manufacturing
Material verification & Control
• Measure and verify passive components before loading on the equipment
• Approved AVL, Alternates and part marking are available through MOS
Paperless factory
• Work instructions are provided in the form of visual aids, pictures etc.,
• Technicians have access to enter any feedback to a centralized system
Integrated Process control and tracking
In process Quality control
• AOI, In line QC, First article, QA
Test Management
All aspects of Process, Quality & Test are fully incorporated
using Aegis (Manufacturing Operations System)
IPC 610, J STD-001 certified
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Paperless Work Instructions
Board level
Traceability
Color coded
Visual aids
Work Instructions
Component
Information
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Defined Manufacturing Process
Each board on the shop floor
is identified using a unique Serial Number
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In-Process Quality
Boards are scanned at
each step of the
process
If defects occur they
are assigned to the
Serial number of the
board and the board is
tagged as failed
System doesn’t let the
boards continue until
the defect is fixed
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Test
Flying probe machines
• Locate Board Shorts
• Measure passive and active components like resistors, capacitors, relays,
diodes, etc on a loaded board
• For relay test the Coils are powered on and relay is tested for proper
switching continuity and functionality
• Current Leakage Measurements
• Increases test efficiency by testing thousands of nets in minutes
• With DFT able to obtain 80 % - 100 % coverage of boards.
Boundary Scan
• Assist in checking BGA to board continuity using JTAG scan connectivity
• Increase test coverage
Programming
• IC Programming of Eproms, FPGA programming like Xilinx/Altera
Functional Test Software/Hardware
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In Summary ~ Why Pactron?
• Ideal model for constantly evolving technology
•Broad Level of Engineering Support
•Integrated Engineering Expertise
•Flexible & Agile Manufacturing Strategy
• Integrated Design & Manufacturing
• Low volume Prototyping
• Medium to High Volume Support
•Strategic global presence
• US – Sunnyvale, Dallas
• Asia – India, China
•One Stop Shop for a Engineering & Manufacturing PCBA Project Requirement
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A Turn-Key Solutions Provider
High End Designs – Manufacturing - Final Test