• Designed a Network-On-Chip router circuit in cadence with facilities for error detection, error correction and a loopback module to route back data away from faulty routers at any port in the router. • Logic Synthesis of the written RTL code was done by Synopsys Design Compiler with our own library obtained from SiliconSmart ACE using the cadence spice netlists of our own standard cells. Applied DC-Tcl scripts for logic optimization with various design constraints. • Adopted Synopsys DC SPEF file for timing-driven placement in the layout. The router layout was auto-place & routed in Cadence Encounter APR from the LEF file format of our own cadence cell library. • Power reduction and timing closure was achieved through Synopsys Primetime and the chip operated at 1.86 GHz with low power consumption of 17.37mW.

1. THE UNIVERSITY OF TEXAS AT DALLAS
EECT/CE 6325 VLSI DESIGN
Fall 2016
PROJECT #6
ROUTER DESIGN
BY:
ILANGO JEYASUBRAMANIAN - 2021270958
MUKESH TRITH SWAIN - 2021288272
ADITYA MANISHBHAI MEHTA - 2021287096

2. GENERAL DESCRIPTION OF THE DESIGN
We have implemented a Verilog code for a simple router with four ports. Each port contains the following modules:
LOOPBACK MODULE:
The data comes in and goes out from each port only through this module block. The important
function of this block is to loopback the output into the input of the same port of the router, whenever the input
port of the corresponding destination router becomes unavailable.
FINITE STATE MACHINE MODULE:
This module is used to detect if the buffers are full at all the ports by checking the input data at
each port sequentially at every clock pulse. It works like a 4-bit sequence detector with bit ‘1’ when input is
present and bit ‘0’ when there is no input at the port. When a sequence of ’1111’ occurs, it means that the data is
present at all the four ports.Hence,it will make all the port unavailable signals id_un1,id_un2,id_un3,id_un4 to bit
‘1’ at the corresponding ports of the router to indicate port unavailability to the adjascent routers, as the buffers
are full.
This helps the other routers to route the data without losing the packets by making use of the loopback module.
ECC MODULE:
The data that comes inside the loopback module will first be sent to the hamming code error correction
module. This checks for any error in the bits and corrects if there is a single bit error. However, when it finds a
double bit error, the data will be discarded as the hamming code operation cannot correct two or more bit errors.
ROUTING-LOGIC:
We use XY routing algorithm here, where the data moves along the Y and X direction to reach the
destination. We have also use adaptive XY routing algorithm such as:
The SH-XY (Surround horizontal XY) mode is used when the router’s left or right neighbor is deac tivated.
Correspondingly, the mode SV-XY (Surround vertical XY) is used when the upper or lower neighbor of the router is
inactive.This helps in reducing the packet loss in the router.
INPUT-DATA:
We have used a 16 bit input ,with the last 4 bits representing the destination address.

3. ROUTER BLOCK - DIAGRAM:
LOOP BACK MODULE
Data_out2
Id_un2
Id_uno2
Data_in2
ECC
D_in2
BUFFER
D_chk2
D_out4
ROUTING
LOGIC
D_chk2
LOOPBACK MODULE
Data_in4 Data_out4
Id_uno4
Id_un4
ECC
D_in4
ROUTING
LOGIC
D_chk4
BUFFER
D_chk2
L
O
O
P
B
A
C
K
M
O
D
U
L
E
L
O
O
P
B
A
C
K
M
O
D
U
L
E
ECC
D_in1
ROUTING
LOGIC
D_chk2
ECC
D_in3
ROUTING
LOGIC
D_chk3
BUFFER
BUFFER
D_out2
D_out21 D_out23
D_out24
D_out13
D_out14
D_out12
D_out34
D_out31
D_out32
D_out43
D_out41
D_out42
D_out1
D_out3
Id_uno1
Data_in1
Id_un1
Data_out1
Id_uno3
Data_in3
Data_out3
Id_un3
PORT-1
PORT-3
PORT-4
PORT-2
FINITESTATE
MACHINEMODULE
Id_un2 Id_un3 Id_un4
Id_un1
D_chk1
D_chk2 D_chk3
D_chk4

4. CONNECTION BETWEEN MODULE ANDTESTBENCH:
BUFFER
DFF1
MODULE
R
O
U
T
E
R
M
O
D
U
L
E
lbm1
(LOOP
BACK
MODULE)
BUFFER
DFF2
MODULE
ECC2
ECC1
ECC4
BUFFER
DFF4
MODULE
lbm3
(LOOP
BACK
MODULE)
ECC3
BUFFER
DFF3
MODULE
lbm2
(LOOP
BACK
MODULE)
lbm4
(LOOP
BACK
MODULE)

5. CONNECTION BETWEEN MODULES:
ROUTE
LOGIC
1
ROUTE
LOGIC
1
R
O
U
T
E
R
M
O
D
U
L
E
ROUTE
LOGIC
3
ROUTE
LOGIC
4
FINITE STATE
MACHINE
MODULE

6. A
clk
D_out21
D_out31
D_out41
D_out12
D_out32
D_out42
D_out13
D_out23
D_out43
D_out14
D_out24
D_out34
Data_in1
id_uno1
Data_req_out1
Data_req_in1
Data_out1
D_in1
id_un1
Data_in2
id_uno2
Data_req_out2
Data_req_in2
Data_out2
D_in2
id_un2
Data_in3
id_uno3
Data_req_out3
Data_req_in3
Data_out3
D_in3
id_un3
Data_in4
id_uno4
Data_req_out4
Data_req_in4
Data_out4
D_in4
id_un4
D_out1
D_out2
D_out3
D_out4
D_chk1
D_chk2
D_chk3
D_chk4
ACK1
ACK2
ACK3
ACK4
R
O
U
T
E
R
M
O
D
U
L
E
R
O
U
T
E
R
T
E
S
T
B
E
N
C
H

7. LOOP-BACKMODULE BLOCK-DIAGRAM:
FINITE-STATE-MACHINE:
MUXDEMUX
D
flip
flop
D
flip
flop
Data_in
mux_outD_in D_loop
D_out
Data_out
D1
~id_uno
~id_uno
Data_req_in
Data_req_out
Dflipflop2
Dflipflop1
Dflipflop0
~Q[1]
Q[2]
I
Q[0]
Q[1]
~Q[2]
I
Q[0]
D[0]
D[1]
Q[1]
Q[2]
D[2]
~Q[2]
I
Q[1]
Q[2]
I
out
~Q[2]
I

8. HAMMING CODE ERROR CORRECTION MODULE:
module ECC(clk,A,ACK,B);
input clk;
input [15:0]A;
output reg [15:0] B;
reg [3:0] P;
output reg ACK;
reg i,P4;
integer j;
always@(posedge clk)
begin
P[0]<=A[0]^A[2]^A[4]^A[6]^A[8]^A[10];
P[1]<=A[1]^A[2]^A[5]^A[6]^A[9]^A[10];
P[2]<=A[3]^A[4]^A[5]^A[6];
P[3]<=A[7]^A[8]^A[9]^A[10];
P4<=A[0]^A[1]^A[2]^A[3]^A[4]^A[5]^A[6]^A[7]^A[8]^A[9]^A[10]^A[11];
if(A==16'h0000) begin
B <= 16'h0000;
end
else if(P==0 && P4==0) begin
ACK <=1'b1;
B <= A;
end
else if(P==0 && P4==1) begin
B[11]<=~A[11];
B <= A;
ACK <=1'b1;
end
else if(P!=0 && P4==1) begin
B[P-1]<=~A[P-1];
B <= A;
ACK <=1'b1;
end
else if(P!=0 && P4==0) begin
ACK <=1'b0;
B <=16'h0000;
end
end
endmodule

9. FLIP-FLOP MODULES:
module dff (q,d,clk);
input [15:0] d;
input clk;
output reg [15:0] q;
always @ (posedge clk)
begin
q <= d;
end
endmodule
module dff1(q,d1,d2,d3,clk);
input [15:0] d1,d2,d3;
input clk;
output reg [15:0] q;
always @ (posedge clk)
begin
if(d1!=16'b0000000000000000)
q <= d1;
else if(d2!=16'b0000000000000000)
q <= d2;
else
q <= d3;
end
endmodule
DEMUX MODULE:
module demux21(clk,D_loop,D1,D_out,sa);
input clk;
input [15:0] D_out;
input sa;
output reg [15:0] D1,D_loop;
always@(posedge clk)
begin
case(sa)
1'b0:
D_loop=D_out;
1'b1:
D1=D_out;
endcase
end
endmodule

10. LOOPBACK MODULE:
module lbm(D_out,id_uno,Data_in,Data_req_in,Data_req_out,Data_out,id_un,D_in,clk);
input clk;
input [15:0] D_out,Data_in;
input id_uno;
inout Data_req_out,Data_req_in;
output [15:0] Data_out,D_in;
output id_un;
wire sm,sd;
wire [15:0] mux_out,D1;
wire [15:0] D_loop;
assign Data_req_out =(D_out ==16'b0000000000000000)?1'b0:1'b1;
assign Data_req_in =(Data_in==16'b0000000000000000)?1'b0:1'b1;
assign sm = ~id_uno * Data_req_in;
assign mux_out=(sm==1'b0)? D_loop:Data_in;
dff b1(D_in,mux_out,clk);
assign sd = ~id_uno * Data_req_out;
demux21 a(clk,D_loop,D1,D_out,sd);
dff a1(Data_out,D1,clk);
endmodule
ROUTE-LOGIC-1 MODULE:
module routelogic1(clk,id_un2,id_un4,A,D_O1,D_chk,D_out1,D_out2,D_out3);
input clk;
input id_un2,id_un4;
input[3:0] A;
input [15:0] D_O1,D_chk;
output reg [15:0] D_out1,D_out2,D_out3;
always@(posedge clk)
begin
if(D_O1==D_chk) begin
if(id_un2!=1'b1) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if(id_un4!=1'b1) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
end
if(D_chk==16'h0000) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[15]!=A[3] && D_chk[15]==1'b1 ) begin
D_out1=16'h0000;

11. D_out2=16'h0000;
D_out3=D_chk;
end
else if( D_chk[15]!=A[3] && D_chk[15]==1'b0 ) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[14]!=A[2] && D_chk[14]==1'b1 ) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
else if( D_chk[14]!=A[2] && D_chk[14]==1'b0 )begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[13]!=A[1] && D_chk[13]==1'b1 ) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
else if( D_chk[11]!=A[0] && D_chk[11]==1'b1) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
end
endmodule
ROUTE-LOGIC-2 MODULE:
module routelogic2(clk,id_un1,id_un3,A,D_O2,D_chk,D_out1,D_out2,D_out3);
input clk;
input id_un1,id_un3;
input[3:0] A;
input [15:0] D_O2,D_chk;
output reg [15:0] D_out1,D_out2,D_out3;
always@(posedge clk)
begin
if(D_O2==D_chk) begin
if(id_un3!=1'b1) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if(id_un1!=1'b1) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
end

12. if(D_chk==16'h0000) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[15]!=A[3] && D_chk[15]==1'b1 ) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
else if( D_chk[14]!=A[2] && D_chk[14]==1'b1 ) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
else if(D_chk[13]!=A[1] && D_chk[13]==1'b1 ) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if(D_chk[13]!=A[1] && D_chk[13]==1'b0 ) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
else if( D_chk[12]!=A[0] && D_chk[12]==1'b1) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[12]!=A[0] && D_chk[12]==1'b0 ) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
end
endmodule
ROUTE-LOGIC-3 MODULE:
module routelogic3(clk,id_un2,id_un4,A,D_O3,D_chk,D_out1,D_out2,D_out3);
input clk;
input id_un4,id_un2;
input [3:0] A;
input [15:0] D_O3,D_chk;
output reg [15:0] D_out1,D_out2,D_out3;
always@(posedge clk)
begin
if(D_O3==D_chk) begin
if(id_un4!=1'b1) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;

13. end
else if(id_un2!=1'b1) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
end
if(D_chk==16'h0000) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[15]!=A[3] && D_chk[15]==1'b1 ) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[15]!=A[3] && D_chk[15]==1'b0 ) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
else if( D_chk[14]!=A[2] && D_chk[14]==1'b1 ) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[14]!=A[2] && D_chk[14]==1'b0 ) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
else if( D_chk[13]!=A[1] && D_chk[13]==1'b0 ) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
else if( D_chk[12]!=A[0] && D_chk[12]==1'b0) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
end
endmodule

14. ROUTE-LOGIC-4-MODULE:
module routelogic4(clk,id_un1,id_un3,A,D_O4,D_chk,D_out1,D_out2,D_out3);
input clk;
input id_un1,id_un3;
input[3:0] A;
input [15:0] D_O4,D_chk;
output reg [15:0] D_out1,D_out2,D_out3;
always@(posedge clk)
begin
if(D_O4==D_chk) begin
if(id_un1!=1'b1) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if(id_un3!=1'b1) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
end
if(D_chk==16'h0000) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[15]!=A[3] && D_chk[15]==1'b0 ) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
else if( D_chk[14]!=A[2] && D_chk[14]==1'b0 ) begin
D_out1=16'h0000;
D_out2=D_chk;
D_out3=16'h0000;
end
else if( D_chk[13]!=A[1] && D_chk[13]==1'b0 ) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[13]!=A[1] && D_chk[13]==1'b1 ) begin
D_out1=16'h0000;
D_out2=16'h0000;
D_out3=D_chk;
end
else if( D_chk[12]!=A[0] && D_chk[12]==1'b0) begin
D_out1=D_chk;
D_out2=16'h0000;
D_out3=16'h0000;
end
else if( D_chk[12]!=A[0] && D_chk[12]==1'b1 ) begin
D_out1=16'h0000;
D_out2=16'h0000;

15. D_out3=D_chk;
end
end
endmodule
FSM MODULE:
module FSM(id_un1,id_un2,id_un3,id_un4,D_chk1,D_chk2,D_chk3,D_chk4,clk);
input clk;
input [15:0] D_chk1,D_chk2,D_chk3,D_chk4;
output reg id_un1, id_un2, id_un3, id_un4;
reg I;
reg out;
reg [2:0] Q;
reg [2:0] Q1;
reg [2:0] D;
initial begin
Q=3'b000;
end
always@(posedge clk)
begin
case(Q)
3'b000:
begin
if(D_chk1!=16'h0000)
I<=1'b1;
else
I<=1'b0;
end
3'b100:
begin
if(D_chk2!=16'h0000)
I<=1'b1;
else
I<=1'b0;
end
3'b010:
begin
if(D_chk3!=16'h0000)
I<=1'b1;
else
I<=1'b0;
end
3'b110:
begin
if(D_chk4!=16'h0000)
I<=1'b1;
else
I<=1'b0;
end

16. 3'b001:
begin
if(D_chk1!=16'h0000)
I<=1'b1;
else
I<=1'b0;
end
endcase
out <= Q[1] * Q[2] * I;
D[0] <= Q[1] * Q[2] * I;
D[1] <= (((~Q[1]) * Q[2] * I) + ((~Q[0]) * Q[1] * (~Q[2]) * I)) ;
D[2] <= (~Q[2]) * I;
Q1=D;
case(Q1)
3'b000:Q=3'b000;
3'b100:Q=3'b100;
3'b010:Q=3'b010;
3'b110:Q=3'b110;
3'b001:Q=3'b001;
endcase
if(out == 1'b1)
begin
id_un1=1'b1;
id_un2=1'b1;
id_un3=1'b1;
id_un4=1'b1;
end
else
begin
id_un1=1'b0;
id_un2=1'b0;
id_un3=1'b0;
id_un4=1'b0;
end
end
endmodule

17. ROUTER MAIN_MODULE:
module Router(
input [3:0] A,
input clk,
inout [15:0] D_out21,D_out31,D_out41,
inout [15:0] D_out12,D_out32,D_out42,
inout [15:0] D_out13,D_out23,D_out43,
inout [15:0] D_out14,D_out24,D_out34,
input [15:0] Data_in1,
input id_uno1,
inout Data_req_out1,Data_req_in1,
output [15:0] Data_out1,D_in1,
output id_un1,
input [15:0] Data_in2,
input id_uno2,
inout Data_req_out2,Data_req_in2,
output [15:0] Data_out2,D_in2,
output id_un2,
input [15:0] Data_in3,
input id_uno3,
inout Data_req_out3,Data_req_in3,
output [15:0] Data_out3,D_in3,
output id_un3,
input [15:0] Data_in4,
input id_uno4,
inout Data_req_out4,Data_req_in4,
output [15:0] Data_out4,D_in4,
output id_un4,
inout [15:0] D_out1,D_out2,D_out3,D_out4,
inout [15:0] D_chk1,D_chk2,D_chk3,D_chk4,
output ACK1,ACK2,ACK3,ACK4
);
dff1 a1(D_out1,D_out21,D_out31,D_out41,clk);
lbm l1(D_out1,id_uno1,Data_in1,Data_req_in1,Data_req_out1,Data_out1,id_un1,D_in1,clk);
ECC e1(clk,D_in1,ACK1,D_chk1);
routelogic1 r1(clk,id_uno2,id_uno4,A,D_out1,D_chk1,D_out12,D_out13,D_out14);
dff1 a2(D_out2,D_out12,D_out32,D_out42,clk);
lbm l2(D_out2,id_uno2,Data_in2,Data_req_in2,Data_req_out2,Data_out2,id_un2,D_in2,clk);
ECC e2(clk,D_in2,ACK2,D_chk2);
routelogic2 r2(clk,id_uno1,id_uno3,A,D_out2,D_chk2,D_out23,D_out24,D_out21);
dff1 a3(D_out3,D_out13,D_out23,D_out43,clk);
lbm l3(D_out3,id_uno3,Data_in3,Data_req_in3,Data_req_out3,Data_out3,id_un3,D_in3,clk);
ECC e3(clk,D_in3,ACK3,D_chk3);
routelogic3 r3(clk,id_uno2,id_uno4,A,D_out3,D_chk3,D_out34,D_out31,D_out32);
dff1 a4(D_out4,D_out14,D_out24,D_out34,clk);
lbm l4(D_out4,id_uno4,Data_in4,Data_req_in4,Data_req_out4,Data_out4,id_un4,D_in4,clk);
ECC e4(clk,D_in4,ACK4,D_chk4);
routelogic4 r4(clk,id_uno1,id_uno3,A,D_out4,D_chk4,D_out41,D_out42,D_out43);
FSM f1(id_un1,id_un2,id_un3,id_un4,D_chk1,D_chk2,D_chk3,D_chk4,clk);
Endmodule

18. ROUTER TEST_BENCH:
module router_tb;
// Inputs
reg [3:0] A;
reg clk;
reg [15:0] Data_in1;
reg id_uno1;
reg [15:0] Data_in2;
reg id_uno2;
reg [15:0] Data_in3;
reg id_uno3;
reg [15:0] Data_in4;
reg id_uno4;
// Outputs
wire [15:0] Data_out1;
wire [15:0] D_in1;
wire id_un1;
wire [15:0] Data_out2;
wire [15:0] D_in2;
wire id_un2;
wire [15:0] Data_out3;
wire [15:0] D_in3;
wire id_un3;
wire [15:0] Data_out4;
wire [15:0] D_in4;
wire id_un4;
wire ACK1;
wire ACK2;
wire ACK3;
wire ACK4;
// Bidirs
wire [15:0] D_out21;
wire [15:0] D_out31;
wire [15:0] D_out41;
wire [15:0] D_out12;
wire [15:0] D_out32;
wire [15:0] D_out42;
wire [15:0] D_out13;
wire [15:0] D_out23;
wire [15:0] D_out43;
wire [15:0] D_out14;
wire [15:0] D_out24;
wire [15:0] D_out34;
wire Data_req_out1;
wire Data_req_in1;
wire Data_req_out2;
wire Data_req_in2;
wire Data_req_out3;
wire Data_req_in3;
wire Data_req_out4;
wire Data_req_in4;
wire [15:0] D_out1;
wire [15:0] D_out2;
wire [15:0] D_out3;
wire [15:0] D_out4;
wire [15:0] D_chk1;
wire [15:0] D_chk2;
wire [15:0] D_chk3;

19. wire [15:0] D_chk4;
// Instantiate the Unit Under Test (UUT)
Router uut (
.A(A),
.clk(clk),
.D_out21(D_out21),
.D_out31(D_out31),
.D_out41(D_out41),
.D_out12(D_out12),
.D_out32(D_out32),
.D_out42(D_out42),
.D_out13(D_out13),
.D_out23(D_out23),
.D_out43(D_out43),
.D_out14(D_out14),
.D_out24(D_out24),
.D_out34(D_out34),
.Data_in1(Data_in1),
.id_uno1(id_uno1),
.Data_req_out1(Data_req_out1),
.Data_req_in1(Data_req_in1),
.Data_out1(Data_out1),
.D_in1(D_in1),
.id_un1(id_un1),
.Data_in2(Data_in2),
.id_uno2(id_uno2),
.Data_req_out2(Data_req_out2),
.Data_req_in2(Data_req_in2),
.Data_out2(Data_out2),
.D_in2(D_in2),
.id_un2(id_un2),
.Data_in3(Data_in3),
.id_uno3(id_uno3),
.Data_req_out3(Data_req_out3),
.Data_req_in3(Data_req_in3),
.Data_out3(Data_out3),
.D_in3(D_in3),
.id_un3(id_un3),
.Data_in4(Data_in4),
.id_uno4(id_uno4),
.Data_req_out4(Data_req_out4),
.Data_req_in4(Data_req_in4),
.Data_out4(Data_out4),
.D_in4(D_in4),
.id_un4(id_un4),
.D_out1(D_out1),
.D_out2(D_out2),
.D_out3(D_out3),
.D_out4(D_out4),
.D_chk1(D_chk1),
.D_chk2(D_chk2),
.D_chk3(D_chk3),
.D_chk4(D_chk4),
.ACK1(ACK1),
.ACK2(ACK2),
.ACK3(ACK3),
.ACK4(ACK4)
);
always begin
#2 clk=~clk;

20. end
initial begin
// Initialize Inputs
/*
A = 4'b1000;
clk = 1'b0;
Data_in1 = 16'b0011111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b1000111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0101111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0100;
Data_in1 = 16'b1000111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b1000111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0011111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0000;
Data_in1 = 16'b0001111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0001111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b01001111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0011111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0001;
Data_in1 = 16'b0011111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b0000111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0000111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0010;
Data_in1 = 16'b0011111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b0001111001100111;

21. id_uno3 = 1'b0;
Data_in4 = 16'b0001111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0011;
Data_in1 = 16'b0011111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b0001111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0001111001100111;
id_uno4 = 1'b0;
*/
A = 4'b1000;
clk = 1'b0;
Data_in1 = 16'b0011111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b1000111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0101111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0100;
Data_in1 = 16'b1000111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b1000111001100111;
id_uno2 = 1'b1;
Data_in3 = 16'b1000111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0011111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0101;
Data_in1 = 16'b0011111001110111;
id_uno1 = 1'b0;
Data_in2 = 16'b1001111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b01001111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0110111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0001;
Data_in1 = 16'b0000111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b0000111001100111;

22. id_uno3 = 1'b0;
Data_in4 = 16'b0011111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0010;
Data_in1 = 16'b0011111001100111;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b0001101001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0001111001100111;
id_uno4 = 1'b0;
#50
A = 4'b0011;
Data_in1 = 16'b0011111001100100;
id_uno1 = 1'b0;
Data_in2 = 16'b0101111001100111;
id_uno2 = 1'b0;
Data_in3 = 16'b0001111001100111;
id_uno3 = 1'b0;
Data_in4 = 16'b0001111001100111;
id_uno4 = 1'b0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
end
endmodule

23. SIMULATION:
X1
2
3
4
A=0010
X1
2
3
4
A=0100
X
0000
X1
2
3
4
A=0000
X
1
2
3
4
A=1000
X1
2
3
4
A=0101
X1
2
3
4
A=0011
X1
2
3
4
A=0001
X1
2
3
4
A=0110
X1
2
3
4
A=1001
X1
2
3
4
A=1100
X1
2
3
4
A=1101
X1
2
3
4
A=1011
X1
2
3
4
A=1010
X1
2
3
4
A=1110
X1
2
3
4
A=1111
1
2
3
4
A=0111
1-error
1-error 2-error

24. SIMULATION-1-GREEN PATH DESCRIPTION:
The router address is given as ‘A’ in the simulation.We have manually changed the value
of router address ‘A’ to represent 16 routers as shown in the above simulation diagram.
Let us consider a 16 bit data “0011111001100111” at the input of the 1st
port of the router
with address A=’1000’ as Data_in1.This data passes through the loopback module and comes out as D_in1 and gets
checked by Error correction module(ECC) and comes out as D_chk1.
Since the last 4 bits represent the destination router address, the last 16th bit in the data
is checked against the first bit in the current router address A='1000’ in the routing-logic of port 1.Since it finds to
differ as bit ‘0’, it will be routed to the 2nd
port to go up ,according to XY routing algorithm. This will cause the data
to enter in the 4th
port of the router with address A=’0100’.
The data is again sent to the loopback module and Error correction module(ECC) in a
similar manner at the port-4 of the router with address A= ‘0100’.The routing logic in port 4 will find that the 16th
bit
matches with the first bit of the destination address. Hence, it will compare the next 15th
bit in the data and finds it
to differs as bit ‘0’.Hence,the data is routed to port-2 of the router with address A=‘0100’, causing the data to enter
in the port-4 of the router with address A=’0000’.
The routing logic in port4 of the router with address A=’ 0000’, finds that the first two bits
(16th
and 15th
bit) of the destination address in data matches with the first 2 bits of the current router address
A=’0000’.Hence,the routing will be done based on the 14th
bit in the destination address of the data and the third bit
in the current router address. This causes the data to be sent through the third port of the router with address
A=’0000’ and enters at the 1st
port of the router with address A=’ 0001’.This continues till it reaches the destination
router with address A=’0011’.
MAPPED VERILOG SIMULATION:

25. BEHAVORIAL VERILOG SIMULATION:

26. SIMULATION-2-RED PATH DESCRIPTION:
In this simulation ,we manually made the 4th
port of the router with router address
A=’0000’ as unavailable by making the id_uno2(port unavailability indication signal) coming from port 4 of router
with address A=’0000’ to port-2 of the router with address A=’0100’.Hence, the data coming out from port-2 of the
router with router address A=’0100’ is made to loopback inside port-2 of the same router as Data_in2.
This data then comes out as D_chk2 from the ECC(error correction module) of port 2 of
the same router. The routing logic then compares the D_chk2 with the D_out2 and finds that it matches, which
indicates that a loopback has taken place.
According to XY adaptive routing algorithm, when there is a port unavailability at the
adjacent router along port-2, we have to route the data either to port-3 or port-1.Hence, we send out the data to
port-3 of router with address A=’0100’.
We also made errors at the data bit and parity bit manually at the inputs of port-1 of the
router with router address A=’0101’ and port-1 of router with address A=’0010’ which gets corrected by the ECC
hamming code correction module. However a two bit errored data at the input of port-1 of the router with router
address ‘0011’ cannot be corrected and will just get discarded.
MAPPED VERILOG SIMULATION:

28. BEHAVORIAL VERILOG SIMULATION:

29. In the last screenshot we can find that the finite state machine module, used to check if data is present in all the
ports and if the buffers are full, outputs the link unavailable signals id_un1,id_un2,id_un3,id_un4 as ‘1’ ,as data is
present at all ports.
However, In the last router 0011, due to a two bit error, the data will be discarded in the 1st
input port. This will
cause the FSM module to make all the unavailable signals ‘0’ as only three valid inputs are present now in the
router(0011) and (Acknowledgment signal)ACK1 of port1 also becomes ‘0’ as data is discarded.

30. CELL REPORT:

31. ROUTER_LAYOUT:
ROUTER_SCHEMATIC:

32. DRC_CHECK:
LVS_CHECK:

33. STATIC_TIMING _ANALYSIS USING PRIMETIME SYNOPSYS TOOL:
For a clock pulse of 95ns, the setup time was met at 0.98ns and the hold time was met at 0.17ps
with output capacitance of 25fF and slew rate of 60ps.
SETUP_TIME_REPORT:

34. POWER_REPORT:
HOLD_TIME_REPORT:

35. TRADE_OFFS IN THE DESIGN:
1. The heights of all the cells were increased to 8.65um to abide with the standard cell
structure of same height in all the cells.
2. In the D-FLIP-FLOP design, we had to make use of Metal-2 connections to provide clock
gate inputs, which helped us to reduce the height of the cell.
3. In order to avoid DRC errors in automatic place and route and to meet the design rules of
cadence encounter tool, we made use of fillers and pitch distance of 0.48um in the design.