This document discusses hardware description languages (HDL) and digital circuit design using HDLs. It covers HDL modeling techniques including gate-level, dataflow, and behavioral modeling. Examples of basic digital components like half adders, full adders, multiplexers are shown in HDL code. The document also discusses HDL simulation, synthesis, and the commonly used HDL languages VHDL and Verilog.

1. CS 8351- DIGITAL PRINCIPLES
AND SYSTEM DESIGN
II YEAR CSE & IT
HDL- HARDWARE DESCRIPTIVE
LANGUAGE
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2. HDL- HARDWARE DESCRIPTIVE
LANGUAGE
A Hardware Descriptive Language
describes the hardware of the digital
system in a Textual Form.
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3. HDL
DESIGN
FLOW
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4. Logic Simulation
• A Simulator interprets the HDL
description given by the designer and
produces a readable output, like a Timing
Diagram, that predicts how the hardware
will behave before it is actually
fabricated.
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5. TEST BENCH
A Testbench is a HDL Program used as
a stimulus to test the functionality of
the design
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6. LOGIC SYNTHESIS
Logic Synthesis is the process of deriving a list
of components and their interconnections
from the model of a digital system described
in HDL.
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7. Two HDL Languages
• VHDL- VHSIC HDL – Very High Speed
Integrated Circuit HDL
• Verilog HDL
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8. HALF ADDER:
Verilog PROGRAM FOR HALF ADDER:
module halfadder (a,b, sum,carry);
input a,b;
output sum,carry;
xor G1(sum,a,b);
and G2(carry,a,b);
endmodule
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9. FULL ADDER:
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10. PROGRAM FOR FULL ADDER:
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire a1,a2,a3;
xor G0(sum,a,b,c);
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11. PROGRAM FOR FULL ADDER:
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire a1,a2,a3;
xor G0(sum,a,b,c);
and G1(a1,a,b);
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12. PROGRAM FOR FULL ADDER:
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire a1,a2,a3;
xor G0(sum,a,b,c);
and G1(a1,a,b);
and G2(a2, b,c);
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13. PROGRAM FOR FULL ADDER:
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire a1,a2,a3;
xor G0(sum,a,b,c);
and G1(a1,a,b);
and G2(a2, b,c);
and G3(a3,a,c);
or G4(carry,a1,a2,a3);
endmodule
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14. PROGRAM FOR HALF SUBTRACTOR:
module halfsubtractor(a,b,borrow,difference);
input a,b;
output borrow,difference;
wire a1;
xor G1(difference,a,b);
not G2(a1,a)
and G3(borrow,a1,b);
endmodule
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15. FULL SUBTRACTOR:
module fullsubtractor(a,b,c,borrow,difference);
input a,b,c;
output borrow,difference;
wire a0,a1,a2,a3;
xor G1(difference,a,b,c);
not G2(a0,a)
and G3(a1,a0,b);
and G4(a2,b,c);
and G5(a3,a0,c);
or G6(borrow,a1,a2,a3);
endmodule
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16. User Defined Primitives
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17. GATE DELAYS
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18. K.BALAJI, AP/ECE, SSMCE

19. HDL MODELS (OR)
MODELING TECHNIQUES
• Gate Level Modeling- It uses Logic Gates
• Data Flow Modeling- It Uses ‘operators’ and
Keyword ‘Assign’
• Behavioral Modeling- It uses Keyword
‘Always’ and assignments using the Truthtable
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20. MULTIPLEXER
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21. Gate Level Modeling code for
Multiplexer
module mux(S1,S0,I0,I1,I2,I3,Y);
input S1,S0,I0,I1,I2,I3;
output Y;
wire m1,m0,a1,a2,a3,a4;
not
G1(m1,S1),
G2(m0,S0);
and
G3(a1,I0,m1,m0),
G4(a2,I1,m1,S0),
G5(a3,I2,S1,m0),
G6(a4,I3,S1,S0);
or G7(Y,a1,a2,a3,a4);
endmodule
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22. DataFlow Modeling for Multiplexer
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23. Behavioral Modeling for Multiplexer
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24. K.BALAJI, AP/ECE, SSMCE

25. K.BALAJI, AP/ECE, SSMCE

26. K.BALAJI, AP/ECE, SSMCE

27. K.BALAJI, AP/ECE, SSMCE

28. REFERENCES:
1. M. Morris R. Mano, Michael D. Ciletti,
―Digital Design: With an Introduction to the
Verilog HDL, VHDL, and SystemVerilog‖, 6th
Edition, Pearson Education, 2017.
2.Digital Principles and System Design, D.Edwin
Das, Trisea Publisher
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