N-gram IDF: A Global Term Weighting Scheme Based on Information Distance (WWW...Masumi Shirakawa
A deck of slides for "N-gram IDF: A Global Term Weighting Scheme Based on Information Distance" (Shirakawa et al.) that was presented at 24th International World Wide Web Conference (WWW 2015).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
N-gram IDF: A Global Term Weighting Scheme Based on Information Distance (WWW...Masumi Shirakawa
A deck of slides for "N-gram IDF: A Global Term Weighting Scheme Based on Information Distance" (Shirakawa et al.) that was presented at 24th International World Wide Web Conference (WWW 2015).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
ON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAMIJCSEA Journal
Two-level logic minimization is a central problem in logic synthesis, and has applications in reliability analysis and automated reasoning. This paper represents a method of minimizing Boolean sum of products function with binary decision diagram and with disjoint sum of product minimization. Due to the symbolic representation of cubes for large problem instances, the method is orders of magnitude faster than previous enumerative techniques. But the quality of the approach largely depends on the variable ordering of the underlying BDD. The application of Binary Decision Diagrams (BDDs) as an efficient approach for the minimization of Disjoint Sums-of-Products (DSOPs). DSOPs are a starting point for several applications. The use of BDDs has the advantage of an implicit representation of terms. Due to this scheme the algorithm is faster than techniques working on explicit representations and the application to large circuits that could not be handled so far becomes possible. Theoretical studies on the influence of the BDDs to the search space are carried out. In experiments the proposed technique is compared to others. The results with respect to the size of the resulting DSOP are as good or better as those of the other techniques.
Analysis of LDPC Codes under Wi-Max IEEE 802.16eIJERD Editor
The LDPC codes have been shown to be by-far the best coding scheme capable for transmitting message over noisy channel. The main aim of this paper is to study the behaviour of LDPC codes on under IEEE 802.16e guidelines. The rate- ½ LDPC codes have been implemented on AWGN channel and the result shows that they can be used on such channels with low BER performance. The BER can be further minimized by increasing the block length.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Cooperative underlay cognitive radio assisted NOMA: secondary network improve...TELKOMNIKA JOURNAL
In this paper, a downlink scenario of a non-orthogonal multiple access (NOMA) scheme with power constraint via spectrum sensing is considered. Such network provides improved outage performance and new scheme of NOMA-based cognitive radio (CR-NOMA) network are introduced. The different power allocation factors are examined subject to performance gap among these secondary NOMA users. To evaluate system performance, the exact outage probability expressions of secondary users are derived. Finally, the dissimilar performance problem in term of secondary users is illustrated via simulation, in which a power allocation scheme and the threshold rates are considered as main impacts of varying system performance. The simulation results show that the performance of CR-NOMA network can be improved significantly.
INDUCTIVE LEARNING OF COMPLEX FUZZY RELATIONijcseit
The objective of this paper to investigate the notion of complex fuzzy set in general view. In constraint to a
traditional fuzzy set, the membership function of the complex fuzzy set, the range from [0.1] extended to a
unit circle in the complex plane. In this article the comprehensive mathematical operations on the complex
fuzzy set are presented. The basic operation of complex fuzzy set such as union, intersection, complement
of complex fuzzy set and complex fuzzy relation are studied. Also vector aggregation and fuzzy relation
over the complex fuzzy set are discussed. Two novel operations of complement and projection for complex
fuzzy relation are introduced.
Comparison of Turbo Codes and Low Density Parity Check CodesIOSR Journals
Abstract-The most powerful channel coding schemes, namely, those based on turbo codes and LPDC (Low density parity check) codes have in common principle of iterative decoding. Shannon’s predictions for optimal codes would imply random like codes, intuitively implying that the decoding operation on these codes would be prohibitively complex. A brief comparison of Turbo codes and LDPC codes will be given in this section, both in term of performance and complexity. In order to give a fair comparison of the codes, we use codes of the same input word length when comparing. The rate of both codes is R = 1/2. However, the Berrou’s coding scheme could be constructed by combining two or more simple codes. These codes could then be decoded separately, whilst exchanging probabilistic, or uncertainty, information about the quality of the decoding of each bit to each other. This implied that complex codes had now become practical. This discovery triggered a series of new, focused research programmes, and prominent researchers devoted their time to this new area.. Leading on from the work from Turbo codes, MacKay at the University of Cambridge revisited some 35 year old work originally undertaken by Gallagher [5], who had constructed a class of codes dubbed Low Density Parity Check (LDPC) codes. Building on the increased understanding on iterative decoding and probability propagation on graphs that led on from the work on Turbo codes, MacKay could now show that Low Density Parity Check (LDPC) codes could be decoded in a similar manner to Turbo codes, and may actually be able to beat the Turbo codes [6]. As a review, this paper will consider both these classes of codes, and compare the performance and the complexity of these codes. A description of both classes of codes will be given.
Mit203 analysis and design of algorithmssmumbahelp
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ON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAMIJCSEA Journal
Two-level logic minimization is a central problem in logic synthesis, and has applications in reliability analysis and automated reasoning. This paper represents a method of minimizing Boolean sum of products function with binary decision diagram and with disjoint sum of product minimization. Due to the symbolic representation of cubes for large problem instances, the method is orders of magnitude faster than previous enumerative techniques. But the quality of the approach largely depends on the variable ordering of the underlying BDD. The application of Binary Decision Diagrams (BDDs) as an efficient approach for the minimization of Disjoint Sums-of-Products (DSOPs). DSOPs are a starting point for several applications. The use of BDDs has the advantage of an implicit representation of terms. Due to this scheme the algorithm is faster than techniques working on explicit representations and the application to large circuits that could not be handled so far becomes possible. Theoretical studies on the influence of the BDDs to the search space are carried out. In experiments the proposed technique is compared to others. The results with respect to the size of the resulting DSOP are as good or better as those of the other techniques.
Analysis of LDPC Codes under Wi-Max IEEE 802.16eIJERD Editor
The LDPC codes have been shown to be by-far the best coding scheme capable for transmitting message over noisy channel. The main aim of this paper is to study the behaviour of LDPC codes on under IEEE 802.16e guidelines. The rate- ½ LDPC codes have been implemented on AWGN channel and the result shows that they can be used on such channels with low BER performance. The BER can be further minimized by increasing the block length.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Cooperative underlay cognitive radio assisted NOMA: secondary network improve...TELKOMNIKA JOURNAL
In this paper, a downlink scenario of a non-orthogonal multiple access (NOMA) scheme with power constraint via spectrum sensing is considered. Such network provides improved outage performance and new scheme of NOMA-based cognitive radio (CR-NOMA) network are introduced. The different power allocation factors are examined subject to performance gap among these secondary NOMA users. To evaluate system performance, the exact outage probability expressions of secondary users are derived. Finally, the dissimilar performance problem in term of secondary users is illustrated via simulation, in which a power allocation scheme and the threshold rates are considered as main impacts of varying system performance. The simulation results show that the performance of CR-NOMA network can be improved significantly.
INDUCTIVE LEARNING OF COMPLEX FUZZY RELATIONijcseit
The objective of this paper to investigate the notion of complex fuzzy set in general view. In constraint to a
traditional fuzzy set, the membership function of the complex fuzzy set, the range from [0.1] extended to a
unit circle in the complex plane. In this article the comprehensive mathematical operations on the complex
fuzzy set are presented. The basic operation of complex fuzzy set such as union, intersection, complement
of complex fuzzy set and complex fuzzy relation are studied. Also vector aggregation and fuzzy relation
over the complex fuzzy set are discussed. Two novel operations of complement and projection for complex
fuzzy relation are introduced.
Comparison of Turbo Codes and Low Density Parity Check CodesIOSR Journals
Abstract-The most powerful channel coding schemes, namely, those based on turbo codes and LPDC (Low density parity check) codes have in common principle of iterative decoding. Shannon’s predictions for optimal codes would imply random like codes, intuitively implying that the decoding operation on these codes would be prohibitively complex. A brief comparison of Turbo codes and LDPC codes will be given in this section, both in term of performance and complexity. In order to give a fair comparison of the codes, we use codes of the same input word length when comparing. The rate of both codes is R = 1/2. However, the Berrou’s coding scheme could be constructed by combining two or more simple codes. These codes could then be decoded separately, whilst exchanging probabilistic, or uncertainty, information about the quality of the decoding of each bit to each other. This implied that complex codes had now become practical. This discovery triggered a series of new, focused research programmes, and prominent researchers devoted their time to this new area.. Leading on from the work from Turbo codes, MacKay at the University of Cambridge revisited some 35 year old work originally undertaken by Gallagher [5], who had constructed a class of codes dubbed Low Density Parity Check (LDPC) codes. Building on the increased understanding on iterative decoding and probability propagation on graphs that led on from the work on Turbo codes, MacKay could now show that Low Density Parity Check (LDPC) codes could be decoded in a similar manner to Turbo codes, and may actually be able to beat the Turbo codes [6]. As a review, this paper will consider both these classes of codes, and compare the performance and the complexity of these codes. A description of both classes of codes will be given.
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A new efficient fpga design of residue to-binary converterVLSICS Design
In this paper, we introduce a new 6n bit Dynamic Range Moduli set { 22n, 22n + 1, 22n – 1} and then present
its associated novel reverse converters. First, we simplify the Chinese Remainder Theorem in order to
obtain an efficient reverse converter which is completely memory less and adder based. Next, we present a
low complexity implementation that does not require the explicit use of modulo operation in the conversion
process and we demonstrate that theoretically speaking it outperforms state of the art equivalent reverse
converters. We also implemented the proposed converter and the best equivalent state of the art reverse
converters on Xilinx Spartan 6 FPGA. The experimental results confirmed the theoretical evaluation. The
FPGA synthesis results indicate that, on the average, our proposal is about 52.35% and 43.94% better in
terms of conversion time and hardware resources respectively.
RADIAL BASIS FUNCTION PROCESS NEURAL NETWORK TRAINING BASED ON GENERALIZED FR...cseij
For learning problem of Radial Basis Function Process Neural Network (RBF-PNN), an optimization
training method based on GA combined with SA is proposed in this paper. Through building generalized
Fréchet distance to measure similarity between time-varying function samples, the learning problem of
radial basis centre functions and connection weights is converted into the training on corresponding
discrete sequence coefficients. Network training objective function is constructed according to the least
square error criterion, and global optimization solving of network parameters is implemented in feasible
solution space by use of global optimization feature of GA and probabilistic jumping property of SA . The
experiment results illustrate that the training algorithm improves the network training efficiency and
stability.
Local Model Checking Algorithm Based on Mu-calculus with Partial OrdersTELKOMNIKA JOURNAL
The propositionalμ-calculus can be divided into two categories, global model checking algorithm
and local model checking algorithm. Both of them aim at reducing time complexity and space complexity
effectively. This paper analyzes the computing process of alternating fixpoint nested in detail and designs
an efficient local model checking algorithm based on the propositional μ-calculus by a group of partial
ordered relation, and its time complexity is O(d2(dn)d/2+2) (d is the depth of fixpoint nesting, n is the
maximum of number of nodes), space complexity is O(d(dn)d/2). As far as we know, up till now, the best
local model checking algorithm whose index of time complexity is d. In this paper, the index for time
complexity of this algorithm is reduced from d to d/2. It is more efficient than algorithms of previous
research.
Building data fusion surrogate models for spacecraft aerodynamic problems wit...Shinwoo Jang
Abstract. This work concerns a construction of surrogate models for a specific aerodynamic data base. This data base is generally available from wind tunnel testing or from CFD aerodynamic simulations and contains aerodynamic coefficients for different flight conditions and configurations (such as Mach number, angle-of-attack, vehicle configuration angle) encountered over different space vehicles mission. The main peculiarity of aerodynamic data base is a specific design of
experiment which is a union of grids of low and high fidelity data with considerably different sizes. Universal algorithms can’t approximate accurately such significantly non-uniform data. In this work a fast and accurate algorithm was developed which takes into account different fidelity of the data and special design of experiments.
Implementation of Low-Complexity Redundant Multiplier Architecture for Finite...ijcisjournal
In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is
employed in applications like cryptography for data encryption and decryptionto deal with discrete
mathematical andarithmetic structures. The proposedmultiplier utilizes a redundant representation because
of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized
using Xilinx VerilogHDL. It is evident from the simulation results that the multiplier has significantly low
area and power when compared to the previous structures using the same representation.
Improved noisy gradient descent bit-flipping algorithm over Rayleigh fading ...IJECEIAES
Gradient descent bit flipping (GDBF) and its many variants have offered remarkable improvements over legacy, or modified, bit flipping decoding techniques in case of decoding low density parity check (LDPC) codes. GDBF method and its many variants, such as noisy gradient descent bit flipping (NGDBF) have been extensively studied and their performances have been assessed over multiple channels such as binary symmetric channel (BSC), binary erasure channel (BEC) and additive white Gaussian noise (AWGN) channel. However, performance of the said decoders in more realistic channels or channel conditions have not been equally studied. An improved noisy gradient descent bit flipping algorithm is proposed in this paper that optimally decodes LDPC encoded codewords over Rayleigh fading channel and under various fade rates. Comparing to NGDBF method, our proposed decoder provides substantial improvements in both error performance of the code, and in the number of iterations required to achieve the said error performance. It subsequently reduces the end-to-end latency in applications with low or ultra-low latency requirements.
Multi-carrier Equalization by Restoration of RedundancY (MERRY) for Adaptive ...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated and less complexity also involved by the simulation of the DST-DMT system.
ON RUN-LENGTH-CONSTRAINED BINARY SEQUENCESijitjournal
A class of binary sequences, constrained with respect to the length of zero runs, is considered.
For such sequences, termed (d, k)-sequences, new combinatorial and computational results
are established. Explicit expressions for enumerating (d, k)-sequences of finite length are
obtained. Efficient computational procedures for calculating the capacity of a (d, k)-code are
given. A simple method for constructing a near-optimal (d, k)-code is proposed. Illustrative
numerical examples demonstrate further the theoretical results.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A lexisearch algorithm for the Bottleneck Traveling Salesman ProblemCSCJournals
The Bottleneck Traveling Salesman Problem (BTSP) is a variation of the well-known Traveling Salesman Problem in which the objective is to minimize the maximum lap (arc length) in the tour of the salesman. In this paper, a lexisearch algorithm using adjacency representation for a tour has been developed for obtaining exact optimal solution to the problem. Then a comparative study has been carried out to show the efficiency of the algorithm as against existing exact algorithm for some randomly generated and TSPLIB instances of different sizes.
Design and implementation of Parallel Prefix Adders using FPGAsIOSR Journals
Abstract: Adders are known to have the frequently used in VLSI designs. In digital design we have half adder and full adder, main adders by using these adders we can implement ripple carry adders. RCA use to perform any number of addition. In this RCA is serial adder and it has commutation delay problem. If increase the ha&fa simultaneously delay also increase. That’s why we go for parallel adders(parallel prefix adders). IN the parallel prefix adder are ks adder(kogge-stone),sks adder(sparse kogge-stone),spaning tree and brentkung adder. These adders are designd and implemented on FPGA sparton3E kit. Simulated and synthesis by model sim6.4b, Xilinx ise10.1.
SOLVING OPTIMAL COMPONENTS ASSIGNMENT PROBLEM FOR A MULTISTATE NETWORK USING ...ijmnct
Optimal components assignment problem subject to system reliability, total lead-time, and total cost constraints is studied in this paper. The problem is formulated as fuzzy linear problem using fuzzy membership functions. An approach based on genetic algorithm with fuzzy optimization to sole the presented problem. The optimal solution found by the proposed approach is characterized by maximum reliability, minimum total cost and minimum total lead-time. The proposed approach is tested on different examples taken from the literature to illustrate its efficiency in comparison with other previous methods.
Similar to Compact binary-tree-representation-of-logic-function-with-enhanced-throughput- (20)
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
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Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
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UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
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1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
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Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
1. World Academy of Science, Engineering and Technology
International Journal of Computer, Information Science and Engineering Vol:1 No:4, 2007
Compact Binary Tree Representation of Logic
Function with Enhanced Throughput
Padmanabhan Balasubramanian, Cemal Ardil
International Science Index 4, 2007 waset.org/publications/6263
Abstract—An effective approach for realizing the binary tree
structure, representing a combinational logic functionality with
enhanced throughput, is discussed in this paper. The optimization in
maximum operating frequency was achieved through delay
minimization, which in turn was possible by means of reducing the
depth of the binary network. The proposed synthesis methodology
has been validated by experimentation with FPGA as the target
technology. Though our proposal is technology independent, yet the
heuristic enables better optimization in throughput even after
technology mapping for such Boolean functionality; whose reduced
CNF form is associated with a lesser literal cost than its reduced
DNF form at the Boolean equation level. For cases otherwise, our
method converges to similar results as that of [12]. The practical
results obtained for a variety of case studies demonstrate an
improvement in the maximum throughput rate for Spartan IIE
(XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA logic
families by 10.49% and 13.68% respectively. With respect to the
LUTs and IOBUFs required for physical implementation of the
requisite non-regenerative logic functionality, the proposed method
enabled savings to the tune of 44.35% and 44.67% respectively, over
the existing efficient method available in literature [12].
Keywords—Binary logic tree, FPGA based design, Boolean
function, Throughput rate, CNF, DNF.
I. INTRODUCTION
T
issue of performance enhancement has been a subject
matter of much research [1] [2] [3] [4] [5]. Also the
relevance of FPGAs based on LUTs in the last decade has
fostered numerous efforts in finding effective methods to
minimize and decompose functions. This paper deals with a
novel technology-independent synthesis methodology to
realize compact and throughput enhanced binary tree
structures for combinational logic circuits, by way of reducing
the logic depth. A number of techniques mentioned in [7] [8]
[9] are technology-independent and aim at reducing the logic
depth of the binary tree representing a Boolean network by
restructuring. Directed acyclic directed graphs (DAG) are
generally used to effectively represent single output
combinational logic circuit functionality. A rooted DAG may
be unfolded to a tree in such a way that no multiple-fanout
nodes exist, except for the primary circuit inputs. Each
internal node is labeled with a logical operator, AND and/or
HE
Padmanabhan Balasubramanian is with the School of Computer Science,
The University of Manchester, Manchester, MAN M13 9PL UK (phone: +44161-275 6294; e-mail: spbalan04@gmail.com, padmanab@cs.man.ac.uk).
Cemal Ardil is with the National Academy of Aviation, Baku,
Azerbaijan (e-mail: cemalardil@gmail.com).
OR, although other operators are also used depending upon
the functionality. In this work, we are primarily concerned
with function representations employing just these two types
of Boolean operations. A labeled edge (dot appearing on an
edge) in a DAG or a binary tree would correspond to a logical
inversion or negation operation. Let us have a reasonable and
valid assumption that all DAGs are reduced and that
isomorphism is not exhibited in the sub-DAGs.
Tree-height reduction was indeed proposed [6] in the scope
of compiler optimization, for code generation in
multiprocessor systems. Given the underlying inherent
complexity of the problem, timing optimization is sought
after, after the size of the Boolean network representing the
circuit has been reduced. Even extraction of kernels, that can
be shared, may lead to an increase in the depth of the network
as an associated effect. This makes it clear that sharing logic is
not always deemed to be a good approach, when considering
the issue of timing optimization. A technique that performs
logic decomposition during technology mapping has been
proposed in [10] [11]. However, the accuracy of this approach
is traded off for a higher computational cost. A recent activity
[12] addresses the issue of delay improvement through
functional decomposition. It actually builds on logic bidecomposition of Boolean functions [13] [14] and also uses
weak algebraic factorization operations. It implicitly relies
upon OR disjunction for functional bi-decomposition. Then it
combines this strategy with tree-height reduction of resulting
Boolean expressions. Though it leads to enhancement in
performance, vis-à-vis achieving logic depth reduction, the
quasi-algebraic decomposition was normally performed on the
minimized disjunctive normal form (DNF) [15], by iteratively
applying a combination of associative, distributive and
commutative (ACD) laws.
The remaining portion of this paper is organized as follows.
In section 2, we introduce a novel terminology, namely the
description set of a Boolean term and give its definition.
Section 3 elucidates the proposed method by means of an
illustrative example and compares it with the solution
obtained using the ACD based algorithm [12] at both the
technology-independent and technology-dependent phases.
Section 4 depicts the simulation results obtained for several
Boolean functions. A comparison of the methods in terms of
the maximum operating frequency achievable for the designs
is given in this section. The resource utilization summary is
also listed in this section. Finally, we make the concluding
remarks in the next section.
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II. DESCRIPTION SET OF A BOOLEAN TERM
A new terminology is proposed, namely the description set
of a Boolean term (sum term or product term). The description
set of a sum term [product term], shall be represented by the
notation D(Si) [D(Pi)].
D(Si) specifies the set of all literals in their actual form, that
the particular sum term Si is dependent upon for its evaluation
to a logic value of ‘0’ and D(Pi) indicates the set of all literals
in their respective form, that a product term Pi depends upon
for its evaluation to a logic value of ‘1’.
For e.g. let a sum-of-disjoint products (SoDP) function be,
Z = AC’DE + B’FG’, where there are two disjoint product
terms; P1 = AC’DE and P2 = B’FG’. Hence D(P1) = {A,
C’,D,E} and D(P2) = {B’,F,G’}.
The description set for a Boolean function would then be
the union of the description sets of all its individual terms. For
the above example, it is given by, D(Z) = D(P1) ∪ D(P2).
International Science Index 4, 2007 waset.org/publications/6263
III. ILLUSTRATION OF PROPOSED HEURISTIC
Let us take an arbitrary logic function, F to describe the
effectiveness of our proposal. Let F(Q,R,S,T,U,V,W) be
described by the following minimized expression,
F = TRU+TRV+ST’W+SU+SV+QT’W+QU+QV
(1)
Using the ACD based heuristic as described in [12], two
logically equivalent and irredundant reduced expressions are
obtained as follows,
F = (TR)·(U+V)+(Q+S)·(T’W+U+V)
(2)
F = (TR+Q+S)·(U+V)+(T’W)·(Q+S)
be combined with just one another different product term at
the end.
As a further generalization, it can be intuitively observed
that if the total number of distinct product terms in the reduced
two-level representation of a logic function is ‘n’; whether ‘n’
is ‘odd’ or ‘even’; the total number of set union operations
required to be performed would be O[n(n-1)/2].
Now we make a decision with regard to grouping those
terms, whose degree of literal matching is the highest, as
determined by the cardinality of the union of the description
set of all possible combinations of two unique Boolean terms.
Therefore for (4), we find that S1 and S2 can be combined
using the distributive law; similarly S3 and S4 are candidates to
be combined using the same axiom. After applying the D rule
for the appropriate terms of (4), which could be grouped, we
get the following reduced expression,
F = (TR+S+Q)·(T’W+U+V)
(5)
Comparing (2) [also (3)] and (5), we find that there is a
savings of 20% in terms of literal count. After representing the
tree structures for (2) and (5) in accordance with the DAG
specification and with sharing of nodes permitted, we observe
that there is a reduction in the number of operators and logic
depth by 12.5% and 25%, for the latter in comparison with the
former. Without node sharing, and for the worst case
realization, the respective savings for the proposed method
would be 22.22% and 40% respectively.
The binary tree representation with node sharing for (1),
given by (2), is shown in fig. 1. The symbols
and
denote Boolean AND and Boolean OR operators respectively
and these are referred to as atomic operators (AO) [16].
(3)
Both the above Boolean equations (2) and (3) have the
same input literal cost. The reduced conjunctive normal form
(CNF) equivalent for (1) is given by,
F = (T+S+Q)·(R+S+Q)·(T’+U+V)·(W+U+V)
(4)
For (4), we could write D(S1) = {T,S,Q}, D(S2) = {R,S,Q},
D(S3) = {T’,U,V} and D(S4) = {W,U,V}. We perform the
union of the description set of a sum term with all other sum
terms of (4) and we get the following: D(S1) ∪ D{S2}= {S,Q},
D(S1) ∪ D(S3) = { }, D(S1) ∪ D(S4) = { }, D(S2) ∪ D(S3) =
{ }, D(S2) ∪ D(S4) = { } and D(S3) ∪ D(S4) = {U,V}. We
now enumerate the cardinality of the above union and thereby
obtain | D(S1) ∪ D(S2) | = 2, | D(S1) ∪ D(S3) | = 0, | D(S1) ∪
D(S4) | = 0, | D(S2) ∪ D(S3) | = 0, | D(S2) ∪ D(S4) | = 0 and
| D(S3) ∪ D(S4) | = 2.
In general, for a function whose minimized two-level CNF
expression contains ‘k’ product terms, the first product term,
say, P1 could be combined with (k-1) different product terms,
the second product term, P2 could be combined with (k-2)
distinct product terms till the (k-1)th product term, which could
Fig. 1 Binary tree representation for (1) based on ACD heuristic
Theoretically speaking, the maximum operating frequency
for fig. 1, given as a reciprocal of the longest path delay or
critical path delay is given by,
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3. World Academy of Science, Engineering and Technology
International Journal of Computer, Information Science and Engineering Vol:1 No:4, 2007
1
t AN D + 3 tO R
f m ax =
=
1
2 t AN D + 2 tO R
(6)
For representation without duplication of nodes and with no
node sharing, the upper bound on the maximum frequency is,
f
m
a x
=
1
2 t
A
N
D
+
(7)
3 t
O
R
International Science Index 4, 2007 waset.org/publications/6263
Fig. 1 is characterized by a maximum logic depth of 4
(specified by the number of nodes in the longest path from
any of the primary inputs to a primary output for a MISO
function) and maximum operating frequencies of 89.847 MHz
and 101.626 MHz for technology mapping with Spartan IIE
(XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA
logic families as targets. The binary tree structure consumed 5
basic logic elements (LUTs of FPGA) and 16 input-output
buffers for physical realization.
The binary logic tree representation corresponding to (5) is
depicted by fig. 2.
Fig. 2 Binary tree representation for (1) based on proposed method
As seen above, this tree representation requires less number
of nodes than fig. 1 and the theoretical upper bound on the
maximum throughput rate is given by the expression,
fm
ax
=
t
A N D
1
+ 2 tO R
=
1
2 t AN D + tO R
(8)
The maximum logic depth of the tree structure is 3 and the
highest operating frequency for Spartan IIE and Spartan 3
FPGA logic families is found to be 99.009 MHz and 118.203
MHz respectively. Also the structural representation required
3 basic logic elements and 9 input-output buffers for
implementation with the above technology targets.
For this particular case study, we find that the throughput
rate is increased by 10.19% and 16.31% for the FPGA target
families in the above order. With respect to the basic logic
elements and input-output buffers needed for technology
mapping, corresponding savings of 40% and 43.75% has
resulted for the proposed procedure over that of [12].
IV. SIMULATION MECHANISM AND PRACTICAL RESULTS
Various combinational logic functions in canonical form of
various types were considered to substantiate the theoretical
claims by validating with experimental results. The
functionalities in PLA format were first minimized using a
commercial industry standard two-level logic minimizer, such
as ESPRESSO [17] and they are listed in Table 5 (made
available as an appendix).
The binary tree structures highlighting the BDAG
representation for the combinational circuits were realized
using the ACD rules based methodology described in [12].
VHDL coding was done for all the functions using structural
modeling style with gate-level primitives strictly conforming
to the binary DAG specification. The detailed design summary
and timing reports were obtained after post place and route
stage. The maximum operating frequency of the different
designs was then determined as a reciprocal of the maximum
combinational logic path delay.
The reduced conjunctive normal forms for the functions can
be obtained by two methods; either by running a direct sumof-products to product-of-sums subroutine or by considering
the complementary phase of the function and a
straightforward conversion to reduced product-of-sums
expression could be done. Infact, a high level language
implementation of the modified Quine-McCluskey’s method
for two-level logic minimization [18] can also be used in this
regard. Next, the description set for the different product
terms corresponding to each and every function was obtained
as per the definition given in section 2. Set union operations
were then performed on the different sets and the candidates
suitable for grouping were found according to the method
explained in section 3. Distributive axiom was applied, so that
the function now tends to comprise reduced, compact and
read-once functionality for the sub-functions, though not in
the original function. Then the tree representation was created
using the basic atomic operators and VHDL coding was done
using a similar modeling style. The design summary and
timing reports were obtained after the placement and routing
phase.
The simulations were all performed with Xilinx project
navigator suite targeting Spartan IIE and Spartan 3 FPGA
boards. The Spartan FPGA logic families are ideally suited for
gate-level designs [19].
Table 1 gives a description of the comparison between the
two schemes in terms of the logical operators required and
literal count. Table 2 shows the maximum throughput rate for
the synthesized tree representations corresponding to the
desired Boolean functionality, based on the two different
methods. Table 3 gives the amount of basic logic elements
utilized (BEL) for the different techniques and Table 4 gives
an account of the input-output buffers (IOBUF) utilized for
the two schemes.
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5. World Academy of Science, Engineering and Technology
International Journal of Computer, Information Science and Engineering Vol:1 No:4, 2007
Z2911
Z3010
Z3110
Z3215
Z3311
Z3411
Z3514
Total
7
8
7
13
8
11
9
239
4
4
5
6
4
4
5
133
7
8
7
13
8
11
9
239
4
4
5
6
4
4
5
133
TABLE IV
INPUT-OUTPUT BUFFERS REQUIRED FOR THE TWO SCHEMES
Spartan IIE
Spartan 3
(XC2S50E-7FT256)
(XC3S50-4PQ144)
Function ID
ACD_BDAG P_BDAG ACD_BDAG P_BDAG
9
15
19
11
19
11
Z411
International Science Index 4, 2007 waset.org/publications/6263
Z15
Z27
Z39
25
13
25
13
Z58
Z69
Z77
Z88
Z96
Z108
Z115
Z127
Z136
Z149
Z158
Z166
Z1710
Z189
Z199
Z208
Z2110
Z2210
Z2311
Z2412
Z2516
Z2612
Z2710
Z288
Z2911
Z3010
Z3110
Z3215
Z3311
Z3411
Z3514
Total
18
15
11
16
11
18
8
16
9
17
19
9
27
14
21
16
24
18
22
34
38
34
18
16
22
24
18
37
19
33
24
694
10
11
9
10
8
10
7
9
8
11
10
8
12
11
11
9
11
11
12
13
17
13
11
9
12
11
11
17
13
13
16
384
18
15
11
16
11
18
8
16
9
17
19
9
27
14
21
16
24
18
22
34
38
34
18
16
22
24
18
37
19
33
24
694
10
11
9
10
8
10
7
9
8
11
10
8
12
11
11
9
11
11
12
13
17
13
11
9
12
11
11
17
13
13
16
384
7
9
9
15
7
9
possible by way of reducing the logic depth in a binary logic
tree representation is discussed in this paper. A fair degree of
correlation is observed between the depth of the Boolean
network at the technology-independent stage represented by a
tree and the practical critical delay parameter obtained
experimentally; however, it turns out to be contrary in some
cases after the technology-mapping phase. The approach
seems to yield optimization in the throughput rate for a wide
variety of problems, which tend to have compact conjunctive
normal forms in comparison with disjunctive normal forms,
with the degree of compactness measured in terms of literal
count at the Boolean equation level.
The effectiveness of our contribution is evident from
improved results of reachability along the computationally
intensive path. Through extensive simulation studies, we infer
that the proposed methodology is promising, as it enables
higher operating frequency and less resource utilization
(FPGA resources) in parallel for significant number of case
studies. We have successfully addressed the issues of delay
improvement and area reduction, highlighted in [12], by
exploring the available design space and achieved
enhancement in performance.
Before technology mapping, with respect to the reduced
expressions governing the actual logic description, we find
that in terms of the atomic operators and input literal count,
the proposed procedure enabled savings of 26.29% and 38.4%
respectively. From the experimental results obtained, we find
that the average improvement in performance (measured in
terms of maximum operating frequency) has been 10.49% and
13.68% for Spartan IIE and Spartan 3 FPGA logic family
targets respectively. The corresponding average decrease in
LUTs for the logic families stated in the above order has been
the same and is around 44.35%. Based on the number of
input-output buffers required for physical realization of the
desired functionality, the proposed method effected mean
savings to the tune of 44.67% for both the logic families.
For functions with DNF forms more compact than its CNF
forms, the proposed heuristic returns the same results as that
of [12], while for the contrary, the approach enables decent
enhancement in throughput rate, whilst ensuring minimum
resource utilization. The approach is pragmatic and results in
tree representations for non-regenerative logic functions,
which promise improved performance, evident from several
problem cases considered in this work.
ACKNOWLEDGMENT
The authors would like to thank Mrs. Prathibha for her
assistance in this work.
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This paper deals with a technology-independent synthesis
methodology for combinational logic functionality that
typically precedes the technology-mapping phase. An
effective technique to address the important issue of
throughput enhancement via, timing optimization, made
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International Journal of Computer, Information Science and Engineering Vol:1 No:4, 2007
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Available: http://www.xilinx.com/support/mysupport.htm#Spartan-3
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7. World Academy of Science, Engineering and Technology
International Journal of Computer, Information Science and Engineering Vol:1 No:4, 2007
APPENDIX
Function ID
TABLE V
LOGIC FUNCTION SPECIFICATION
Minimized two-level logic obtained using ESPRESSO [17]
Z15
agb+agc+abf+fc
Z2
7
afe+afd+afg+aec+cd+cg+abe+bd+bg
Z39
dbfcg+dbfgh+dbfi+dceg+eh+ei+adcg+ah+ai
Z411
mnqst+mnqu+mnqv+mnqw+msto+uo+vo+wo+mstp+up+vp+wp+mstr+ur+vr+wr
Z58
ijn+ijo+ijp+kin+ko+kp+inl+ol+pl+min+mo+mp
Z69
pqrsuvw+pqrsx+puvwt+xt
Z77
mnpq+mnpr+mnqo+ro
Z8
8
qrwx+qru+qrv+qwxs+su+sv+qwxt+tu+tv
Z96
bgc+bgd+bge+abc+ad+ae
Z108
abe+abf+abg+abh+aec+fc+gc+hc+aed+fd+gd+hd
Z115
stw+s’vu+uw
tru+trv+t’ws+us+vs+t’wq+qu+qv (FOR ILLUSTRATION)
Z136
International Science Index 4, 2007 waset.org/publications/6263
Z127
pmr+p’qn+nr+p’qo+or
Z149
abch+abci+a’fgh+dh+di+a’fge+eh+ei
Z15
8
pmx+pmy+qp’v+qx+qy+p’vw+wx+wy+p’vu+ux+uy
Z166
mnr+m’pqo+or
Z1710
mnv+mnw+mnx+m’uq+vq+wq+xq+m’ur+vr+wr+xr+m’us+vs+ws+xs+m’ut+vt+wt+xt
Z189
abci+a’ghd+di+a’ghe+ei+a’ghf+fi
Z199
wxn+wxo+wxp+wxq+w’my+ny+oy+py+qy+w’mz+nz+oz+pz+qz
Z208
pqrsm+pqrsn+pqrso+pqrsp+p’xyzt+mt+nt+ot+pt+p’xyzu+mu+nu+ou+pu+
Z2110
defgl+defgk+d’onmh+lh+kh+d’onmi+li+ki
Z2210
ijp+ijq+ijr+ijs+i’ok+pk+qk+rk+sk+i’ol+pl+ql+rl+sl+i’om+pm+qm+rm+sm+
Z2311
cdefgn+cdefgo+c’jklmh+nh+oh+c’jklmi+ni+oi
Z2412
a’be’f+a’bg+a’bh+ce’f+cg+ch+de’f+dg+dh
p’xyzv+ mv+nv+ov+pv+p’xyzw+mw+nw+ow+pw
i’on+pn+qn+rn+sn
Z2516
i’jkn’op+i’jkq+i’jkr+n’opl+ql+rl+n’opm+ qm+rm
Z2612
p’qrv’wx+p’qry+p’qrz+v’wxs+sy+sz+v’wxt+ty+tz+uv’wx+uy+uz
Z2710
a’bcdg’hij+a’bcdk+a’bcdl+g’hije+ke+le+g’hijf+kf+lf
Z288
r’sx’y+r’sz+r’sm+r’sn+r’so+x’yt+zt+mt+nt+ot+x’yu+zu+mu+nu+ou+x’yv+
Z2911
c’defgjklmn+c’defgo+c’defgp+j’klmnh+ho+hp+j’klmni+io+ip
Z3010
p’qrsx’yzm+p’qrsn+p’qrso+p’qrsk+p’qrsl+x’yzmt+nt+ot+kt+lt+x’yzmu+nu+
Z3110
a’bcf’gh+a’bci+a’bcj+f’ghd+id+jd+f’ghe+ie+je
Z3215
g’hk’l+g’hm+g’hn+k’li+mi+ni+k’lj+mj+nj
Z3311
o’pqu’vw+o’pqx+o’pqy+u’vwr+rx+ry+u’vws+xs+ys+u’wvt+xt+yt
Z3411
e’fj’k+e’fl+e’fm+e’fn+j’kg+lg+mg+ng+j’kh+lh+mh+nh+j’ki+li+mi+ni
Z3514
q’rsv’wx+q’rsy+q’rsz+v’wxt+yt+zt+v’wxu+uy+uz
ZXn; X – Function ID, n – Number of primary inputs
zv+mv+nv+ov+x’yw+zw+mw+nw+ow
ou+ku+lu+x’yzmv+nv+ov+kv+lv+x’yzmw+nw+ow+kw+lw
520