The document introduces Cockatrice, a hardware design environment that uses Elixir as its description language. Cockatrice aims to synthesize hardware description language (HDL) from Elixir code written in a "Zen style" with Enum and Flow functions. This allows hardware to be designed and operated from Elixir code. Cockatrice provides templates to synthesize HDL modules from Elixir functions and connects them as a dataflow circuit from the abstract syntax tree. It also generates an interface driver in C to enable communication between the synthesized hardware and controlling Elixir software.
Detecting attended visual targets in video の勉強会用資料Yasunori Ozaki
第三回 全日本コンピュータビジョン勉強会(後編)で発表した Detecting attended visual targets in video のまとめ資料です。映像中にいる人物が注意を払っている対象を推定するタスクを解いた話です。コンピュータビジョンや認知科学などに興味がある方はぜひご覧ください。
Detecting attended visual targets in video の勉強会用資料Yasunori Ozaki
第三回 全日本コンピュータビジョン勉強会(後編)で発表した Detecting attended visual targets in video のまとめ資料です。映像中にいる人物が注意を払っている対象を推定するタスクを解いた話です。コンピュータビジョンや認知科学などに興味がある方はぜひご覧ください。
PyCon JP 2021 (2021/10/16) @Hirosaji @Hirosaji_draw
https://2021.pycon.jp/time-table/?id=273843
※表示画面が小さいと感じる場合は、次のSpeakerDeckをご覧ください。
https://speakerdeck.com/hirosaji/the-art-of-reading-illustrations
=====
Title (English): The Art of Reading Pictures: Illustration Analysis in Python
PyCon JP 2021 (2021/10/16) @Hirosaji @Hirosaji_draw
https://2021.pycon.jp/time-table/?id=273843
※表示画面が小さいと感じる場合は、次のSpeakerDeckをご覧ください。
https://speakerdeck.com/hirosaji/the-art-of-reading-illustrations
=====
Title (English): The Art of Reading Pictures: Illustration Analysis in Python
.NET Core, ASP.NET Core Course, Session 3aminmesbahi
Session 3,
Introducing to Compiler
What is the LLVM?
LLILC
RyuJIT
AOT Compilation
Preprocessors and Conditional Compilation
An Overview on Dependency Injection
Field Programmable Gate Arrays (FPGAs) are configurable integrated circuits able to provide a good trade-off in terms of performance, power consumption, and flexibility with respect to other architectures, like CPUs, GPUs and ASICs. The main drawback in using FPGAs, however, is their steep learning curve. An emerging solution to this problem is to write algorithms in a Domain Specific Language (DSL) and to let the DSL compiler generate efficient code targeting FPGAs. This work proposes FROST, a unified backend that enables different DSL compilers to target FPGA architectures. Differently from other code generation frameworks targeting FPGA, FROST exploits a scheduling co-language that enables users to have full control over which optimizations to apply in order to generate efficient code (e.g. loop pipelining, array partitioning, vectorization). At first, FROST analyzes and manipulates the input Abstract Syntax Tree (AST) in order to apply FPGA-oriented transformations and optimizations, then generates a C/C++ implementation suitable for High-Level Synthesis (HLS) tools. Finally, the output of HLS phase is synthesized and implemented on the target FPGA using Xilinx SDAccel toolchain.
FROST currently supports as front-end Halide, an Image Processing DSL, and Tiramisu, a DSL optimizer, and allows to achieve significant speedups with respect to state-of-the-art FPGA implementations of the same algorithms.
(Costless) Software Abstractions for Parallel ArchitecturesJoel Falcou
Performing large, intensive or non-trivial computing on array like data structures is one of the most common task in scientific computing, video game development and other fields. This matter of fact is backed up by the large number of tools, languages and libraries to perform such tasks. If we restrict ourselves to C++ based solutions, more than a dozen such libraries exists from BLAS/LAPACK C++ binding to template meta-programming based Blitz++ or Eigen. If all of these libraries provide good performance or good abstraction, none of them seems to fit the need of so many different user types.
Moreover, as parallel system complexity grows, the need to maintain all those components quickly become unwieldy. This talk explores various software design techniques - like Generative Programming, MetaProgramming and Generic Programming - and their application to the implementation of a parallel computing librariy in such a way that:
- abstraction and expressiveness are maximized - cost over efficiency is minimized
We'll skim over various applications and see how they can benefit from such tools. We will conclude by discussing what lessons were learnt from this kind of implementation and how those lessons can translate into new directions for the language itself.
Rclex: A Library for Robotics meet ElixirHideki Takase
Presentation at Code BEAM America 2021
https://codesync.global/conferences/code-beam-sf-2021
https://codesync.global/speaker/hideki-takase/
How do we install the magic of Elixir into robot systems? One of the solutions is "Rclex", that is a client library for ROS 2 platform. ROS (Robot Operating System) provides publish/subscribe based messaging mechanism between robot modules with the DDS (Data Distribution Service) stack. We suggest that the force of Erlang/Elixir can power up the scalability of ROS 2 communication. This talk will introduce how did we integrate ROS 2 and Elixir by using NIFs, and discuss the possibility of this library in the IoT field.
ROS Japan UG #34 LT大会 で飛び込みLTした資料です.
https://rosjp.connpass.com/event/161041/
ROS 2のDashing/Eloquentで QoS (Quality of Service) 周りのAPIがそれぞれ破壊的に更新されててツラかったので,そのTIPS・知見を共有させていただきました.
Top Features to Include in Your Winzo Clone App for Business Growth (4).pptxrickgrimesss22
Discover the essential features to incorporate in your Winzo clone app to boost business growth, enhance user engagement, and drive revenue. Learn how to create a compelling gaming experience that stands out in the competitive market.
Large Language Models and the End of ProgrammingMatt Welsh
Talk by Matt Welsh at Craft Conference 2024 on the impact that Large Language Models will have on the future of software development. In this talk, I discuss the ways in which LLMs will impact the software industry, from replacing human software developers with AI, to replacing conventional software with models that perform reasoning, computation, and problem-solving.
Providing Globus Services to Users of JASMIN for Environmental Data AnalysisGlobus
JASMIN is the UK’s high-performance data analysis platform for environmental science, operated by STFC on behalf of the UK Natural Environment Research Council (NERC). In addition to its role in hosting the CEDA Archive (NERC’s long-term repository for climate, atmospheric science & Earth observation data in the UK), JASMIN provides a collaborative platform to a community of around 2,000 scientists in the UK and beyond, providing nearly 400 environmental science projects with working space, compute resources and tools to facilitate their work. High-performance data transfer into and out of JASMIN has always been a key feature, with many scientists bringing model outputs from supercomputers elsewhere in the UK, to analyse against observational or other model data in the CEDA Archive. A growing number of JASMIN users are now realising the benefits of using the Globus service to provide reliable and efficient data movement and other tasks in this and other contexts. Further use cases involve long-distance (intercontinental) transfers to and from JASMIN, and collecting results from a mobile atmospheric radar system, pushing data to JASMIN via a lightweight Globus deployment. We provide details of how Globus fits into our current infrastructure, our experience of the recent migration to GCSv5.4, and of our interest in developing use of the wider ecosystem of Globus services for the benefit of our user community.
SOCRadar Research Team: Latest Activities of IntelBrokerSOCRadar
The European Union Agency for Law Enforcement Cooperation (Europol) has suffered an alleged data breach after a notorious threat actor claimed to have exfiltrated data from its systems. Infamous data leaker IntelBroker posted on the even more infamous BreachForums hacking forum, saying that Europol suffered a data breach this month.
The alleged breach affected Europol agencies CCSE, EC3, Europol Platform for Experts, Law Enforcement Forum, and SIRIUS. Infiltration of these entities can disrupt ongoing investigations and compromise sensitive intelligence shared among international law enforcement agencies.
However, this is neither the first nor the last activity of IntekBroker. We have compiled for you what happened in the last few days. To track such hacker activities on dark web sources like hacker forums, private Telegram channels, and other hidden platforms where cyber threats often originate, you can check SOCRadar’s Dark Web News.
Stay Informed on Threat Actors’ Activity on the Dark Web with SOCRadar!
TROUBLESHOOTING 9 TYPES OF OUTOFMEMORYERRORTier1 app
Even though at surface level ‘java.lang.OutOfMemoryError’ appears as one single error; underlyingly there are 9 types of OutOfMemoryError. Each type of OutOfMemoryError has different causes, diagnosis approaches and solutions. This session equips you with the knowledge, tools, and techniques needed to troubleshoot and conquer OutOfMemoryError in all its forms, ensuring smoother, more efficient Java applications.
Enhancing Project Management Efficiency_ Leveraging AI Tools like ChatGPT.pdfJay Das
With the advent of artificial intelligence or AI tools, project management processes are undergoing a transformative shift. By using tools like ChatGPT, and Bard organizations can empower their leaders and managers to plan, execute, and monitor projects more effectively.
Enterprise Resource Planning System includes various modules that reduce any business's workload. Additionally, it organizes the workflows, which drives towards enhancing productivity. Here are a detailed explanation of the ERP modules. Going through the points will help you understand how the software is changing the work dynamics.
To know more details here: https://blogs.nyggs.com/nyggs/enterprise-resource-planning-erp-system-modules/
Innovating Inference - Remote Triggering of Large Language Models on HPC Clus...Globus
Large Language Models (LLMs) are currently the center of attention in the tech world, particularly for their potential to advance research. In this presentation, we'll explore a straightforward and effective method for quickly initiating inference runs on supercomputers using the vLLM tool with Globus Compute, specifically on the Polaris system at ALCF. We'll begin by briefly discussing the popularity and applications of LLMs in various fields. Following this, we will introduce the vLLM tool, and explain how it integrates with Globus Compute to efficiently manage LLM operations on Polaris. Attendees will learn the practical aspects of setting up and remotely triggering LLMs from local machines, focusing on ease of use and efficiency. This talk is ideal for researchers and practitioners looking to leverage the power of LLMs in their work, offering a clear guide to harnessing supercomputing resources for quick and effective LLM inference.
Code reviews are vital for ensuring good code quality. They serve as one of our last lines of defense against bugs and subpar code reaching production.
Yet, they often turn into annoying tasks riddled with frustration, hostility, unclear feedback and lack of standards. How can we improve this crucial process?
In this session we will cover:
- The Art of Effective Code Reviews
- Streamlining the Review Process
- Elevating Reviews with Automated Tools
By the end of this presentation, you'll have the knowledge on how to organize and improve your code review proces
First Steps with Globus Compute Multi-User EndpointsGlobus
In this presentation we will share our experiences around getting started with the Globus Compute multi-user endpoint. Working with the Pharmacology group at the University of Auckland, we have previously written an application using Globus Compute that can offload computationally expensive steps in the researcher's workflows, which they wish to manage from their familiar Windows environments, onto the NeSI (New Zealand eScience Infrastructure) cluster. Some of the challenges we have encountered were that each researcher had to set up and manage their own single-user globus compute endpoint and that the workloads had varying resource requirements (CPUs, memory and wall time) between different runs. We hope that the multi-user endpoint will help to address these challenges and share an update on our progress here.
We describe the deployment and use of Globus Compute for remote computation. This content is aimed at researchers who wish to compute on remote resources using a unified programming interface, as well as system administrators who will deploy and operate Globus Compute services on their research computing infrastructure.
May Marketo Masterclass, London MUG May 22 2024.pdfAdele Miller
Can't make Adobe Summit in Vegas? No sweat because the EMEA Marketo Engage Champions are coming to London to share their Summit sessions, insights and more!
This is a MUG with a twist you don't want to miss.
Software Engineering, Software Consulting, Tech Lead.
Spring Boot, Spring Cloud, Spring Core, Spring JDBC, Spring Security,
Spring Transaction, Spring MVC,
Log4j, REST/SOAP WEB-SERVICES.
How to Position Your Globus Data Portal for Success Ten Good PracticesGlobus
Science gateways allow science and engineering communities to access shared data, software, computing services, and instruments. Science gateways have gained a lot of traction in the last twenty years, as evidenced by projects such as the Science Gateways Community Institute (SGCI) and the Center of Excellence on Science Gateways (SGX3) in the US, The Australian Research Data Commons (ARDC) and its platforms in Australia, and the projects around Virtual Research Environments in Europe. A few mature frameworks have evolved with their different strengths and foci and have been taken up by a larger community such as the Globus Data Portal, Hubzero, Tapis, and Galaxy. However, even when gateways are built on successful frameworks, they continue to face the challenges of ongoing maintenance costs and how to meet the ever-expanding needs of the community they serve with enhanced features. It is not uncommon that gateways with compelling use cases are nonetheless unable to get past the prototype phase and become a full production service, or if they do, they don't survive more than a couple of years. While there is no guaranteed pathway to success, it seems likely that for any gateway there is a need for a strong community and/or solid funding streams to create and sustain its success. With over twenty years of examples to draw from, this presentation goes into detail for ten factors common to successful and enduring gateways that effectively serve as best practices for any new or developing gateway.
In 2015, I used to write extensions for Joomla, WordPress, phpBB3, etc and I ...Juraj Vysvader
In 2015, I used to write extensions for Joomla, WordPress, phpBB3, etc and I didn't get rich from it but it did have 63K downloads (powered possible tens of thousands of websites).
16. What is FPGA?
• Field Programmable Gate Array
− LSIs whose contents can
be changed any time
− We can design a unique
digital circuit (HW) on it
− Two major vendors
Xilinx・Altera (powered by Intel)
16
IOB
SB
CB LB
IOB
IOB
SB
IOB LB
SB
CB CB
SB
CB
SB SB
CB CBLB IOBIOB LB
SB SB SB
IOB IOB
CB
CB
CB
CB
CB
CB
I/O block
connection blockLB logic block
IOBSB switching block
CB
LUT
IN OUT
0000 1
0001 0
0010 0
… …
1110 1
1111 0
D-FF
D Q
17. How to Use of FPGA
17
processor
通信バス
FPGA
Offloading
heavy processing
HW
HW
interface IF
circuit
performance improvement
and low power consumption
can be achieved
SW
SW
communication
between SW/HW
SW
SW
IF
driver
18. Advantages of FPGA
18
FPGA
Memory
Func Func
Func FuncFunc
Func FuncFunc
FuncFunc
• Various systems can be designed onto one LSI
• High performance / low power consumption
• Parallel processing can be realized at task/data level
• Data streaming processing can be realized
19. Current Technology Trends
• Increase in circuit scale and amount of LB
− High performance systems can be realized
− Further increase will continue by new technology
multi-die, 3D stacking,,,
• Tightly coupling with processors
− General-purpose: Connection via PCIe to processors
− Embedded: Integration with embedded processors
19
high-quality system design
in a short time
has become difficult,,,
20. High Level Synthesis (HLS)
• Solution to improve design productivity!
− Technology for synthesizing HDL from behavioral
descriptions with a programming language
C/C++ or its extension is commonly used
− Abstraction level of design becomes higher
20
int func (int x) {
int a[N];
int i;
for(i=0;i<N;i++){
a[i] = ・・・;
:
:
}
:
}
x
func
i
a
21. Commercial HLS Tools
• Xilinx Vivado HLS
− Synthesize from C/C++
− #pragma is offered to
indicate the optimization
21
• Intel SDK for OpenCL
− Synthesize from
OpenCL parallelized code
− Can be executed with same
description as the host PC
Ref: Xilinx Inc. White paper UG902
D. Neto, Optimizing OpenCL for Altera FPGAs, Int’l Workshop on Open CL, 2014.
It is essential to understand
#pragma and libraries deeply
for deriving optimized hardware
22. not only C/C++!!
• Chisel: Scala based
− Object Oriented / Functional styled DSL
• CλaSH: Haskell based
− Synthesize HDL from description of functional language
• Karuta: original scripting language
• Synthesijer: Java based
− HLS from the subset of Java specification
• PyCoRAM, Polyphony: Python based
Veriloggen: Python library for HDL design
• Mulvery: Ruby based
− Synthesis from Reactive Programming
• Octopus🐙:OCaml based
22
developed by
hls-friends!!
24. OK, What We Want is,,,
24
We want to design
HW by Elixir!!
We want to operate HW
from our Elixir code!!
25. Concept of Cockatrice
• Why Elixir would be suitable for HW design?
• HW synthesis flow from Elixir code
• SW/HW communication interface
26. What is Cockatrice?
• Summoned beast that appears in FF4 (^^;
− The effect is to make all enemies to stones
• Hardware design environment with Elixir!
• Features
− It synthesizes Elixir Zen Styled code
to the description of HW circuits
− It provides communication interface
between Elixir code and HW circuits
26
Your Elixir code can be accelerated,
and low-powered!!
NOTE: Current logo of cockatrice is from Wikipedia
27. Zen’s process model
27
input_list
|> Flow.from_enumerable(stages: 4)
|> Flow.map(& foo(&1))
|> Flow.map(fn a->-a end)
|> Enum.to_list
|> Enum.sort
from_
enumerable
input_list
foo
foo
foo
foo
sortto_list
arbitrator
-a
-a
-a
-a
It’s similar to
efficient HW
architecture!!
28. Zen is suitable for HW design!
28
Cockatrice
input_list
|> Flow.from_enumerable(stages: 4)
|> Flow.map(& foo(&1))
|> Flow.map(fn a->-a end)
|> Enum.to_list
|> Enum.sort
from_
enumerable
input_list
foo
foo
foo
foo
sortto_list
arbitrator
-a
-a
-a
-a
We summon Cockatrice to lithify
Elixir Zen Styled Code
as parallel HW stones!!
29. Effect of Cockatrice
29
Input
List from_
enume
rable
to_list
sort
foo -a
foo -a
foo -a
foo -a
arbitrator
foo -a
foo
-a
foo -a
foo
-a
foo
-a
foo
foo -a
foo
-a
foo -a -a
foo -a
foo -afoo -a
foo -a
30. HW Description by Elixir
• defcockatrice part will be
treat as HW description
− It is completely equivalent
to native Elixir code
You do not need to
consider HW design
It can be verified at
functional level
• HW module can be called
as same as SW function
− We assume SW/HW
cooperative systems
30
31. Synthesis Flow
31
Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
32. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
32
Metaprogramming method is employed
to derive AST of Zen styled design
description by Quote function
33. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
33
we provide templates of HDL
code that are equivalent to
Enum functions as DSL files
HDL code is synthesized by
applying pattern matching
with AST and DSL
34. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
34
each modules is connected as data flow
from AST representation of |> and Flow
data flow and parallel processing
HW circuit is finally synthesized!!
35. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
35
communication interface
and its driver are
generated as NIF function
36. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
SW binary and HW bit files are
compiled by respective tools
Synthesis Flow
36
SW binary and HW bit files are
compiled by respective tools
37. SW/HW Comm. Interface
• Activation/Operation to
HW from Elixir code
• Data communication
between SW and HW
− AXI4 bus on Zynq is used
• We implement device
driver as C/NIF module
− ikwzm/udmabuf is used
for DMA transfer
− Elixir/Erlang list should be
converted to C array
37
FPGA
processor
DMA buffer
HW circuits
Elixir app
Erlang VM
device driver
(NIF module)
interface
circuit
44. Discussion
• Currently, we just implement prototypes
− We will publish them as Hex pkgs very soon,,,
− Currently supported features are limited
IOW, we only synthesize Zen styled code
Are another Elixir/Erlang process models
suitable for efficient HW architecture?
− Quantitative evaluation of our proposal will be also
important (to verify academic contribution^^;
44
45. Discussion
• Applicable range of Cockatrice?
− Not only embedded, but also HPC domain!?
Bigger data for Cockatrice would be suitable
since there is some overhead on SW/HW comm.
− AI/ML would be a killer application
Big data stream processing for IoT
Cloud processing that allows users
to change functions flexibly
− We are planning to support large-scale FPGA
boards with comm. interface for PCIe bus
45
46. BTW, I love Nerves!!
• Experiences at Lonestar2019 was great for me!
• I made a presentation to promote the innovation of
Nerves to Japan at Erlang & Elixir Fest 2019!!
46
Nervesが開拓する
『ElixirでIoT』
の新世界
⾼瀬 英希
(京都⼤学/JSTさきがけ)
takase@i.kyoto-u.ac.jp
18
ライブデモのお品書き
1. Nervesプロジェクトの準備とビルド
2. microSDに書き込んでブート・IEx実⾏
3. ソース編集してlocal ssh書き込み
4. NervesHubから書き込み
5. Scenic連携&GPIOデバイスの制御
Raspberry Pi Zero WH Adafruit 128x64 OLED Bonnet
https://github.com/takasehideki/eefest19demo
NervesKey
『ElixirでIoT』の新世界︕
25
デバイス
エッジサーバ クラウド
あらゆるモノ・コト・ヒトを
ネットワーク化︕
情報科学の総合格闘技︕
新たな社会的価値を創出!!
みんなで⼀緒に
IoTを創ろう︕
14
NervesHub
•サーバ経由のOTA (Over The Air) で
Nervesアプリをリモートデプロイ︕
- X.509署名証明書とNervesKey回路で
セキュアな接続経路を実現
- 更新先とファームを任意指定可
47. Future Direction
47
What will happen
when Nerves meets Cockatrice?
Please help us, to evolve the new era of
"IoT development with Elixir"
48. Future of “Elixir for IoT”
48
device
edge server cloud
これがワタシの
Extreme Computing!!
49. Thank to,,, with Wabi-Sabi
• My students in lab.
− Kentaro Matsui
− Yasuhiro Nitta
• My research partners at fukuoka.ex
− @zacky1972
− @hisawayex
− @piacere_ex
− @enpedasi
• My friends at hls-friends
− Tech comm. for self-made high-level synthesis tools
49
Editor's Notes
I’m Hideki Takase from Kyoto, Japan.
This is the second time for me to attend ElixirConf. First time was Lonestar in this year.
So, nice to see you or long time no see!
It’s my big pleasure to present our work on ElixirConf.
Thank you so much to accept my talk proposal.
粗粒度並列化よりパイプライン化とかのほうが効くかも それを指定できると良いかも
どこかで高位合成しないといけないのだから,HLS Cを吐くアプローチを取ったほうが手っ取り早いのでは?
Elixir/ErlangからCに変換するようなコンパイラの研究ありそう
データを流すから通信が重くなる 共有メモリへのアクセスとかで改善したほうが良さそう
最適化目標を指定できるようにしたほうが良いのか?
My presentation consists of 3 parts.
How many people do you know about FPGA?
First part is just a lecture in the University. I will introduce about hardware design and FPGA.
OK, let’s go to the 1st part.
by providing the training materials from Frank and Justin.
He agreed to hold it in Japan.
Thank you so much, Justin & Frank,
My presentation consists of 3 parts.
How many people do you know about FPGA?
First part is just a lecture in the University. I will introduce about hardware design and FPGA.
OK, let’s go to the 1st part.
There is pros and cons between SW and HW.
For HW, performance and power efficiency are much better compared with processor because HW can be operated as the demand. In addition, high-performance parallel processing can be realized easily if we can design HW carefully.
On the other hands, one of the advantages of processor is design flexibility. We can realize various application respective to your programming.
So, FPGA takes good advantage from both resources. This means that FPGA is better performance and power efficiency than processor with better design flexibility.
I introduce what is FPGA?
FPGA stands for field programmable gate array, that is LSI whose contents can be changed any time as you want. So, we can realize a unique digital circuits on FPGA.
There is 2 major vendors, Xilinx and Intel Altera.
As shown in this figure, internal architecture of FPGA is expressed as the systolic array of logic block, connection, switching, and I/O blocks. The logic block consists of lookup tables and data flip-flop.
So, we can change the HW Behavior by deciding the values of LUTs and their connections.
I will show general usage of FPGA.
FPGA is typically used with processor as the accelerator.
We can offload the part of heavy processing on processor to the FPGA. So, we expect the performance improvement and power savings by utilizing FPGA.
To communicate between processors and FPGA efficiently, we need the suitable communication interface.
Higher quality HW/SW cooperative system can be realized
逐次,分岐,繰り返しなどの制御はステートマシンとして,変数はレジスタ,配列はメモリとして生成される
sequential
オープンソース!
LegUpはトロント大,ChiselはUCB
18分でいきたい
The effect of cockatrice is to make all enemies to stones. So, I decide its codename that makes your Elixir code to HW.
flow genstage
Metaprogramming
udmabuf is a Linux device driver that allocates contiguous memory blocks in the kernel space as DMA buffers and makes them available from the user space. It is intended that these memory blocks are used as DMA buffers when a user application implements device driver in user space using UIO (User space I/O).
Zynq-7000 devices are equipped with dual-core ARM Cortex-A9 processors integrated with 28nm Artix-7 or Kintex®-7 based programmable logic for excellent performance-per-watt and maximum design flexibility. With up to 6.6M logic cells and offered with transceivers ranging from 6.25Gb/s to 12.5Gb/s, Zynq-7000 devices enable highly differentiated designs for a wide range of embedded applications including multi-camera drivers assistance systems and 4K2K Ultra-HDTV.
EG devices feature a quad-core ARM® Cortex-A53 platform running up to 1.5GHz. Combined with dual-core Cortex-R5 real-time processors, a Mali-400 MP2 graphics processing unit, and 16nm FinFET+ programmable logic, EG devices have the specialized processing elements needed to excel in next-generation wired and 5G wireless infrastructure, cloud computing, and Aerospace and Defense applications.
I’m Hideki Takase from Kyoto, Japan.
This is the second time for me to attend ElixirConf. First time was Lonestar in this year.
So, nice to see you or long time no see!
It’s my great pleasure to present our work. Thank you so much to accept my talk proposal.
粗粒度並列化よりパイプライン化とかのほうが効くかも それを指定できると良いかも
どこかで高位合成しないといけないのだから,HLS Cを吐くアプローチを取ったほうが手っ取り早いのでは?
Elixir/ErlangからCに変換するようなコンパイラの研究ありそう
データを流すから通信が重くなる 共有メモリへのアクセスとかで改善したほうが良さそう
最適化目標を指定できるようにしたほうが良いのか?
Task, GenServer, and so on
Bigger data would be suitable
The new era of "IoT development with Elixir" pioneered by Nerves technology
This is the last slide.
I believe if Nerves can control the FPGA directly.
19:30
First of all, let me introduce my research collaborator since Wabi-Sabi is important for Japanese.
I would like to say a big thank to Kentaro and Yasuhiro. They are my students in laboratory, and have made a great effort on this project.
I appreciate the members of fukuoka.ex, It is a Elixir community in Fukuoka, Japan. They always give a technical support for me. As you may know, Zacky and Hisaway will present their work for a novel technology about GPU with Elixir.
I also appreciate the members of hls-friends. It is a Japanese community for self-made high level synthesis tools by various programming languages. These members give useful comments and motivation to my project.