IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A Configurable and Low Power Hard-Decision Viterbi Decoder in VLSI ArchitectureIRJET Journal
This document describes a configurable and low power VLSI architecture for a hard-decision Viterbi decoder. It proposes a design that can be configured for different numbers of traceback steps (N) by adjusting traceback parameters without major modifications to the register transfer level design. The design aims to consume low power. It was synthesized in Xilinx and showed good results for operational speed and area consumption when tested for N=32 and N=64 traceback steps. Viterbi decoding is an important error correction technique that involves convolutional encoding, transmission with potential errors, and decoding using the Viterbi algorithm. Low power is a priority for Viterbi decoders due to their power consumption.
IRJET- Review Paper on Study of Various Interleavers and their SignificanceIRJET Journal
This document reviews various interleavers and their significance in digital communication systems. It discusses how interleavers can be used in turbo encoders and decoders to improve error correction capabilities without reducing bandwidth. The document summarizes different types of interleavers including random, QPP, helical, odd-even, and matrix interleavers. It also discusses turbo encoding and decoding processes and how convolutional codes differ from block codes. Key performance metrics like bit error rate and bit error rate curves are analyzed to evaluate and compare interleaver quality.
The importance of cryptography knuckle down to the security in electronic data transmissions has gained an essential relevance during past years. Cryptography security mechanisms uses some algorithms to muddle the data into unreadable text with a key which can only be decoded/decrypted by one who has that associated key for the locked data. Cryptography techniques are of two types: Symmetric & Asymmetric. In this paper we’ve used symmetric cryptography method-Advance Encryption Standard algorithm with 200 bit block size as well as 200 bit key size. We’ve used 5*5 matrix to implement same 128 bit conventional AES algorithm for 200 bit block size. After implementing the algorithm, the proposed work is compared with 128,192 & 256 bits AES techniques in context with Encryption and Decryption Time & Throughput at both Encryption and Decryption ends.
The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A Configurable and Low Power Hard-Decision Viterbi Decoder in VLSI ArchitectureIRJET Journal
This document describes a configurable and low power VLSI architecture for a hard-decision Viterbi decoder. It proposes a design that can be configured for different numbers of traceback steps (N) by adjusting traceback parameters without major modifications to the register transfer level design. The design aims to consume low power. It was synthesized in Xilinx and showed good results for operational speed and area consumption when tested for N=32 and N=64 traceback steps. Viterbi decoding is an important error correction technique that involves convolutional encoding, transmission with potential errors, and decoding using the Viterbi algorithm. Low power is a priority for Viterbi decoders due to their power consumption.
IRJET- Review Paper on Study of Various Interleavers and their SignificanceIRJET Journal
This document reviews various interleavers and their significance in digital communication systems. It discusses how interleavers can be used in turbo encoders and decoders to improve error correction capabilities without reducing bandwidth. The document summarizes different types of interleavers including random, QPP, helical, odd-even, and matrix interleavers. It also discusses turbo encoding and decoding processes and how convolutional codes differ from block codes. Key performance metrics like bit error rate and bit error rate curves are analyzed to evaluate and compare interleaver quality.
The importance of cryptography knuckle down to the security in electronic data transmissions has gained an essential relevance during past years. Cryptography security mechanisms uses some algorithms to muddle the data into unreadable text with a key which can only be decoded/decrypted by one who has that associated key for the locked data. Cryptography techniques are of two types: Symmetric & Asymmetric. In this paper we’ve used symmetric cryptography method-Advance Encryption Standard algorithm with 200 bit block size as well as 200 bit key size. We’ve used 5*5 matrix to implement same 128 bit conventional AES algorithm for 200 bit block size. After implementing the algorithm, the proposed work is compared with 128,192 & 256 bits AES techniques in context with Encryption and Decryption Time & Throughput at both Encryption and Decryption ends.
The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document describes a technique for constructing Walsh code sets of any length recursively using 4-bit Gray codes and Inverse Gray codes. It begins with algorithms to generate n-bit binary cyclic Gray codes and Inverse Gray codes. Walsh codes are then constructed from these Gray/Inverse Gray codes. Specifically, all possible 4-bit Gray and Inverse Gray codes are generated, yielding 24 codes total. These codes are then used to recursively build Walsh code sets of any length. Finally, the document discusses mapping techniques to rearrange the Walsh code sets into different orderings like Walsh-Hadamard and Walsh-Paley matrices.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
A Block Cipher Based Cryptosystem through Modified Forward Backward Overlappe...IOSR Journals
This document proposes a new block cipher cryptosystem called Modified Forward Backward Overlapped Modulo Arithmetic Technique (MFBOMAT). MFBOMAT divides a message into blocks of varying sizes from 2 to 256 bits. It then performs modular addition on overlapping pairs of blocks in a cascading manner from the most to least significant bits. For decryption, modular subtraction is used. The algorithm is implemented on sample 32-bit messages to demonstrate the encryption and decryption process. Analysis shows the encrypted text is well distributed over the character space providing security. MFBOMAT encryption time is comparable to other techniques like RSA and FBOMAT based on tests on sample files.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
This document summarizes research on improving the performance of multiplier and accumulator (MAC) circuits used in digital signal processing. It presents four architectures for carry-select adders (CSLA) that can be used in MACs: 1) a regular CSLA, 2) a CSLA that replaces full adders with binary-to-excess converters (BEC) to reduce area, 3) a CSLA that uses D-latches to store intermediate values and reduce the number of adders, and 4) a modified CSLA architecture. The document analyzes the delay and area of each group of bits for the different CSLA architectures. It finds that BEC and D-latch based C
Design and Implementation of High Speed Area Efficient Double Precision Float...IOSR Journals
The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
This document summarizes a research paper that proposes a new binary tree algorithm for implementing a Huffman decoder. It begins by explaining the disadvantages of using an array data structure to represent the Huffman decoding tree and how the proposed binary tree method requires less memory. The proposed decoder is then implemented using ASIC and FPGA design tools. Performance metrics like power, area, and number of registers are obtained and compared between the ASIC and FPGA implementations. Simulation results show that the ASIC implementation has lower power consumption than the FPGA version. In conclusion, the binary tree algorithm is shown to improve memory usage for Huffman decoding.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
This document discusses the implementation of AES encryption and decryption using a multiplexer look-up table (MLUT) based substitution box (S-box) on an FPGA to reduce power consumption and increase resistance to side channel attacks. The proposed MLUT S-box uses a 256-byte to 1-byte multiplexer with a 256-byte memory to select pre-computed S-box outputs, making it simpler and lower power than conventional implementations. Simulation results show the MLUT S-box design encrypting and decrypting data correctly while consuming 0.55W of power, three times lower than a conventional S-box. Power analysis also found the MLUT S-box has highly uniform power dissipation for different inputs
This document presents a comparison of a modified 64-bit binary comparator design and an existing 64-bit binary comparator design. The modified design implements the first stage using CMOS logic instead of pass transistor logic to improve speed. Simulation results show the modified design has a 0.47% reduction in delay for the A_LT_B output and a 1.23% reduction in delay for the A_EQU_B output compared to the existing design, while using more power and transistors. Therefore, the modified design provides better performance for high-speed applications.
This document describes the design of different types of parallel multipliers using low power techniques on a 0.18um technology node. It discusses Braun multipliers, row-bypassing multipliers, and column-bypassing multipliers. The multipliers are implemented using both conventional methods and the Gate-Diffusion-Input (GDI) technique. Simulation results show that implementing the multipliers using GDI reduces transistor counts and power consumption compared to conventional implementations. The 4x4 Braun multiplier implemented with GDI uses 136 transistors and consumes 3mW of power, providing significant improvements over the conventional implementation.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Modified Golomb Code For Integer RepresentationIJSRD
In this computer age, all the computer applications handle data in the form of text, numbers, symbols and combination of all of them. The primary objective of data compression is to reduce the size of data while data needs to be stored and transmitted in the digital devices. Hence, the data compression plays a vital role in the areas of data storage and data transmission. Golomb code, which is a variable-length integer code, has been used for text compression, image compression, video compression and audio compression. The drawback of Golomb code is that it requires more bits to represent large integers if the divisor is small. Alternatively, Golomb code needs more bits to represent small integers if the divisor is large. This paper proposes Modified Golomb Code based on Golomb Code, Extended Golomb Code to represent small as well as large integers compactly for the chosen divisor. In this work, as an application of Modified Golomb Code, Modified Golomb Code is used with Burrows-Wheeler transform for text compression. The performances of Golomb Code and Modified Golomb Code are evaluated on Calcary corpus dataset. The experimental results show that the proposed code provides better compression rate than Golomb code on an average. The performance of the proposed code is also compared with Extended Golomb Codes (EGC). The comparison results show that the proposed code achieves significant improvement for the binary files of Calgary corpus comparing to EGC.
Enhancement of DES Algorithm with Multi State LogicIJORCS
The principal goal to design any encryption algorithm must be the security against unauthorized access or attacks. Data Encryption Standard algorithm is a symmetric key algorithm and it is used to secure the data. Enhanced DES algorithm works on increasing the key length or complex S-BOX design or increased the number of states in which the information is to be represented or combination of above criteria. By increasing the key length, the number of combinations for key will increase which is hard for the intruder to do the brute force attack. As the S-BOX design will become the complex there will be a good avalanche effect. As the number of states increases in which the information is represented, it is hard for the intruder to crack the actual information. Proposed algorithm replace the predefined XOR operation applied during the 16 round of the standard algorithm by a new operation called “Hash function” depends on using two keys. One key used in “F” function and another key consists of a combination of 16 states (0,1,2…13,14,15) instead of the ordinary 2 state key (0, 1). This replacement adds a new level of protection strength and more robustness against breaking methods.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Importance of post processing for improved binarization of text documentseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Nanoparticle based charge trapping memory device applying mos technology a co...eSAT Publishing House
This document discusses the development of a nanoparticle-based charge trapping memory device using a MOS structure. Specifically, it proposes replacing the continuous polysilicon floating gate of flash memory cells with a discrete layer of polyvinyl alcohol (PVA)-capped zinc oxide nanoparticles. This is expected to allow reducing the thickness of the tunneling oxide without affecting endurance, reliability or performance. The document summarizes the basic MOS structure and operation of charge trapping memory devices. It then discusses how using nanoparticles as discrete charge trapping sites could improve retention time, scalability, programming speed, endurance and reliability compared to conventional floating gate devices.
The document compares the security of grid computing and cloud computing. Grid computing is considered more mature and has tighter security than cloud computing. Some key differences are:
- Grid computing uses multiple IDs for authentication while cloud often uses a single ID and password.
- Grid security infrastructure (GSI) uses public key protocols for authentication, communication protection, and authorization. Cloud relies more on basic username and password.
- Grid computing enforces service level agreements (SLAs) and policies across sites using distributed enforcement points. Cloud SLA security is simpler.
- The document proposes a new two-factor authentication model for cloud computing that uses graphical passwords and pass point selection on images for added security.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document describes a technique for constructing Walsh code sets of any length recursively using 4-bit Gray codes and Inverse Gray codes. It begins with algorithms to generate n-bit binary cyclic Gray codes and Inverse Gray codes. Walsh codes are then constructed from these Gray/Inverse Gray codes. Specifically, all possible 4-bit Gray and Inverse Gray codes are generated, yielding 24 codes total. These codes are then used to recursively build Walsh code sets of any length. Finally, the document discusses mapping techniques to rearrange the Walsh code sets into different orderings like Walsh-Hadamard and Walsh-Paley matrices.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
A Block Cipher Based Cryptosystem through Modified Forward Backward Overlappe...IOSR Journals
This document proposes a new block cipher cryptosystem called Modified Forward Backward Overlapped Modulo Arithmetic Technique (MFBOMAT). MFBOMAT divides a message into blocks of varying sizes from 2 to 256 bits. It then performs modular addition on overlapping pairs of blocks in a cascading manner from the most to least significant bits. For decryption, modular subtraction is used. The algorithm is implemented on sample 32-bit messages to demonstrate the encryption and decryption process. Analysis shows the encrypted text is well distributed over the character space providing security. MFBOMAT encryption time is comparable to other techniques like RSA and FBOMAT based on tests on sample files.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
This document summarizes research on improving the performance of multiplier and accumulator (MAC) circuits used in digital signal processing. It presents four architectures for carry-select adders (CSLA) that can be used in MACs: 1) a regular CSLA, 2) a CSLA that replaces full adders with binary-to-excess converters (BEC) to reduce area, 3) a CSLA that uses D-latches to store intermediate values and reduce the number of adders, and 4) a modified CSLA architecture. The document analyzes the delay and area of each group of bits for the different CSLA architectures. It finds that BEC and D-latch based C
Design and Implementation of High Speed Area Efficient Double Precision Float...IOSR Journals
The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
This document summarizes a research paper that proposes a new binary tree algorithm for implementing a Huffman decoder. It begins by explaining the disadvantages of using an array data structure to represent the Huffman decoding tree and how the proposed binary tree method requires less memory. The proposed decoder is then implemented using ASIC and FPGA design tools. Performance metrics like power, area, and number of registers are obtained and compared between the ASIC and FPGA implementations. Simulation results show that the ASIC implementation has lower power consumption than the FPGA version. In conclusion, the binary tree algorithm is shown to improve memory usage for Huffman decoding.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
This document discusses the implementation of AES encryption and decryption using a multiplexer look-up table (MLUT) based substitution box (S-box) on an FPGA to reduce power consumption and increase resistance to side channel attacks. The proposed MLUT S-box uses a 256-byte to 1-byte multiplexer with a 256-byte memory to select pre-computed S-box outputs, making it simpler and lower power than conventional implementations. Simulation results show the MLUT S-box design encrypting and decrypting data correctly while consuming 0.55W of power, three times lower than a conventional S-box. Power analysis also found the MLUT S-box has highly uniform power dissipation for different inputs
This document presents a comparison of a modified 64-bit binary comparator design and an existing 64-bit binary comparator design. The modified design implements the first stage using CMOS logic instead of pass transistor logic to improve speed. Simulation results show the modified design has a 0.47% reduction in delay for the A_LT_B output and a 1.23% reduction in delay for the A_EQU_B output compared to the existing design, while using more power and transistors. Therefore, the modified design provides better performance for high-speed applications.
This document describes the design of different types of parallel multipliers using low power techniques on a 0.18um technology node. It discusses Braun multipliers, row-bypassing multipliers, and column-bypassing multipliers. The multipliers are implemented using both conventional methods and the Gate-Diffusion-Input (GDI) technique. Simulation results show that implementing the multipliers using GDI reduces transistor counts and power consumption compared to conventional implementations. The 4x4 Braun multiplier implemented with GDI uses 136 transistors and consumes 3mW of power, providing significant improvements over the conventional implementation.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Modified Golomb Code For Integer RepresentationIJSRD
In this computer age, all the computer applications handle data in the form of text, numbers, symbols and combination of all of them. The primary objective of data compression is to reduce the size of data while data needs to be stored and transmitted in the digital devices. Hence, the data compression plays a vital role in the areas of data storage and data transmission. Golomb code, which is a variable-length integer code, has been used for text compression, image compression, video compression and audio compression. The drawback of Golomb code is that it requires more bits to represent large integers if the divisor is small. Alternatively, Golomb code needs more bits to represent small integers if the divisor is large. This paper proposes Modified Golomb Code based on Golomb Code, Extended Golomb Code to represent small as well as large integers compactly for the chosen divisor. In this work, as an application of Modified Golomb Code, Modified Golomb Code is used with Burrows-Wheeler transform for text compression. The performances of Golomb Code and Modified Golomb Code are evaluated on Calcary corpus dataset. The experimental results show that the proposed code provides better compression rate than Golomb code on an average. The performance of the proposed code is also compared with Extended Golomb Codes (EGC). The comparison results show that the proposed code achieves significant improvement for the binary files of Calgary corpus comparing to EGC.
Enhancement of DES Algorithm with Multi State LogicIJORCS
The principal goal to design any encryption algorithm must be the security against unauthorized access or attacks. Data Encryption Standard algorithm is a symmetric key algorithm and it is used to secure the data. Enhanced DES algorithm works on increasing the key length or complex S-BOX design or increased the number of states in which the information is to be represented or combination of above criteria. By increasing the key length, the number of combinations for key will increase which is hard for the intruder to do the brute force attack. As the S-BOX design will become the complex there will be a good avalanche effect. As the number of states increases in which the information is represented, it is hard for the intruder to crack the actual information. Proposed algorithm replace the predefined XOR operation applied during the 16 round of the standard algorithm by a new operation called “Hash function” depends on using two keys. One key used in “F” function and another key consists of a combination of 16 states (0,1,2…13,14,15) instead of the ordinary 2 state key (0, 1). This replacement adds a new level of protection strength and more robustness against breaking methods.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Importance of post processing for improved binarization of text documentseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Nanoparticle based charge trapping memory device applying mos technology a co...eSAT Publishing House
This document discusses the development of a nanoparticle-based charge trapping memory device using a MOS structure. Specifically, it proposes replacing the continuous polysilicon floating gate of flash memory cells with a discrete layer of polyvinyl alcohol (PVA)-capped zinc oxide nanoparticles. This is expected to allow reducing the thickness of the tunneling oxide without affecting endurance, reliability or performance. The document summarizes the basic MOS structure and operation of charge trapping memory devices. It then discusses how using nanoparticles as discrete charge trapping sites could improve retention time, scalability, programming speed, endurance and reliability compared to conventional floating gate devices.
The document compares the security of grid computing and cloud computing. Grid computing is considered more mature and has tighter security than cloud computing. Some key differences are:
- Grid computing uses multiple IDs for authentication while cloud often uses a single ID and password.
- Grid security infrastructure (GSI) uses public key protocols for authentication, communication protection, and authorization. Cloud relies more on basic username and password.
- Grid computing enforces service level agreements (SLAs) and policies across sites using distributed enforcement points. Cloud SLA security is simpler.
- The document proposes a new two-factor authentication model for cloud computing that uses graphical passwords and pass point selection on images for added security.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An extended database reverse engineering – a key for database forensic invest...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Building extraction from remote sensing imageries by data fusion techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The document analyzes problems with the shaft of a biomass grinder integrated with a briquetting plant. Finite element analysis was conducted using ANSYS software to model and simulate stresses on the stepped shaft under different loads and rotational speeds. The analysis found that maximum shear stress occurred at the point where the blower was fitted to the shaft. Increasing pressure led to higher von Mises and shear stresses. However, operating the shaft at higher rotational speeds reduced von Mises stresses, lowering the risk of failure. The study provides insights to reduce shaft stresses and improve reliability of the biomass grinder.
Sdci scalable distributed cache indexing for cache consistency for mobile env...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document compares symmetrical and asymmetrical cascaded current source multilevel inverters. It discusses their structures, operational characteristics, advantages, and simulation results. Symmetrical multilevel inverters have equal current sources, while asymmetrical have unequal sources in a geometric progression. For the same number of components, asymmetrical inverters can produce more output levels and higher voltages with lower total harmonic distortion. Simulation results show the output waveform and THD for different configurations, confirming asymmetrical inverters have better performance.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of all digital phase locked loop (d pll) with fast acquisition timeeSAT Journals
Abstract
A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate
from 6.54MHz to 105MHz with a power dissipation of is 7.763μW (at 210MHz) with 1.2V supply voltage. The D-PLL is
synthesized using cadence RTL compiler in 45nm CMOS process technology.
Keywords: Digital PLL, Digital Phase/Frequency detector, NCO, Divide by N counter.
Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This document summarizes a research paper that presents a codec scheme to optimize power in VLSI interconnects using bus encoding. The scheme detects different types of crosstalk couplings between wires and encodes the data to reduce switching activity. It was implemented using Cadence tools in 0.18um technology. Simulation results found a maximum power of 6.44uW for an input combination, showing a 38.89% power reduction over previous work. The scheme models the full custom design approach instead of semi-custom.
Design of High Speed and Low Power Veterbi Decoder for Trellis Coded Modulati...ijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Speed Low Power Veterbi Decoder Design for TCM Decodersijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
Viterbi Decoder Plain Sailing Design for TCM Decodersijtsrd
Convolutional codes are error correction technique used in noisy channels. Viterbi Algorithm is the most widely used decoding Algorithm, which decodes the sequence in a maximum likelihood sense. But the complexity of the Viterbi decoder increases with the coding rate of the system. Viterbi decoder is the most power hungry module in the Trellis coded modulation system. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths. The basic building blocks of Viterbi decoder are branch metric unit, add compare and select unit and survivor memory management unit. From the simulation results it is observed that the proposed Viterbi decoder architecture with modified Branch metric calculation can reduce significant amount of computations in order to decrease the hardware usage and to simplify the proceedings. Suman Chandel | Manju Mathur "Viterbi Decoder Plain Sailing Design for TCM Decoders" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26710.pdf Paper URL: https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/26710/viterbi-decoder-plain-sailing-design-for-tcm-decoders/suman-chandel
Investigative Compression Of Lossy Images By Enactment Of Lattice Vector Quan...IJERA Editor
In the digital era we live in, efficient representation of data generated by a discrete source and its reliable transmission are unquestionable need. In this work we have focused on source coding taking image as source. Lattice Vector Quantization (LVQ) can be used for source coding as well as for channel coding. (LVQ) with Generator Matrix (GM) and codebook is implemented. When implementation using codebook is done, two codebooks are constructed, one with 256 lattice points that are closest to (0,0,0,0) and another with 256 lattice points that are closest to (1,0,0,0). Energy for both the codes is calculated. When we compare the energy of both the codes we find that codes centered at a non lattice point is lower energy code.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A review on glitch reduction techniqueseSAT Journals
Abstract This paper presents different techniques for reducing glitch power in digital circuits. The aim of this study is to minimize glitch power as glitch power comes under dynamic power, so that power dissipation will reduce up to some extent in digital circuits. Warren Shum et.al [2011] work shows glitch power in FPGA’s varies from 4 % to 73 % of total dynamic power having an average of 22.6 %. Warren Shum et.al [2011] and J. Lamoureux et.al [2008] motivates us to reduce glitch power in digital circuits as well as FPGA’s. Different techniques are available for reducing glitch power like gate sizing, gate freezing, multiple threshold transistors, hazard filtering, balancing path delay, by reducing switching activity etc. Keywords: Glitch, Power dissipation, Gate sizing, Gate freezing, multiple threshold transistor, Hazard filtering, balancing path delay and switching activity.
Protocol converter (uart, i2 c, manchester protocols to usb)eSAT Journals
Abstract
Abstract now a day’s many industries are using different types of protocols to show data on computer. For this purpose different modules are used which increases the hardware complexity and cost. This project (PROTOCOL CONVERTER) is helpful to overcome these problem different types of protocols such as Manchester, UART and I2Cconverted to the USB format which is compatible to the laptops which is the major application .By using different components such as PIC microcontroller 18F452, LCD, Personal computer, Max 232, DB9 connector.
Keywords::USB (universal serial bus)1, UART(universal asynchronous receiver/transmitter2), I2C (Inter-Integrated Circuit3), Manchester4.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Fpga implementation of various lines coding technique for efficient transmiss...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr AlgorithmIJERA Editor
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There
are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to
the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different
versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance.
The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory
consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this
increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select
(ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3
FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT
log BCJR decoder.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document summarizes a paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a low complexity turbo decoder architecture using a modified Add Compare Select (ACS) unit and registers to implement the Constant log BCJR algorithm. The Constant log BCJR algorithm reduces complexity compared to other MAP decoding algorithms. The proposed decoder is designed to decode two blocks of data simultaneously, increasing throughput. Simulation and synthesis results showed the Constant log BCJR decoder uses less memory and power than an LUT log BCJR decoder.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
This document describes the design of a 4-bit SFQ (Single Flux Quantum) multiplier circuit using a modified Booth encoding technique. It begins with background on multipliers and the advantages of the Booth encoding method over an AND array for reducing the number of partial products. The document then presents the design and analysis of the proposed 4-bit SFQ multiplier using a modified 2-bit Booth encoder, Carry Save Adder tree, and 6-bit carry lookahead adder. Simulation results show the modified Booth encoder approach reduces power consumption by 22.24% and delay by 23.96% compared to a conventional Booth encoder design.
This document describes an FPGA-based address generator for the deinterleaver used in WiMAX systems. It proposes algorithms to generate addresses for the deinterleaver that support different modulation schemes like QPSK, 16-QAM, and 64-QAM without using a floor function. The algorithms are implemented using VHDL on a Xilinx FPGA. Simulation results show the address generation for different modulation types matches the output of a MATLAB program. The FPGA implementation provides better performance and resource utilization than a conventional LUT-based approach.
Similar to Burrows wheeler based data compression and secure transmission (20)
Hudhud cyclone caused extensive damage in Visakhapatnam, India in October 2014, especially to tree cover. This will likely impact the local environment in several ways: increased air pollution as trees absorb less; higher temperatures without tree canopy; increased erosion and landslides. It also created large amounts of waste from destroyed trees. Proper management of solid waste is needed to prevent disease spread. Suggested measures include restoring damaged plants, building fountains to reduce heat, mandating light-colored buildings, improving waste management, and educating public on health risks. Overall, changes are needed to water, land, and waste practices to rebuild the environment after the cyclone removed green cover.
Impact of flood disaster in a drought prone area – case study of alampur vill...eSAT Publishing House
1) In September-October 2009, unprecedented heavy rainfall and dam releases caused widespread flooding in Alampur village in Mahabub Nagar district, a historically drought-prone area.
2) The flood damaged or destroyed homes, buildings, infrastructure, crops, and documents. It displaced many residents and cut off the village.
3) The socioeconomic conditions and mud-based construction of homes in the village exacerbated the flood's impacts, making damage more severe and recovery more difficult.
The document summarizes the Hudhud cyclone that struck Visakhapatnam, India in October 2014. It describes the cyclone's formation, rapid intensification to winds of 175 km/h, and landfall near Visakhapatnam. The cyclone caused extensive damage estimated at over $1 billion and at least 109 deaths in India and Nepal. Infrastructure like buildings, bridges, and power lines were destroyed. Crops and fishing boats were also damaged. The document then discusses coping strategies and improvements needed to disaster management plans to better prepare for future cyclones.
Groundwater investigation using geophysical methods a case study of pydibhim...eSAT Publishing House
This document summarizes the results of a geophysical investigation using vertical electrical sounding (VES) methods at 13 locations around an industrial area in India. The VES data was interpreted to generate geo-electric sections and pseudo-sections showing subsurface resistivity variations. Three main layers were typically identified - a high resistivity topsoil, a weathered middle layer, and a basement rock. Pseudo-sections revealed relatively more weathered areas in the northwest and southwest. Resistivity sections helped identify zones of possible high groundwater potential based on low resistivity anomalies sandwiched between more resistive layers. The study concluded the electrical resistivity method was useful for understanding subsurface geology and identifying areas prospective for groundwater exploration.
Flood related disasters concerned to urban flooding in bangalore, indiaeSAT Publishing House
1. The document discusses urban flooding in Bangalore, India. It describes how factors like heavy rainfall, population growth, and improper land use have contributed to increased flooding in the city.
2. Flooding events in 2013 are analyzed in detail. A November rainfall caused runoff six times higher than the drainage capacity, inundating low-lying residential areas.
3. Impacts of urban flooding include disrupted daily life, damaged infrastructure, and decreased economic activity in affected areas. The document calls for improved flood management strategies to better mitigate urban flooding risks in Bangalore.
Enhancing post disaster recovery by optimal infrastructure capacity buildingeSAT Publishing House
This document discusses enhancing post-disaster recovery through optimal infrastructure capacity building. It presents a model to minimize the cost of meeting demand using auxiliary capacities when disaster damages infrastructure. The model uses genetic algorithms to select optimal capacity combinations. The document reviews how infrastructure provides vital services supporting recovery activities and discusses classifying infrastructure into six types. When disaster reduces infrastructure services, a gap forms between community demands and available support, hindering recovery. The proposed research aims to identify this gap and optimize capacity selection to fill it cost-effectively.
Effect of lintel and lintel band on the global performance of reinforced conc...eSAT Publishing House
This document analyzes the effect of lintels and lintel bands on the seismic performance of reinforced concrete masonry infilled frames through non-linear static pushover analysis. Four frame models are considered: a frame with a full masonry infill wall; a frame with a central opening but no lintel/band; a frame with a lintel above the opening; and a frame with a lintel band above the opening. The results show that the full infill wall model has 27% higher stiffness and 32% higher strength than the model with just an opening. Models with lintels or lintel bands have slightly higher strength and stiffness than the model with just an opening. The document concludes lintels and lintel
Wind damage to trees in the gitam university campus at visakhapatnam by cyclo...eSAT Publishing House
1) A cyclone with wind speeds of 175-200 kph caused massive damage to the green cover of Gitam University campus in Visakhapatnam, India. Thousands of trees were uprooted or damaged.
2) A study assessed different types of damage to trees from the cyclone, including defoliation, salt spray damage, damage to stems/branches, and uprooting. Certain tree species were more vulnerable than others.
3) The results of the study can help in selecting more wind-resistant tree species for future planting and reducing damage from future storms.
Wind damage to buildings, infrastrucuture and landscape elements along the be...eSAT Publishing House
1) A visual study was conducted to assess wind damage from Cyclone Hudhud along the 27km Visakha-Bheemli Beach road in Visakhapatnam, India.
2) Residential and commercial buildings suffered extensive roof damage, while glass facades on hotels and restaurants were shattered. Infrastructure like electricity poles and bus shelters were destroyed.
3) Landscape elements faced damage, including collapsed trees that damaged pavements, and debris in parks. The cyclone wiped out over half the city's green cover and caused beach erosion around protected areas.
1) The document reviews factors that influence the shear strength of reinforced concrete deep beams, including compressive strength of concrete, percentage of tension reinforcement, vertical and horizontal web reinforcement, aggregate interlock, shear span-to-depth ratio, loading distribution, side cover, and beam depth.
2) It finds that compressive strength of concrete, tension reinforcement percentage, and web reinforcement all increase shear strength, while shear strength decreases as shear span-to-depth ratio increases.
3) The distribution and amount of vertical and horizontal web reinforcement also affects shear strength, but closely spaced stirrups do not necessarily enhance capacity or performance.
Role of voluntary teams of professional engineers in dissater management – ex...eSAT Publishing House
1) A team of 17 professional engineers from various disciplines called the "Griha Seva" team volunteered after the 2001 Gujarat earthquake to provide technical assistance.
2) The team conducted site visits, assessments, testing and recommended retrofitting strategies for damaged structures in Bhuj and Ahmedabad. They were able to fully assess and retrofit 20 buildings in Ahmedabad.
3) Factors observed that exacerbated the earthquake's impacts included unplanned construction, non-engineered buildings, improper prior retrofitting, and defective materials and workmanship. The professional engineers' technical expertise was crucial for effective post-disaster management.
This document discusses risk analysis and environmental hazard management. It begins by defining risk, hazard, and toxicity. It then outlines the steps involved in hazard identification, including HAZID, HAZOP, and HAZAN. The document presents a case study of a hypothetical gas collecting station, identifying potential accidents and hazards. It discusses quantitative and qualitative approaches to risk analysis, including calculating a fire and explosion index. The document concludes by discussing hazard management strategies like preventative measures, control measures, fire protection, relief operations, and the importance of training personnel on safety.
Review study on performance of seismically tested repaired shear wallseSAT Publishing House
This document summarizes research on the performance of reinforced concrete shear walls that have been repaired after damage. It begins with an introduction to shear walls and their failure modes. The literature review then discusses the behavior of original shear walls as well as different repair techniques tested by other researchers, including conventional repair with new concrete, jacketing with steel plates or concrete, and use of fiber reinforced polymers. The document focuses on evaluating the strength retention of shear walls after being repaired with various methods.
Monitoring and assessment of air quality with reference to dust particles (pm...eSAT Publishing House
This document summarizes a study on monitoring and assessing air quality with respect to dust particles (PM10 and PM2.5) in the urban environment of Visakhapatnam, India. Sampling was conducted in residential, commercial, and industrial areas from October 2013 to August 2014. The average PM2.5 and PM10 concentrations were within limits in residential areas but moderate to high in commercial and industrial areas. Exceedance factor levels indicated moderate pollution for residential areas and moderate to high pollution for commercial and industrial areas. There is a need for management measures like improved public transport and green spaces to combat particulate air pollution in the study areas.
Low cost wireless sensor networks and smartphone applications for disaster ma...eSAT Publishing House
This document describes a low-cost wireless sensor network and smartphone application system for disaster management. The system uses an Arduino-based wireless sensor network comprising nodes with various sensors to monitor the environment. The sensor data is transmitted to a central gateway and then to the cloud for analysis. A smartphone app connected to the cloud can detect disasters from the sensor data and send real-time alerts to users to help with early evacuation. The system aims to provide low-cost localized disaster detection and warnings to improve safety.
Coastal zones – seismic vulnerability an analysis from east coast of indiaeSAT Publishing House
This document summarizes an analysis of seismic vulnerability along the east coast of India. It discusses the geotectonic setting of the region as a passive continental margin and reports some moderate seismic activity from offshore in recent decades. While seismic stability cannot be assumed given events like the 2004 tsunami, no major earthquakes have been recorded along this coast historically. The document calls for further study of active faults, neotectonics, and implementation of improved seismic building codes to mitigate vulnerability.
Can fracture mechanics predict damage due disaster of structureseSAT Publishing House
This document discusses how fracture mechanics can be used to better predict damage and failure of structures. It notes that current design codes are based on small-scale laboratory tests and do not account for size effects, which can lead to more brittle failures in larger structures. The document outlines how fracture mechanics considers factors like size effect, ductility, and minimum reinforcement that influence the strength and failure behavior of structures. It provides examples of how fracture mechanics has been applied to problems like evaluating shear strength in deep beams and investigating a failure of an oil platform structure. The document argues that fracture mechanics provides a more scientific basis for structural design compared to existing empirical code provisions.
This document discusses the assessment of seismic susceptibility of reinforced concrete (RC) buildings. It begins with an introduction to earthquakes and the importance of vulnerability assessment in mitigating earthquake risks and losses. It then describes modeling the nonlinear behavior of RC building elements and performing pushover analysis to evaluate building performance. The document outlines modeling RC frames and developing moment-curvature relationships. It also summarizes the results of pushover analyses on sample 2D and 3D RC frames with and without shear walls. The conclusions emphasize that pushover analysis effectively assesses building properties but has limitations, and that capacity spectrum method provides appropriate results for evaluating building response and retrofitting impact.
A geophysical insight of earthquake occurred on 21 st may 2014 off paradip, b...eSAT Publishing House
1) A 6.0 magnitude earthquake occurred off the coast of Paradip, Odisha in the Bay of Bengal on May 21, 2014 at a depth of around 40 km.
2) Analysis of magnetic and bathymetric data from the area revealed the presence of major lineaments in NW-SE and NE-SW directions that may be responsible for seismic activity through stress release.
3) Movements along growth faults at the margins of large Bengal channels, due to large sediment loads, could also contribute to seismic events by triggering movements along the faults.
Effect of hudhud cyclone on the development of visakhapatnam as smart and gre...eSAT Publishing House
This document discusses the effects of Cyclone Hudhud on the development of Visakhapatnam as a smart and green city through a case study and preliminary surveys. The surveys found that 31% of participants had experienced cyclones, 9% floods, and 59% landslides previously in Visakhapatnam. Awareness of disaster alarming systems increased from 14% before the 2004 tsunami to 85% during Cyclone Hudhud, while awareness of disaster management systems increased from 50% before the tsunami to 94% during Hudhud. The surveys indicate that initiatives after the tsunami improved awareness and preparedness. Developing Visakhapatnam as a smart, green city should consider governance
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
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- Steps:
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- Allow user to assume the role.
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- Differentiation between PassRole vs AssumeRole
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Mechanical Engineering on AAI Summer Training Report-003.pdf
Burrows wheeler based data compression and secure transmission
1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Special Issue: 02 | Dec-2013, Available @ http://www.ijret.org 14
BURROWS WHEELER BASED DATA COMPRESSION AND SECURE
TRANSMISSION
M.P.Bhuyan1
, V.Deka2
, S.Bordoloi3
1
Department of Information Technology, Gauhati University
2
Department of Information Technology, Gauhati University
3
Department of Computer Applications, Assam Engineering College
Abstract
Now days, computer technology mostly focusing on storage space and speed With the rapid growing of important data and increased
number of applications, devising new approach for efficient compression and encryption methods are playing a vital role in
performance. In this work, burrows wheeler transformation is introduced for pre processing of the input data and made several
performance analysis experiments over different compression techniques for various types of text files and improved compression
ratio has been found by applying burrows wheeler transform as pre-processing step.
Keywords: RLE, arithmetic, Huffman, LZW, lossless data compression.
----------------------------------------------------------------------***--------------------------------------------------------------------
1. INTRODUCTION
It is seen that day by day amount data increases, so it becomes
necessary to optimize the storage space for efficient utilization.
In lossy compression methods, during the decompression
process it is not possible to recover the original file. To
overcome this difficulty we need lossless data compression
technique. Use of lossless data compression technique
reconstructs the original file as it was before the compression.
Lossless data compression is an important compression
technique to compress text files, because removal of much
redundancy in text files causes the change in meaning of the
original data or text. Burrows Wheeler Transform is widely used
in all over the world for lossless data compression [1]. People
have devoted lots of time in innovating new techniques for the
enhancement of lossless data compression algorithm. We will
try to use Burrows Wheeler transform in lossless image
compression and if possible special care can be taken. Further if
possible, we will try to use the technique in the compression of
other kind of files like audio or video files. The rest of the paper
is organized as follows: Section 2 presents a brief explanation
about Burrows Wheeler Transformation; Section 3 discusses
about some existing lossless data compression algorithms,
Section 4 reflects the challenges of combining cryptography and
compression and the cryptographic algorithm, Section 5 has its
focus on comparing the performance of different lossless data
compression algorithms, finally, section 6 concludes the work
and section 7 proposes the future work.
2. BURROWS WHEELER TRANSFORM
Burrows Wheeler Transform is a transformation technique first
introduced in 1994[6], which is the unpublished work by
Wheeler in 1983. The fundamental concept behind this
technique is that when a text file or a character string is
transformed the size of the string does not change. The
transformation only permutes the string into n permutations,
where n is the total number of characters in the string. After
performing Burrows Wheeler Transform new transformed string
can be compressed easily with compression method like run
length encoding. In addition, if move to front encoding is
applied to the transformed data then it can be compressed quite
efficiently.
2.1 The Forward Transform
Consider a string p= dckdacm.
Step1: The original sequence p is copied to the first row, also
referred to as index 0. The sequence is then sorted with all left
cyclic permutations into each next index row. The step 1 of the
BWT is presented in Table 2.1.1
Step2: The rows are sorted lexicographically then from this
output sequences. The step 2 of the BWT is shown in Table
2.1.2. Step 3 is the final step of the BWT process consisting of
output of the BWT and the final index.
Step3: The original sequence p= dckdacm appears in the fifth
row of Table 2.1.2, and the output of the BWT transform is the
last column, indicated by L = ddakmcc which is shown in
table2.1.3.
With the index = 4, the result can be written as BWT = [index,
L], where L is the output of the Burrows-Wheeler transform and
index indicates the location of the original sequence in the
lexicographically ordered sequence. We also determine the first
column F = accddkm, which can be obtained from L by sorting
which is required reverse transform of the BWT.
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Special Issue: 02 | Dec-2013, Available @ http://www.ijret.org 15
Table 2.1.1 step1 of BWT with all cyclic permutations
Index Step1 Output
0 dckdacm
1 ckdacmd
2 kdacmdc
3 dacmdck
4 acmdckd
5 cmdckda
6 mdckdac
Table 2.1.2 step2 of BWT rows of step1 are lexicographically
sorted
Index Step3 Output
0 d
1 d
2 a
3 k
4 m
5 c
6 c
Table 2.1.3 step3 of BWT contains last character of each row of
step1
Index Step2 Output
0 acmdckd
1 ckdacmd
2 cmdckda
3 dacmdck
4 dckdacm
5 kdacmdc
6 mdckdac
2.2 The Reverse Burrows-Wheeler Transform:
The BWT is a reversible transformation which can recover the
original sequence from the BWT output sequence. In reverse
transform only the BWT output sequence L and index are
needed for reconstructing the original sequence. To solve the
reverse BWT using output of the BWT, L and index, the reverse
BWT is presented in Table 2.2.1.
Input (ddakmcc, index=4).
Output=dckdacm
Table 2.2.1 Step1 of reverse BWT
Index Reverse
BWT
input
Previous
combine
Sort New combine
(BWT i/p+
Sort)
0 d Φ a da
1 d Φ c dc
2 a Φ c ac
3 k Φ d kd
4 m Φ d md
5 c Φ k ck
6 c Φ m cm
Table 2.2.2 Step2 of reverse BWT
Index Reverse
BWT
input
Previous
combine
Sort New combine
(BWT i/p+
Sort)
0 d da ac dac
1 d dc ck dck
2 a ac cm acm
3 k kd da kda
4 m md dc mdc
5 c ck kd ckd
6 c cm md cmd
Table 2.2.3 Step3 of reverse BWT
Index Reverse
BWT
input
Previous
combine
Sort New combine
(BWT i/p+
Sort)
0 d dac acm dacm
1 d dck ckd dckd
2 a acm cmd acmd
3 k kda dac kdac
4 m mdc dck mdck
5 c ckd kda ckda
6 c cmd mdc cmdc
Table 2.2.4 Step4 of reverse BWT
Index Reverse
BWT
input
Previous
combine
Sort New combine
(BWT i/p+
Sort)
0 d dac acm dacm
1 d dck ckd dckd
2 a acm cmd acmd
3 k kda dac kdac
4 m mdc dck mdck
5 c ckd kda ckda
6 c cmd mdc cmdc
3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Special Issue: 02 | Dec-2013, Available @ http://www.ijret.org 16
Table 2.2.5 Step5 of reverse BWT
Ind
ex
Reverse
BWT
input
Previous
combine
Sort New
combine
(BWT i/p+
Sort)
0 d dacmd acmdc dacmdc
1 d dckda ckdac dckdac
2 a acmdc cmdck acmdck
3 k kdacm dacmd kdacmd
4 m mdckd dckda mdckda
5 c ckdac kdacm ckdacm
6 c cmdck mdckd cmdckd
Table 2.2.6 Step6 of reverse BWT
Inde
x
Reverse
BWT
input
Previous
combine
Sort New combine
(BWT i/p+
Sort)
0 d dacmdc acmdck acmdckd
1 d dckdac ckdacm ckdacmd
2 a acmdck cmdckd cmdckda
3 k kdacmd dacmdc dacmdck
4 m mdckda dckdac dckdacm
5 c ckdacm kdacmd kdacmdc
6 c cmdckd mdckda mdckdac
Burrows Wheeler transformation is used in various field of
research from the beginning of its invention, it is seen that the
importance of Burrows Wheeler Transform is increased day by
day. It is widely used as a pre processing stage in lossless data
compression. BWT is used to compress DNA sequencing in the
field of bioinformatics. Research is going on to compress the
medical information or some astronomical images. Due to the
efficiency of BWT, researchers from various backgrounds are
attracted to this technique and use this technique to optimize
their resources. So many people try to improve the BWT
technique for better processing in their own fields. In the
coming days, this technique may overcome the deficiency of
storage space.
3. SOME LOSSLESS DATA COMPRESSION
ALGORITHMS
3.1 Run Length Encoding
Run Length Encoding (RLE) compression technique is used
when a given file contains too many redundant data or long run
of similar characters. The repeated string or characters present
in the input file or message is called a run which is encoded into
two bytes. The first byte represents the value of the character in
the run and the second byte contains the number of times given
character appears in the run. For example the following string
can be represented in RLE as
ZZZZZZkkkHHHHHttt
Z6k3H5t3
3.2 Huffman Coding
Huffman coding is a data compression technique in which each
input character is replaced with variable length binary digits
which are called codeword and the codeword has been derived
in a particular way based on the probability of occurrence of
each symbol or character. The most frequent symbols in the
source have the shortest length code and the least frequent
symbol has the longest code. This technique is implemented by
creating a binary tree of nodes. These can be stored in data
structures like array or link list, the size of which depends on the
number of symbols, n.
3.2 Arithmetic Coding
The arithmetic coding concept is to have a probability value 0 to
1, and assign to every symbol a range in between 0 and 1 based
on its probability, higher the probability, higher is the range.
Once we have defined the ranges and the probability, encoding
of symbols can be started, every symbol in encoding process
gives us a new floating point range to encode the next symbol.
3.4 LZW Coding
This is a dictionary based compression algorithm which is
implemented by depending on a dictionary. A dictionary is a
collection of some possible words of a particular language and
is stored in tabular fashion, some indexes are used to represent
repeating symbols. In Lempel-Ziv Welch algorithm or LZW,
one kind dictionary is used to store the symbols. In the
compression process, the index values are used in place of the
similar repeated strings or symbols. Creation of dictionary is a
dynamic process, so it is not transferred with the encoded data,
during decompression the dictionary is created automatically.
4. CHALLENGES OF COMBINING COMPRE-
SSION AND CRYPTOGRAPHY AND THE
CRYPTOGRAPHIC ALOGORITHM USED IN THIS
ANALYSIS
Most of the powerful cryptographic algorithms increase size
after encryption and if we modify the algorithm then strength of
the algorithm decreases. So we need algorithms of the type
stream cipher, substitution cipher etc. One substitution type
algorithm is given below.
Encryption Algorithm:
Step 1: Input Text (T)
Step 2: Check ASCII value of each character
Step 3: If (Character (ASCII value)>127)
4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Special Issue: 02 | Dec-2013, Available @ http://www.ijret.org 17
ASCII value=255-ASCII value of the character
Else
ASCII value=127+ASCII value of the character
Step 4: Now print the corresponding character of the ASCII
value in ENCRYPT.txt file.
Decryption Algorithm:
Step1: Check each character of the file ENCRYPT.txt
Step 2: If (Character (ASCII value)>127)
ASCII value= ASCII value-127
Else
ASCII value=255-ASCII value of the character
Step 3: Now print the corresponding character of the ASCII
value in DECRYPT.txt.
5. PERFORMANCE ANALYSIS
The performance analysis of the compression algorithms are
done for different text files of different size. Comparison is done
in terms of compression ratio which is the ratio of the size of
file after compression to the size of file before compression. The
comparison is also shown graphically. Text files of different
size with different characters have been taken and then
compression is done in MATLAB for the different compression
algorithms. The results are shown in the table 5.1 and 5.2. The
following charts showing the comparison graphically for
different algorithms with respect to different text files.
Fig 5.1 Comparison of compressed files in Arithmetic Coding
Fig 5.2 Comparison of compressed files in Huffman Coding
Fig 5.3 Comparison of compressed files in Run Length
Encoding
Fig 5.4 Comparison of compressed files in LZW Coding
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Special Issue: 02 | Dec-2013, Available @ http://www.ijret.org 18
Fig 5.5 Comparison of Average Compression ratio of different
algorithms
From the analysis it is seen that RLE compression has shown
drastic improvement and LZW has shown a little improvement
in the compression ratio after preprocessing with Burrows
Wheeler Transform and encryption. Though the other
compression algorithms have not shown much improvement in
compression ratio after preprocessing with Burrows Wheeler
Transform For the time being RLE has performed much better
with pre-processing with Burrows Wheeler Transform and
encryption.
6. CONCLUSIONS
After doing a detail study on different compression algorithms it
is seen that RLE shows a great improvement on compression
ratio after preprocessing with Burrows Wheeler Transformation.
With these results we can conclude that the combination of
Burrows Wheeler Transform and RLE gives us a best
compression method for lossless data compression.
FUTURE WORK
In future it is possible to apply the same technique to compress
image, audio and video files etc. It is possible to make the
encryption process powerful by using some powerful algorithms
like Blowfish, RC5 etc.
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