Ee660 ex 24_bi_cmos_comparisons_all

1. EXERCISE 24: BiCMOS Circuit Comparisons 1
Exercise 24: BiCMOS Circuit Comparisons
L. Schwappach, T. Thede, D. Wehnes
EE660: Modern Electronic Design
Colorado Technical University
November 2011

2. EXERCISE 24: BiCMOS Circuit Comparisons 2
Exercise 24: BiCMOS Circuit Comparisons
Objectives:
The objective of this exercise is to evaluate new BiCMOS technologies and systems and
identify elements which could be used to facilitate or improve a design using SPICE modeling.
To achieve these goals four circuits, to include a CMOS inverter, a BiCMOS emitter follower, a
BiCMOS common emitter and a BiCMOS gated diode must be evaluated. In addition, each
circuit must be evaluated to determine the viability of using such circuits in a design once the
power supply voltages and device sizes have been reduced.
Theory and Design Approaches/Trade-offs:
First of all, all four circuits needed to be created in SPICE as shown below with the
model parameters given by the instructor as shown in the table below:
Device/Parameter VTO KP LAMBDA
2
PMOS -1.0 V 32uA/V 0.004
NMOS 1.5 V 72uA/V2 0.002
Table 1: PMOS and NMOS Model Specifications for Circuits.
Initially all four circuits need to be provided an input voltage (Vdd) of +5 VDC and given
device sizes: PMOS: W=84um, L=1um; NMOS: W=40um, L=1um. These four circuits must
then be analyzed using SPICE to determine their critical characteristics. In part 2 of the exercise,
the input voltage will be lowered to +3.3 VDC and the size of the devices were lowered to:
PMOS: W=56um, L=.67um; NMOS: W=26.4um, L=.67um. The circuits must again be
analyzed in order to determine their critical characteristics by using SPICE and comparing the
circuits to the performance of the circuits at +5 VDC. In part 3 of this exercise, the input voltage

3. EXERCISE 24: BiCMOS Circuit Comparisons 3
is lowered to +1.8 VDC and the size of the devices is lowered to: PMOS: W=30um, L=.36um;
NMOS: W=14.4um, L=.36um. The circuits are again analyzed to determine their critical
characteristics using SPICE and compared to the performance of the circuits at +5 VDC and +3.3
VDC. Each circuit must be compared in terms of speed, power, and noise immunity with the
benefits and disadvantages of each circuit discussed.
The required device sizes and power requirement changes for the four circuits modeled in
PSPICE are illustrated by Table 2 below.
Evaluation NMOS W/L PMOS W/L Power Supply
Number
1 40um/1um 84um/1um 5V
2 26.4um/.67um 56um/.67um 3.3V
3 14.4um/.36um 30um/.36um 1.8V
Table 2: PMOS and NMOS Physical Specifications for Circuits
Finally as an additional step to this exercise, in order to avoid the Vthreshold problems that
were discovered while decreasing device sizes to allow for the 1.8VDD power supplies used in
Exercise 23 the PMOS and NMOS models for the 1.8V models in this exercise were adjusted
according to device shrinking scaling rules. The 1.8V circuits PMOS Vthreshold values were
adjusted to -.4356mV and the 1.8V circuits NMOS Vthreshold values was adjusted to 653mV.

4. EXERCISE 24: BiCMOS Circuit Comparisons 4
Schematics:
Figure 1: Schematic Used for Circuits where VDD = 5V, VGate modified according to Analysis

5. EXERCISE 24: BiCMOS Circuit Comparisons 5
Figure 2: Schematic Used for Circuits to Isolate Power Supplies where VDD = 5V

6. EXERCISE 24: BiCMOS Circuit Comparisons 6
Figure 3: Schematic Used for Circuits when VDD = 3.3V, VGate modified according to Analysis

7. EXERCISE 24: BiCMOS Circuit Comparisons 7
Figure 4: Schematic Used for Circuits to Isolate Power Supplies when VDD = 3.3V

8. EXERCISE 24: BiCMOS Circuit Comparisons 8
Figure 5: Schematic Used for Circuits when VDD = 1.8V, VGate modified according to Analysis

9. EXERCISE 24: BiCMOS Circuit Comparisons 9
Figure 6: Schematic Used for Circuits to Isolate Power Supplies when VDD = 1.8

10. EXERCISE 24: BiCMOS Circuit Comparisons 10
Analysis
VThreshold and Noise Margins
Using SPICE, the DC transfer characteristics were determined by running a DC Sweep of
VGate from 0V to (VDD)V in .001V increments. The results of all three simulations are
displayed below. The traces of Vout verified that the CMOS, BiCMOS Emitter Follower and
BiCMOS Gated Diode circuits functioned as inverters while the BiCMOS Common Emitter
circuit was not functioning as an inverter due to a 180 degree phase shift. The Vin threshold
voltage was determined by looking at the middle of the vertical linear regions where
Vout=((Vout(High) – Vout(Low))/2 + Vout(Low)) with the results shown in the table below.
Figure 7: VTH and Noise Margin Results where VDD = 5V

11. EXERCISE 24: BiCMOS Circuit Comparisons 11
Figure 8: VTH and Noise Margin Results where VDD = 3.3V
Figure 9: VTH and Noise Margin Results where VDD = 1.8V

12. EXERCISE 24: BiCMOS Circuit Comparisons 12
The noise margins for these circuits were calculated as follows and are shown in the table:
Noise Margin (High) = Vout(High) – Vin(High)
Noise Margin (Low) = Vin(Low) – Vout(Low)
VDD Parameter Ideal CMOS Emitter Common Gated
Case Follower Emitter Diode
5V VThreshold 2.5V 2.73V 3.61V 2.79V 2.72V
5V NMH 2.5V 1.651V 1.129V 1.594V 1.246V
5V NML 2.5V 2.096V 3.203V 2.319V 1.689V
3.3V VThreshold 1.65V 1.89V 2.17V 1.9V 1.88V
3.3V NMH 1.65V 1.213V 237mV 1.172V 998mV
3.3V NML 1.65V 1.685V 1.874V 1.658V 1.499V
1.8V VThreshold 900mV 1.002V 1.338V 1.010V 988mV
1.8V NMH 900mV 623mV 315mV 588mV 451mV
1.8V NML 900mV 820mV 996mV 783mV 638mV
Table 3: Vthreshold and Noise Margin Results
High noise margins are needed to avoid errors. The CMOS circuit displayed a good
Vthreshold and the best NMH. The BiCMOS Emitter Follower displayed the best NML but had
the worst Vthreshold and NMH results. The BiCMOS Common Emitter displayed poor
Vthreshold results and a range of sufficient to poor NMH and NML results. The BiCMOS Gated
Diode had the closest Vthreshold to the Ideal however it suffers from a poor NMH and the worst
NML. As the devices shrink in size the Noise margin performance continues with the exception
of the CMOS inverter whose NML gets better than the BiCMOS Common Emitter circuit.
However due to the common emitters 180 degree phase shift it cannot function as an inverter for
logic functions.

13. EXERCISE 24: BiCMOS Circuit Comparisons 13
Power Usage Results
Each circuit was provided an independent VDD for the power usage comparison of the
four CMOS/BiCMOS devices. The simulation results follow:
Figure 10: Power Usage where VDD = 5V

14. EXERCISE 24: BiCMOS Circuit Comparisons 14
Figure 11: Power Usage where VDD = 3.3V
Figure 12: Power Usage where VDD = 1.8V

15. EXERCISE 24: BiCMOS Circuit Comparisons 15
VDD Parameter CMOS Emitter Common Gated
Case Follower Emitter Diode
5V Power Used
25pW 157pW 109mW 257pW
At Vgate = 0V
5V Power Used
25pW 448pW 90mW 6nW
At Vgate = 5V
5V Max Power Used 11mW 179mW 855mW 207mW
3.3V Power Used
11pW 66pW 24mW 96pW
At Vgate = 0V
3.3V Power Used
11pW 166pW 15mW 2.2nW
At Vgate = 3.3V
3.3V Max Power Used 731uW 12mW 108mW 57nW
1.8V Power Used
3pW 18pW 4mW 22pW
At Vgate = 0V
1.8V Power Used
3pW 37pW 3mW 513pW
At Vgate = 1.8V
1.8V Max Power Used 316uW 4mW 47mW 5nW
Table 4: Power Usage Results
From the analysis above the BiCMOS Common Emitter uses large amounts of power
even while offline. The BiCMOS Gated Diode is second in power usage but gains a slight
advantage over the BiCMOS Emitter Follower and CMOS inverters at smaller device sizes.
AC Characteristics
Using SPICE, the AC characteristics were also determined for the circuits. The AC small
signal characteristics were obtained by changing the input voltage source from a DC source to an
AC source and by changing the DC value of the new source to each threshold voltage. A bias
point small signal analysis was developed in SPICE with the output next below and compared in
a table to follow.

16. EXERCISE 24: BiCMOS Circuit Comparisons 16
Figure 13: Small Signal Characteristics of CMOS, BiCMOS Emitter Follower, BiCMOS
Common Emitter, and BiCMOS Gated Diode when VDD = 5V

17. EXERCISE 24: BiCMOS Circuit Comparisons 17
Figure 14: Small Signal Characteristics of CMOS, BiCMOS Emitter Follower, BiCMOS
Common Emitter, and BiCMOS Gated Diode when VDD = 3.3V

18. EXERCISE 24: BiCMOS Circuit Comparisons 18
Figure 15: Small Signal Characteristics of CMOS, BiCMOS Emitter Follower, BiCMOS
Common Emitter, and BiCMOS Gated Diode when VDD = 1.8V

19. EXERCISE 24: BiCMOS Circuit Comparisons 19
VDD Parameter Ideal CMOS Emitter Common Gated
Case Follower Emitter Diode
5V Gain Inf. -538 -11 31 -93
5V Input Inf. Ohms 1e20 ohms 1e20 ohms 1e20 ohms 1e20 ohms
Impedance
5V Output Zero 77k ohms 73 ohms 100 ohms 377 ohms
Impedance Ohms.
3.3V Gain Inf. -10 -30 127 -1.2k
3.3V Input Inf. Ohms 1e20 ohms 1e20 ohms 1e20 ohms 1e20 ohms
Impedance
3.3V Output Zero 4.78k ohms 446 ohms 495 ohms 9.4e8 ohms
Impedance Ohms.
1.8V Gain Inf. -1.88k -3 142 -1.17k
1.8V Input Inf. Ohms 1e20 ohms 1e20 ohms 1e20 ohms 1e20 ohms
Impedance
1.8V Output Zero 951k ohms 386 ohms 593 ohms 5.047G
Impedance Ohms. ohms
Table 5: Small Signal Characteristic Results
From the results shown the CMOS inverter offers the best choice as an amplifier circuit
when connected to a 5V and 1.8V power supply, however when connected to the 3.3V power
supply it functioned the worst. The BiCMOS emitter follow had the best input and output
impedance of the four circuits and thus would function great as a buffer and with several
additional output devices. The small signal characteristics remain steady as the devices decrease
however the output impedance becomes much greater after each technology reduction.
Frequency Analysis
A frequency analysis of the circuits was obtained by running an AC Sweep/Noise
analysis of the circuits. Bode plots were created highlighting the corner frequency (-3dB) point
of the circuits. The results follow:

20. EXERCISE 24: BiCMOS Circuit Comparisons 20
Figure 16: Frequency Analysis Results of CMOS Circuit when VDD = 5V
Figure 17: Frequency Analysis Results of BiCMOS Emitter Follower Circuit when VDD =
5V

21. EXERCISE 24: BiCMOS Circuit Comparisons 21
Figure 18: Frequency Analysis Results of BiCMOS Common Emitter Circuit when VDD =
5V
Figure 19: Frequency Analysis Results of BiCMOS Gated Diode Circuit when VDD = 5V
Figure 20: Frequency Analysis Results of CMOS Circuit when VDD = 3.3V

22. EXERCISE 24: BiCMOS Circuit Comparisons 22
Figure 21: Frequency Analysis Results of BiCMOS Emitter Follower Circuit when VDD =
3.3V
Figure 22: Frequency Analysis Results of BiCMOS Common Emitter Circuit when VDD =
3.3V

23. EXERCISE 24: BiCMOS Circuit Comparisons 23
Figure 23: Frequency Analysis Results of BiCMOS Gated Diode Circuit when VDD = 3.3V
Figure 24: Frequency Analysis Results of CMOS Circuit when VDD = 1.8V

24. EXERCISE 24: BiCMOS Circuit Comparisons 24
Figure 25: Frequency Analysis Results of BiCMOS Emitter Follower Circuit when VDD =
1.8V
Figure 26: Frequency Analysis Results of BiCMOS Common Emitter Circuit when VDD =
1.8V

25. EXERCISE 24: BiCMOS Circuit Comparisons 25
Figure 27: Frequency Analysis Results of BiCMOS Gated Diode Circuit when VDD = 1.8V
VDD Parameter Ideal CMOS Emitter Common Gated
Case Follower Emitter Diode
5V F3db Inf. Hz 52 Hz 56k Hz 39k Hz 10 k Hz
3.3V F3db Inf. Hz 830 Hz 8.9k Hz 7.8k Hz 1.4 Hz
1.8V F3db Inf. Hz 4.4 Hz 10k Hz 6.5k Hz 1.4 Hz
Table 6: Corner Frequency Results
From the results of the frequency analysis it seems that the BiCMOS Emitter Follower
has the best frequency response and as device sizes shrink the circuits f3dB frequency decreases.
With the benefits of low power usage the BiCMOS Emitter Follower looks to be the ideal
power/speed inverter technology combination, however the results of the propagation delay
analysis should offer more insight.

26. EXERCISE 24: BiCMOS Circuit Comparisons 26
Time Domain Analysis (Rise and Fall Times, Propagation Delays)
The rise time for the circuits is calculated by taking the time at the point each output rose
from low to ninety percent of the high output and subtracting the time at which each output rose
from low to ten percent of the high output. This is defined by the following formula:
TR = Trise(.9Vout) – Trise(.1Vout) or t4 – t2 below.
The fall time for the circuits is calculated by taking the time at the point each output fell
from high to ten percent of the high output and subtracting the time at which each output fell
from high to ninety percent of the high output. This is defined by the following formula:
TF = Tfall(.1Vout) – Tfall(.9Vout) or t8-t6 below.
The low to high propagation delay time (tPLH) for a circuit is calculated by taking the time
at the point the output has risen from low to fifty percent of the high input voltage and
subtracting the time at which the input voltage dropped to its fifty percent voltage point. tPLH is
defined by t3-t1 on the following results.
The high to low propagation delay time (tPHL) for a circuit is calculated by taking the time
at the point the output has fallen from high to fifty percent of the high input voltage and
subtracting the time at which the input voltage rose to its fifty percent voltage point. tPHL is
defined by t7-t5 on the following results.
The total propagation delay is the sum of tPLH and tPHL. There are several methods for
stating fMAX. This lab will simplify fMAX to 1/tP.

27. EXERCISE 24: BiCMOS Circuit Comparisons 27
Figure 28: Time Domain Analysis Results of CMOS at VDD = 5V
Figure 29: Time Domain Analysis Results of BiCMOS Emitter Follower at VDD = 5V

28. EXERCISE 24: BiCMOS Circuit Comparisons 28
Figure 30: Time Domain Analysis Results of BiCMOS Common Emitter at VDD = 5V
Figure 31: Time Domain Analysis Results of BiCMOS Gated Diode at VDD = 5V

29. EXERCISE 24: BiCMOS Circuit Comparisons 29
Figure 32: Time Domain Analysis Results of CMOS at VDD = 3.3V
Figure 33: Time Domain Analysis Results of BiCMOS Emitter Follower at VDD = 3.3V

30. EXERCISE 24: BiCMOS Circuit Comparisons 30
Figure 34: Time Domain Analysis Results of BiCMOS Common Emitter at VDD = 3.3V
Figure 35: Time Domain Analysis Results of BiCMOS Gated Diode at VDD = 3.3V

31. EXERCISE 24: BiCMOS Circuit Comparisons 31
VDD Parameter Ideal CMOS Emitter Common Gated
Case Follower Emitter Diode
5V tR 0s 10.914us 265ns 525ns 386ns
5V tF 0s 12.294us 2.27us 346ns 367ns
5V tPLH 0s 4.723us 135ns 387ns 203ns
5V tPHL 0s 5.691us 947ns 256ns 202ns
5V tP 0s 10.414us 1.082us 643ns 405ns
5V fMAX Inf. Hz 96k Hz 924k Hz 1.555 MHz 2.469MHz
3.3V tR 0s 20.745us 303ns 491ns 505ns
3.3V tF 0s 27.522us 4.346us 396ns 616ns
3.3V tPLH 0s 7.324us 146ns 491ns 261ns
3.3V tPHL 0s 14.251us 1.887us 291ns 344ns
3.3V tP 0s 21.575us 2.033us 782ns 605ns
3.3V fMAX Inf. Hz 46k Hz 492k Hz 1.279M Hz 1.653M Hz
1.8V tR 0s 33.158us 3.097us 662ns 1.421us
1.8V tF 0s 39.754us 9.227us 455ns 1.533us
1.8V tPLH 0s 14.732us 146ns 457ns 347ns
1.8V tPHL 0s 19.033us 2.813us 323ns 376ns
1.8V tP 0s 33.765us 2.959us 780ns 723ns
1.8V fMAX Inf. Hz 30k Hz 338k Hz 1.282M Hz 1.383M Hz
Table 7: Corner Frequency Results
From the time domain analysis results above the CMOS has the slowest switching speed
of the four circuits. The BiCMOS Emitter Follower was also slower than expected as the
frequency analysis showed that it would be the fastest of the four. However, with the new data it
appears that the BiCMOS Gated Diode offers the best combination of switching speed and low
power usage of the four devices.

32. EXERCISE 24: BiCMOS Circuit Comparisons 32
Conclusion
From all of the simulation results comparing the four devices as device sizes shrink the
1.8V BiCMOS Gated diode inverter offers a 1.4MHz switching speed at a cost of 5nW of power
during switching. However it suffers from extremely large output impedance and poor noise
margins. The 3.3V BiCMOS Gated diode also offers the fast switching speeds and low power
usage (57nW of power during switching). The BiCMOS Common Emitter has a 180 degree
phase shift preventing its use as configured for inversion and requires a massive amount of
power (when compared to the other devices) making it a poor choice for small digital logic
devices. The CMOS inverter offers the best noise margin performance and low power utilization
of the four devices but suffers from the slowest switching speed making it an impractical option
for high speed electronics. Finally, the BiCMOS Emitter Follower circuit performs good
inversion at speeds lower than the Gated Diode, yet fast when compared solely to the CMOS
device. The BiCMOS Emitter Follower also had the lowest output impedance allowing for a
larger fanout than the other three technologies, consumes less power than the Common Emitter
and Gated Diode when not inverting. Of the three BiCMOS device sizes compared the 1.8V
sized device seems to have the greatest benefits offering a small device size with low power
utilization with only a small decrease in switching frequency speed.