International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Multilevel DC Link Inverter with Reduced Switches and BatteriesIJPEDS-IAES
Multilevel inverters are the best solution for medium and high voltage power electronic drives. Because of its unique characteristic of synthesizing sinusoidal voltage with less harmonic contents using several DC sources. In a three phase multilevel inverter, each phase of a cascaded H-bridge inverter requires ‘n’ DC sources to obtain 2n + 1 output voltage levels. One particular disadvantage is that, it increases number of power semiconductor switches. To overcome this disadvantage a multilevel DC link inverter (MLDCLI) with reduced number of switches and batteries is proposed.
Stand alone regulated single phase five level inverter with coupled inductorIAEME Publication
This document summarizes a research paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a stand-alone regulated single phase five level inverter with a coupled inductor. It includes a high step-up DC-DC converter as a front-end stage to stabilize the output voltage from a variable DC source. The converter uses a coupled inductor to attain high voltage gain. The inverter can produce a five level AC output without variation in amplitude. The operation of the DC-DC converter and inverter are explained. Simulation and experimental results demonstrate the circuit can provide a constant output voltage waveform from different DC input voltages.
Comparison of thd reduction for asymmetrical cascaded h bridge invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A seven level cascaded multilevel dstatcom for compensation of reactive power...IAEME Publication
This document describes a seven-level cascaded multilevel DSTATCOM system for compensating reactive power and harmonics. It uses a cascaded H-bridge multilevel inverter with either phase shifted PWM or level shifted PWM modulation techniques. Simulation results show the system is able to compensate load current harmonics and reactive power, reducing the total harmonic distortion of source currents from 36.89% to 4.37% with a seven-level inverter using phase shifted PWM. The DSTATCOM provides unity power factor correction at the point of common coupling.
This document discusses cascaded H-bridge multilevel inverters and their symmetrical and asymmetrical configurations. It begins by introducing two-level and multilevel inverters, noting that multilevel inverters are better suited for high power and voltage applications as they reduce harmonics. There are three main multilevel inverter topologies: neutral-point-clamped, flying capacitors, and cascaded H-bridges. The cascaded H-bridge topology connects H-bridge cells in series to generate stepped voltage waveforms. Symmetrical configurations use equal DC voltages for each cell, while asymmetrical configurations use unequal voltages, allowing more voltage levels with the same number of cells. The document presents simulations of
A review of pfc boost converters for hybrid electric vehicle battery chargersiaemedu
1) The document reviews different types of PFC boost converters that can be used for Plug-in Hybrid Electric Vehicle (PHEV) battery chargers, including conventional, bridgeless, interleaved, and bridgeless interleaved topologies.
2) The conventional boost converter is well-suited for power levels up to 1 kW due to diode bridge losses and heat dissipation issues at higher power. The bridgeless topology avoids the rectifier bridge but has EMI and voltage sensing challenges.
3) Interleaved and bridgeless interleaved topologies offer improvements like lower ripple current and higher effective switching frequency, making them suitable for power levels up to 3 kW and 5 kW, respectively.
This document summarizes a research paper on a high efficiency three phase nine level diode clamped multilevel inverter. The paper proposes a nine level diode clamped multilevel inverter (DCMLI) topology for medium voltage applications. It describes the working of the DCMLI, which uses nine levels of voltage from the DC supply to produce a nine step output voltage waveform with lower total harmonic distortion compared to other lower level inverters. Simulation results show that the nine level inverter produces a line voltage waveform with 7.84% THD, lower than the 10.47% THD of a seven level inverter. The paper concludes that increasing the number of levels in the DCMLI reduces the total harmonic distortion
ACADEMIC MATLAB SIMULATION 2013/14/15 PROJECTS FOR
• ELECTRICAL AND ELECTRONICs ENGINEERING[EEE]
• POWER ELECTRONICs AND DRIVES[PED]
• POWER SYSTEMS[PS]….
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We also write papers for your projects and give guidance for paper publishing.
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Multilevel DC Link Inverter with Reduced Switches and BatteriesIJPEDS-IAES
Multilevel inverters are the best solution for medium and high voltage power electronic drives. Because of its unique characteristic of synthesizing sinusoidal voltage with less harmonic contents using several DC sources. In a three phase multilevel inverter, each phase of a cascaded H-bridge inverter requires ‘n’ DC sources to obtain 2n + 1 output voltage levels. One particular disadvantage is that, it increases number of power semiconductor switches. To overcome this disadvantage a multilevel DC link inverter (MLDCLI) with reduced number of switches and batteries is proposed.
Stand alone regulated single phase five level inverter with coupled inductorIAEME Publication
This document summarizes a research paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a stand-alone regulated single phase five level inverter with a coupled inductor. It includes a high step-up DC-DC converter as a front-end stage to stabilize the output voltage from a variable DC source. The converter uses a coupled inductor to attain high voltage gain. The inverter can produce a five level AC output without variation in amplitude. The operation of the DC-DC converter and inverter are explained. Simulation and experimental results demonstrate the circuit can provide a constant output voltage waveform from different DC input voltages.
Comparison of thd reduction for asymmetrical cascaded h bridge invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A seven level cascaded multilevel dstatcom for compensation of reactive power...IAEME Publication
This document describes a seven-level cascaded multilevel DSTATCOM system for compensating reactive power and harmonics. It uses a cascaded H-bridge multilevel inverter with either phase shifted PWM or level shifted PWM modulation techniques. Simulation results show the system is able to compensate load current harmonics and reactive power, reducing the total harmonic distortion of source currents from 36.89% to 4.37% with a seven-level inverter using phase shifted PWM. The DSTATCOM provides unity power factor correction at the point of common coupling.
This document discusses cascaded H-bridge multilevel inverters and their symmetrical and asymmetrical configurations. It begins by introducing two-level and multilevel inverters, noting that multilevel inverters are better suited for high power and voltage applications as they reduce harmonics. There are three main multilevel inverter topologies: neutral-point-clamped, flying capacitors, and cascaded H-bridges. The cascaded H-bridge topology connects H-bridge cells in series to generate stepped voltage waveforms. Symmetrical configurations use equal DC voltages for each cell, while asymmetrical configurations use unequal voltages, allowing more voltage levels with the same number of cells. The document presents simulations of
A review of pfc boost converters for hybrid electric vehicle battery chargersiaemedu
1) The document reviews different types of PFC boost converters that can be used for Plug-in Hybrid Electric Vehicle (PHEV) battery chargers, including conventional, bridgeless, interleaved, and bridgeless interleaved topologies.
2) The conventional boost converter is well-suited for power levels up to 1 kW due to diode bridge losses and heat dissipation issues at higher power. The bridgeless topology avoids the rectifier bridge but has EMI and voltage sensing challenges.
3) Interleaved and bridgeless interleaved topologies offer improvements like lower ripple current and higher effective switching frequency, making them suitable for power levels up to 3 kW and 5 kW, respectively.
This document summarizes a research paper on a high efficiency three phase nine level diode clamped multilevel inverter. The paper proposes a nine level diode clamped multilevel inverter (DCMLI) topology for medium voltage applications. It describes the working of the DCMLI, which uses nine levels of voltage from the DC supply to produce a nine step output voltage waveform with lower total harmonic distortion compared to other lower level inverters. Simulation results show that the nine level inverter produces a line voltage waveform with 7.84% THD, lower than the 10.47% THD of a seven level inverter. The paper concludes that increasing the number of levels in the DCMLI reduces the total harmonic distortion
ACADEMIC MATLAB SIMULATION 2013/14/15 PROJECTS FOR
• ELECTRICAL AND ELECTRONICs ENGINEERING[EEE]
• POWER ELECTRONICs AND DRIVES[PED]
• POWER SYSTEMS[PS]….
We Can also Develop Your Own Ideas and Your IEEE Papers With Extension also…
We also write papers for your projects and give guidance for paper publishing.
For Further Details Call Us @
0-9347143789/9949240245
Visit us at: www.asokatechnologies.in
For Abstracts of IEEE papers and For Any Queries
Mail us : asokatechnologies@gmail.com
The document contains a list of 134 topics related to power electronics and drives. The topics cover various fields including renewable energy, multilevel converters, resonant converters, Z-source inverters, industrial drive control applications for traction systems and aircraft, and more. The list provides a short description for each topic and indicates the corresponding research field.
Harmonic Minimization In Multilevel Inverters By Using PSOIDES Editor
Harmonic Elimination in a multilevel inverters is
an optimization problem which is solved by applying particle
swarm optimization (PSO) technique. The derived equation
for the computation of total harmonic distortion (THD) of the
output voltage of the multilevel inverter is used as the objective
function in PSO algorithm. The objective function used is to
reduce the THD of the multilevel inverter and obtain the
corresponding switching angles with the elimination of
possible lower order harmonics. In this paper a pseudo code
based algorithm is proposed to deal with inequality constraints
which will helps in accelerating the optimization process. The
proposed method is applied for seven level cascade inverter to
eliminate the 5th and 7th order harmonics to reduce the total
harmonic distortion .This proposed PSO algorithm is effective
in reducing the total harmonic distortion corresponding the
range of modulation index. The simulation results shows that
the proposed PSO method is indeed capable of obtaining
higher quality of solutions to eliminate 5th and 7th order
harmonics and to reduce the total harmonic distortion of 7-
level cascade inverter
Simulation and study of multilevel inverter (report)Arpit Kurel
The document discusses the simulation and study of a multilevel inverter. It begins with an abstract that outlines that multilevel inverters are used to convert DC power to AC power at required voltage and frequency levels for applications like motor drives and grid connections. It then discusses different multilevel inverter topologies like diode clamped, flying capacitor, and cascaded H-bridge. For this project, a three phase five level inverter is simulated using sinusoidal PWM technique in MATLAB/Simulink. The topology used is a cascaded H-bridge inverter with separate DC sources. The multilevel inverter reduces harmonic contents in the output waveform compared to a three level inverter.
A solar power generation system with a seven level invertershashank chelpuri
This document proposes a new solar power generation system composed of a DC/DC boost converter and a novel seven-level inverter. The seven-level inverter uses only six switches, simplifying the circuit. It operates in different modes to produce varying output voltages. Simulation results show the system works as intended. Advantages of solar include being renewable, producing electricity and heat with little maintenance, while disadvantages are lack of power at night and during cloud cover.
Hybrid topology of asymmetric cascaded multilevel inverter with renewable ene...Asoka Technologies
This paper presents a binary topology of Multimodule level inverters produce a staircase output voltage from renewable DC voltage sources. The MLI (Multi Level Inverter) Requires many number of semiconductor switches is main drawback of multilevel inverters. The MLI can be classified as two method, one is symmetric and another asymmetric converters. In symmetrical multilevel inverter can apply same voltage level to all cascaded circuit, in asymmetric multilevel inverters can be vary input source voltage at each cascaded H-bridge by using binary algorithm. In this paper, a discrete binary topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converter can produce sixty three levels of voltage from five discrete DC source. The Total Harmonic Distortions (THD) is minimized by discrete binary topology. The working operation and performance of the proposed multilevel inverters studies has been verified by simulation of using SIMULINK / MA TLAB results.
SIMULATION AND STUDY OF MULTILEVEL INVERTER (ppt)Arpit Kurel
This document discusses the simulation and study of a multilevel inverter. It aims to simulate a three-phase five-level inverter using MATLAB/Simulink. Multilevel inverters are attractive for medium-voltage high-power applications as they can produce outputs with low distortion at medium voltages. The document reviews literature on multilevel inverters and various topologies. It then discusses objectives of simulating a five-level inverter to reduce harmonics. Simulation results show that a five-level inverter has lower total harmonic distortion and higher efficiency compared to a three-level inverter.
Ieee Power Electronics Ieee Project Titles, 2009 2010 Ncct Final Year Projectsncct
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Performance and Analysis of Hybrid Multilevel Inverter fed Induction Motor Drivernvsubbarao koppineni
This paper presents the Five level inverter with single DC source which is used to generate a five level output with two bridges and six switches and performance of three phase induction motor is analyzed when connected to PV array For this two identical dc sources of 50V each for two bridges in five levels using Multi level inverter and five level output is obtained by using a single DC source of 100V with six switches. A virtual DC source (charged capacitor acts as virtual DC source) is used for getting the output. The same technique is implemented for three-phase circuit i.e. by using single DC source. An asynchronous motor (three-phase) is connected as load and its performance characteristics are analyzed. And further the DC source is replaced by a renewable resource such as solar panels, fuel cell etc. and DC voltage is obtained. Performance characteristics of three-phase asynchronous motor are analyzed with PV array connected. The method can be easily extended to an m-level inverter.
H bridge multilevel inverter organized krunal gamit
This document certifies that two students, Patel Vinalkumar I. and Gamit Krunalbhai H., completed a project on an H-Bridge Multilevel Inverter under the guidance of Smt S.J. Pandav. The project report discusses the design and implementation of a new topology for a single-phase five-level cascaded H-bridge multilevel inverter using only five switches and two DC power sources. Various switching topologies are analyzed and modulation techniques are proposed to minimize total harmonic distortion and improve output voltage. Simulation results show the new topology reduces harmonics and switches compared to conventional methods.
Simulation and analysis of multilevel inverter with reduced number of switchesIAEME Publication
This document summarizes a research paper that proposes a new multilevel inverter topology with reduced number of switches compared to conventional cascaded H-bridge multilevel inverters. The proposed topology is a five-level inverter that requires only six switches compared to eight switches in a conventional design. Simulation results show the performance of the new topology is validated using MATLAB/Simulink software. The paper also describes the operating modes and switching techniques used in the new multilevel inverter design, including phase disposition, alternative phase opposition disposition, and phase opposition disposition pulse width modulation strategies.
This document discusses performance enhancement of a multilevel inverter using genetic algorithms. It presents an optimal solution for eliminating pre-specified harmonics from a stepped waveform generated by a multilevel inverter topology with equal DC sources. A genetic algorithm is proposed that reduces computational burden and allows for fast convergence in solving the non-linear equations involved. Simulation results show the genetic algorithm approach achieves significant improvement in harmonic profile compared to the conventional Newton-Raphson method.
This document provides an introduction to multilevel inverters. It begins by defining power electronics as the field dealing with conversion and control of electric power across a wide range of power scales. It then discusses different types of power converters including rectifiers, cycloconverters, choppers, and inverters. The document focuses on inverters, explaining that they convert DC to AC with adjustable frequency, phase and amplitude. It provides examples of two-level and multilevel inverters, describing their components and operation. The benefits of multilevel inverters for medium voltage applications are outlined. Finally, it discusses common multilevel inverter topologies including diode-clamped, flying capacitor, and cascaded H-bridge configurations.
In this paper the multicarrier pulse width modulation (MCPWM) with multi value DC voltage source multilevel inverter is presented. These MLI’s are suitable in high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum. Seven level inverter is simulated using MATLAB/Simulink. The use of Photovoltaic Cell as a DC source for the multilevel Inverter is proposed here.
BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel...MOHAMMED SAQIB
This document discusses asymmetrical multilevel inverters for producing higher output voltage levels. It introduces multilevel inverters and their advantages over traditional two-level inverters. The cascaded H-bridge topology requires fewer components and is suitable for high power applications. Asymmetric cascaded H-bridge topologies can produce more voltage levels using different DC source voltages. The document proposes a new asymmetric bidirectional converter topology that uses contradictory ratios of DC voltages to generate a higher number of output voltage levels using fewer switches. Simulation results will validate that this topology can achieve a seven-level output from two H-bridges with reduced total harmonic distortion.
IRJET- Mitigation of Harmonics in Active Neutral Point Clamped Multilevel Inv...IRJET Journal
This document presents a simulation of a 7-level active neutral point clamped (ANPC) inverter. It begins with an introduction to multilevel inverters and discusses issues with conventional 5-level NPC and flying capacitor topologies. It then presents the objectives to develop a Simulink model of a 7-level ANPC inverter using MATLAB. The model is described including subsystems for the source, pulse generation, and switches. Simulation results showing the output voltage and current waveforms are presented, with THD values below 13% for voltage and 6% for current.
Implementation of Cascaded H-bridge MULTI-LEVEL INVERTEREditor IJMTER
The classical two level inverter produce output with levels either Vdc or -Vdc. The output
voltage waveform of ideal inverter should be sinusoidal but the waveform of conventional inverters
is non-sinusoidal and contains certain harmonics. Large capacitor is normally connected across the
DC voltage source and such a capacitor is costly and demands space. In order to overcome these
drawbacks Multi level inverters are introduced. The great advantage of this kind of inverter is the
minimum harmonic distortion obtained. Power electronics is the applications of power
semiconductor devices for the control and conversion of electric power such that these devices
operate as switches. An inverter is an electrical device that converts DC voltage to AC voltage; the
resulting AC can be at any required frequency. Multi-level inverters are nothing but the modification
of basic bridge inverters [1]. The multilevel inverter collectively converts the several levels of dc
voltage to a desired ac voltage. The unique structure of multilevel inverters allows them to reach
nearer to sinusoidal i.e., with low harmonics. In this project the work is done on five & nine level
multilevel inverter but the multilevel can be done up to any level and how many levels we increase
that much precise sinusoidal supply we can get i.e., we can reduce that many harmonics from the
supply. Simulation work is done using the MATLAB software
Cascaded h bridge multilevel inverter for induction motor driveseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document presents research on asymmetrical cascaded H-bridge multilevel inverters. It summarizes the structure and operation of 5-level, 7-level symmetrical, and 7-level and 9-level asymmetrical configurations. Simulation results show that asymmetrical configurations reduce harmonics without increasing components compared to symmetrical configurations. The conclusion is that asymmetrical multilevel inverters can produce more output levels without adding components by using different progression factors.
This document presents a new multi-level inverter topology for solar energy applications. It uses a H-bridge structure with four switches connected to the DC link. It proposes a new PWM method that requires only one carrier signal. The switching sequence balances the capacitor voltages. The proposed topology requires a minimum number of components to increase the number of voltage levels. It provides simulation results showing the output voltage and current waveforms for the multi-level inverter with a solar input. The system has advantages of simple structure, low power consumption, and operating at the fundamental frequency.
Design & Simulation of 3-Phase, 27-Level Inverter with Reverse Voltage TopologyIJMTST Journal
Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance
is highly superior to that of conventional Seven-level inverters due to reduced harmonic distortion, lower
electromagnetic interference, and higher dc link voltages. In this paper, a new topology with a
reversing-voltage component is proposed to improve the multilevel performance. This topology requires fewer
components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals
and gate drives. Therefore, the complexity is greatly reduced particularly for higher output voltage levels. The
Proposed 27-level inverter is modeled and simulated in Matlab 2012b using Simulink and Sim Power
Systems set tool boxes
Chopper basically uses a Thyristor for high power applications. The process of turning off a conducting Thyristor is known as commutation. Here Thyristor is turned off by a current pulse that is why it is called a Current Commutated Chopper.
This document presents a project on improving power quality using a multi converter unified power quality conditioner (MC-UPQC). The project is presented by a student under the guidance of a professor. The MC-UPQC uses voltage source converters connected back-to-back to compensate for supply voltage and load current imperfections. It can also compensate for power quality issues across multiple feeders by sharing compensation capabilities. The document outlines the objectives, existing systems, proposed MC-UPQC system, literature review, problem formation, test system design, simulation results and conclusions.
The document contains a list of 134 topics related to power electronics and drives. The topics cover various fields including renewable energy, multilevel converters, resonant converters, Z-source inverters, industrial drive control applications for traction systems and aircraft, and more. The list provides a short description for each topic and indicates the corresponding research field.
Harmonic Minimization In Multilevel Inverters By Using PSOIDES Editor
Harmonic Elimination in a multilevel inverters is
an optimization problem which is solved by applying particle
swarm optimization (PSO) technique. The derived equation
for the computation of total harmonic distortion (THD) of the
output voltage of the multilevel inverter is used as the objective
function in PSO algorithm. The objective function used is to
reduce the THD of the multilevel inverter and obtain the
corresponding switching angles with the elimination of
possible lower order harmonics. In this paper a pseudo code
based algorithm is proposed to deal with inequality constraints
which will helps in accelerating the optimization process. The
proposed method is applied for seven level cascade inverter to
eliminate the 5th and 7th order harmonics to reduce the total
harmonic distortion .This proposed PSO algorithm is effective
in reducing the total harmonic distortion corresponding the
range of modulation index. The simulation results shows that
the proposed PSO method is indeed capable of obtaining
higher quality of solutions to eliminate 5th and 7th order
harmonics and to reduce the total harmonic distortion of 7-
level cascade inverter
Simulation and study of multilevel inverter (report)Arpit Kurel
The document discusses the simulation and study of a multilevel inverter. It begins with an abstract that outlines that multilevel inverters are used to convert DC power to AC power at required voltage and frequency levels for applications like motor drives and grid connections. It then discusses different multilevel inverter topologies like diode clamped, flying capacitor, and cascaded H-bridge. For this project, a three phase five level inverter is simulated using sinusoidal PWM technique in MATLAB/Simulink. The topology used is a cascaded H-bridge inverter with separate DC sources. The multilevel inverter reduces harmonic contents in the output waveform compared to a three level inverter.
A solar power generation system with a seven level invertershashank chelpuri
This document proposes a new solar power generation system composed of a DC/DC boost converter and a novel seven-level inverter. The seven-level inverter uses only six switches, simplifying the circuit. It operates in different modes to produce varying output voltages. Simulation results show the system works as intended. Advantages of solar include being renewable, producing electricity and heat with little maintenance, while disadvantages are lack of power at night and during cloud cover.
Hybrid topology of asymmetric cascaded multilevel inverter with renewable ene...Asoka Technologies
This paper presents a binary topology of Multimodule level inverters produce a staircase output voltage from renewable DC voltage sources. The MLI (Multi Level Inverter) Requires many number of semiconductor switches is main drawback of multilevel inverters. The MLI can be classified as two method, one is symmetric and another asymmetric converters. In symmetrical multilevel inverter can apply same voltage level to all cascaded circuit, in asymmetric multilevel inverters can be vary input source voltage at each cascaded H-bridge by using binary algorithm. In this paper, a discrete binary topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converter can produce sixty three levels of voltage from five discrete DC source. The Total Harmonic Distortions (THD) is minimized by discrete binary topology. The working operation and performance of the proposed multilevel inverters studies has been verified by simulation of using SIMULINK / MA TLAB results.
SIMULATION AND STUDY OF MULTILEVEL INVERTER (ppt)Arpit Kurel
This document discusses the simulation and study of a multilevel inverter. It aims to simulate a three-phase five-level inverter using MATLAB/Simulink. Multilevel inverters are attractive for medium-voltage high-power applications as they can produce outputs with low distortion at medium voltages. The document reviews literature on multilevel inverters and various topologies. It then discusses objectives of simulating a five-level inverter to reduce harmonics. Simulation results show that a five-level inverter has lower total harmonic distortion and higher efficiency compared to a three-level inverter.
Ieee Power Electronics Ieee Project Titles, 2009 2010 Ncct Final Year Projectsncct
Final Year Projects, IEEE Projects, Final Year Projects in Chennai, Final Year IEEE Projects, final year projects, college projects, student projects, java projects, asp.net projects, software projects, software ieee projects, ieee 2009 projects, 2009 ieee projects, embedded projects, final year software projects, final year embedded projects, ieee embedded projects, matlab projects, microcontroller projects, vlsi projects, dsp projects, free projects, project review, project report, project presentation, free source code, free project report, Final Year Projects, IEEE Projects, Final Year Projects in Chennai, Final Year IEEE Projects, final year projects, college projects, student projects, java projects, asp.net projects, software projects, software ieee projects, ieee 2009 projects, 2009 ieee projects, embedded projects, final year software projects, final year embedded projects, ieee embedded projects, matlab projects
Performance and Analysis of Hybrid Multilevel Inverter fed Induction Motor Drivernvsubbarao koppineni
This paper presents the Five level inverter with single DC source which is used to generate a five level output with two bridges and six switches and performance of three phase induction motor is analyzed when connected to PV array For this two identical dc sources of 50V each for two bridges in five levels using Multi level inverter and five level output is obtained by using a single DC source of 100V with six switches. A virtual DC source (charged capacitor acts as virtual DC source) is used for getting the output. The same technique is implemented for three-phase circuit i.e. by using single DC source. An asynchronous motor (three-phase) is connected as load and its performance characteristics are analyzed. And further the DC source is replaced by a renewable resource such as solar panels, fuel cell etc. and DC voltage is obtained. Performance characteristics of three-phase asynchronous motor are analyzed with PV array connected. The method can be easily extended to an m-level inverter.
H bridge multilevel inverter organized krunal gamit
This document certifies that two students, Patel Vinalkumar I. and Gamit Krunalbhai H., completed a project on an H-Bridge Multilevel Inverter under the guidance of Smt S.J. Pandav. The project report discusses the design and implementation of a new topology for a single-phase five-level cascaded H-bridge multilevel inverter using only five switches and two DC power sources. Various switching topologies are analyzed and modulation techniques are proposed to minimize total harmonic distortion and improve output voltage. Simulation results show the new topology reduces harmonics and switches compared to conventional methods.
Simulation and analysis of multilevel inverter with reduced number of switchesIAEME Publication
This document summarizes a research paper that proposes a new multilevel inverter topology with reduced number of switches compared to conventional cascaded H-bridge multilevel inverters. The proposed topology is a five-level inverter that requires only six switches compared to eight switches in a conventional design. Simulation results show the performance of the new topology is validated using MATLAB/Simulink software. The paper also describes the operating modes and switching techniques used in the new multilevel inverter design, including phase disposition, alternative phase opposition disposition, and phase opposition disposition pulse width modulation strategies.
This document discusses performance enhancement of a multilevel inverter using genetic algorithms. It presents an optimal solution for eliminating pre-specified harmonics from a stepped waveform generated by a multilevel inverter topology with equal DC sources. A genetic algorithm is proposed that reduces computational burden and allows for fast convergence in solving the non-linear equations involved. Simulation results show the genetic algorithm approach achieves significant improvement in harmonic profile compared to the conventional Newton-Raphson method.
This document provides an introduction to multilevel inverters. It begins by defining power electronics as the field dealing with conversion and control of electric power across a wide range of power scales. It then discusses different types of power converters including rectifiers, cycloconverters, choppers, and inverters. The document focuses on inverters, explaining that they convert DC to AC with adjustable frequency, phase and amplitude. It provides examples of two-level and multilevel inverters, describing their components and operation. The benefits of multilevel inverters for medium voltage applications are outlined. Finally, it discusses common multilevel inverter topologies including diode-clamped, flying capacitor, and cascaded H-bridge configurations.
In this paper the multicarrier pulse width modulation (MCPWM) with multi value DC voltage source multilevel inverter is presented. These MLI’s are suitable in high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum. Seven level inverter is simulated using MATLAB/Simulink. The use of Photovoltaic Cell as a DC source for the multilevel Inverter is proposed here.
BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel...MOHAMMED SAQIB
This document discusses asymmetrical multilevel inverters for producing higher output voltage levels. It introduces multilevel inverters and their advantages over traditional two-level inverters. The cascaded H-bridge topology requires fewer components and is suitable for high power applications. Asymmetric cascaded H-bridge topologies can produce more voltage levels using different DC source voltages. The document proposes a new asymmetric bidirectional converter topology that uses contradictory ratios of DC voltages to generate a higher number of output voltage levels using fewer switches. Simulation results will validate that this topology can achieve a seven-level output from two H-bridges with reduced total harmonic distortion.
IRJET- Mitigation of Harmonics in Active Neutral Point Clamped Multilevel Inv...IRJET Journal
This document presents a simulation of a 7-level active neutral point clamped (ANPC) inverter. It begins with an introduction to multilevel inverters and discusses issues with conventional 5-level NPC and flying capacitor topologies. It then presents the objectives to develop a Simulink model of a 7-level ANPC inverter using MATLAB. The model is described including subsystems for the source, pulse generation, and switches. Simulation results showing the output voltage and current waveforms are presented, with THD values below 13% for voltage and 6% for current.
Implementation of Cascaded H-bridge MULTI-LEVEL INVERTEREditor IJMTER
The classical two level inverter produce output with levels either Vdc or -Vdc. The output
voltage waveform of ideal inverter should be sinusoidal but the waveform of conventional inverters
is non-sinusoidal and contains certain harmonics. Large capacitor is normally connected across the
DC voltage source and such a capacitor is costly and demands space. In order to overcome these
drawbacks Multi level inverters are introduced. The great advantage of this kind of inverter is the
minimum harmonic distortion obtained. Power electronics is the applications of power
semiconductor devices for the control and conversion of electric power such that these devices
operate as switches. An inverter is an electrical device that converts DC voltage to AC voltage; the
resulting AC can be at any required frequency. Multi-level inverters are nothing but the modification
of basic bridge inverters [1]. The multilevel inverter collectively converts the several levels of dc
voltage to a desired ac voltage. The unique structure of multilevel inverters allows them to reach
nearer to sinusoidal i.e., with low harmonics. In this project the work is done on five & nine level
multilevel inverter but the multilevel can be done up to any level and how many levels we increase
that much precise sinusoidal supply we can get i.e., we can reduce that many harmonics from the
supply. Simulation work is done using the MATLAB software
Cascaded h bridge multilevel inverter for induction motor driveseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document presents research on asymmetrical cascaded H-bridge multilevel inverters. It summarizes the structure and operation of 5-level, 7-level symmetrical, and 7-level and 9-level asymmetrical configurations. Simulation results show that asymmetrical configurations reduce harmonics without increasing components compared to symmetrical configurations. The conclusion is that asymmetrical multilevel inverters can produce more output levels without adding components by using different progression factors.
This document presents a new multi-level inverter topology for solar energy applications. It uses a H-bridge structure with four switches connected to the DC link. It proposes a new PWM method that requires only one carrier signal. The switching sequence balances the capacitor voltages. The proposed topology requires a minimum number of components to increase the number of voltage levels. It provides simulation results showing the output voltage and current waveforms for the multi-level inverter with a solar input. The system has advantages of simple structure, low power consumption, and operating at the fundamental frequency.
Design & Simulation of 3-Phase, 27-Level Inverter with Reverse Voltage TopologyIJMTST Journal
Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance
is highly superior to that of conventional Seven-level inverters due to reduced harmonic distortion, lower
electromagnetic interference, and higher dc link voltages. In this paper, a new topology with a
reversing-voltage component is proposed to improve the multilevel performance. This topology requires fewer
components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals
and gate drives. Therefore, the complexity is greatly reduced particularly for higher output voltage levels. The
Proposed 27-level inverter is modeled and simulated in Matlab 2012b using Simulink and Sim Power
Systems set tool boxes
Chopper basically uses a Thyristor for high power applications. The process of turning off a conducting Thyristor is known as commutation. Here Thyristor is turned off by a current pulse that is why it is called a Current Commutated Chopper.
This document presents a project on improving power quality using a multi converter unified power quality conditioner (MC-UPQC). The project is presented by a student under the guidance of a professor. The MC-UPQC uses voltage source converters connected back-to-back to compensate for supply voltage and load current imperfections. It can also compensate for power quality issues across multiple feeders by sharing compensation capabilities. The document outlines the objectives, existing systems, proposed MC-UPQC system, literature review, problem formation, test system design, simulation results and conclusions.
The document discusses power quality issues caused by nonlinear loads and various power quality conditioners used to address these issues. It introduces the unified power quality conditioner (UPQC), which integrates series and shunt active power filters to compensate for both voltage and current-related power quality problems. The UPQC can mitigate issues like harmonics, voltage sags and swells, reactive power, power factor, and load unbalance. It operates by injecting compensating currents from the shunt filter and generating compensating voltages from the series filter to regulate the supply voltage and current waveforms seen by the load. The UPQC provides a comprehensive solution for improving power quality in distribution systems.
This document summarizes a research paper that proposes a method to enhance security in a video copy detection system using content-based fingerprinting. The paper discusses how existing video fingerprinting systems are not robust against content-changing attacks like changing the background of a video. To address this, the paper proposes using an interest point matching algorithm to extract fingerprints. The interest point matching algorithm detects interest points in video frames using the Harris corner detection method. It then constructs correspondences between interest points to form fingerprints. The fingerprints extracted with this method are claimed to be more robust against content-changing attacks compared to existing fingerprinting methods. The proposed algorithm is tested on videos with distortions and is found to have high detection rates and low false positive rates.
This document describes enhancements made to the energy modeling framework in the OMNET++ wireless sensor network simulator. OMNET++ is a modular discrete event simulator written in C++ that allows models to be built from reusable components. The document discusses several frameworks within OMNET++ for modeling energy consumption, including MIXIM, INET, INETMANET, PAWIS, and CASTALIA. It provides details on how energy parameters can be configured in simulation profiles, how energy levels are updated during transmissions and other events, and how output is recorded to analyze energy performance.
Dash7 is a wireless networking standard ratified in 2004 that uses low power for applications like RFID tags. It operates at 433MHz, which allows penetration through obstacles but makes efficient compact antennas difficult to design. Dash7 uses an asynchronous transmission method called BLAST that minimizes active transmission time to reduce power usage compared to standards like Zigbee. While lower frequencies have disadvantages like larger antenna size, designs like loop and helical antennas can achieve reasonable efficiency at 433MHz for applications requiring long battery life and range.
Fatigue Analysis of Acetylene converter reactorIJMER
The structural integrity of mechanical components during several transients should be
assured in the design stage. This requires a fatigue analysis including thermal and structural analysis. As
an example, this study performs a fatigue analysis of the acetylene converter reactor during arbitrary
transients. Using heat transfer coefficients determined based on the operating environments, a transient
thermal analysis is performed and the results are applied to a finite element model along with the
pressure to calculate the stresses. The total stress intensity range and cumulative fatigue usage factor are
investigated to determine the adequacy of the design.
Theoretical and graphical analysis of abrasivewater jetturningIJMER
This document presents a theoretical and graphical analysis of abrasive water jet turning. It begins with an abstract that describes using finite element analysis to simulate the impact of abrasive particles on stainless steel in abrasive water jet machining. The influences of impact angle and particle velocity were observed. The results of the FEA simulation agreed well with experimental validation. The objective of the present work is to develop a mathematical model considering the variation in jet impact angle and kerf profile to predict the final diameter achieved in abrasive water jet turning of ductile and brittle materials. Various distributions are evaluated to represent the kerf shape, with a sine function found to better represent the observed kerf geometry than exponential and cosine functions.
An Amalgamation-Based System for Micro aneurysm Detection and Diabetic Retino...IJMER
We propose an ensemble-based framework to improve microaneurysm detection. Unlike
the well-known approach of considering the output of multiple classifiers, we propose a combination of
internal components of microaneurysm detectors, namely preprocessing methods and candidate
extractors. We have evaluated our approach for microaneurysm detection in an online competition,
where this algorithm is currently ranked as first, and also on two other databases.
Numerical Analysis of Fin Side Turbulent Flow for Round and Flat Tube Heat E...IJMER
Numerical three dimensional simulation of turbulent flow in round and flat tube fin heat exchangers having two rows of staggered arrangement has been carried out to investigate fluid flow and heat transfer characteristics using ANSYS Fluent 14® software. HYPERMESH10® Software has been
used for the creation of models as well for meshing. The cases have been simulated for different fin side Reynolds number in turbulent regime to observe the effect of various parameters like fin pitch, tube pitch and fin temperature on Colburn j factor and Friction factor f for both round and flat tubes. Fin side flow has been simulated using various steady flow models in the software for same velocity range. As simulation using k-ε model resulted in close agreement with that of experimental in turbulent regime, it is considered for further analysis. The performance of round tubes is compared with that of flat tubes with same flow area and geometrical parameters. For both round and flat tube domains with all the geometrical configurations simulated in this work Colburn j factor varied inversely with the inlet air velocity. The heat transfer is more with the higher fin spacing for both round and flat tubes following the above said trend. On the other hand, the pressure drop across the tubes is more with the lesser fin spacing
in contrast to the heat transfer. Due to lesser turbulent intensity in flat tubes, they exhibit slightly lesser
Colburn j factor and considerably lesser pressure drop compared to round tubes. Although flat tubes
exhibit slightly lesser Colburn j factor, due to larger exposed tube area increase in the air temperature in
the fin side is comparable with that of round tubes. Higher fin temperatures result with lesser Colburn j factor and higher pressure drop across the tubes although the fin temperature affects the pressure drop to lesser extent.
Mechanical Characterization of Biodegradable Linen Fiber CompositesIJMER
This document discusses the mechanical characterization of biodegradable linen fiber composites. It begins by introducing linen fiber as a natural fiber that is made from flax plants. The document then discusses the properties of linen fiber and describes how linen fiber composites were prepared by layering linen fibers with an epoxy resin matrix. Four composite samples with different numbers of linen fiber layers were made and tested for their mechanical properties under tensile testing. The results of the tensile tests for the first two samples, which contained 4 and 3 linen fiber layers respectively, are presented. Both samples exhibited relatively high yield strengths and stresses.
The document discusses some key patterns in the minds of creative geniuses. It identifies several factors: wasting no time on unproductive activities but instead engaging in self-exploration and learning; developing confidence through challenges; getting children to think through puzzles, games, and problem-solving; ensuring proper diet, nutrition, exercise to get oxygen to the brain; and balancing different learning styles such as visual, auditory, and kinesthetic. The document advocates an active approach to learning that challenges children in a balanced way.
El documento presenta el nuevo sistema constructivo USG TABLAROCA® ANTI MOHO, un tablero de yeso tratado con inhibidores que combaten los hongos no solo en la superficie sino también en el núcleo. Incluye dos sistemas: USG TABLAROCA® ANTI MOHO para humedad y hongos, y USG TABLAROCA® ANTI MOHO FIRECODE® para humedad, hongos y fuego. Describe isométricos para muros y plafones corridos, incluyendo especificaciones como bastidores metá
Regression analysis of shot peening process for performance characteristics o...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Experimental Investigation on Effect of Particle Sizes of Molybdenum Disulphi...IJMER
In the present work, experimental investigation has been carried out to identify the
effectiveness of employing three different particle sizes of MoS2 (Nano-particles: 40 nm size, Technical
superfine grade: 1.75 μm size and Technical grade: 53 μm size) in varying quantities (0.5, 1.0 and 1.5% by
weight) on the wear of the sliding surfaces. The experiments were conducted on a conformal block and
disk test setup. The running-in distance required to achieve steady state wear was determined
experimentally. The wear of the block is measured as its weight loss after the test. The results of the
experiments are reported
The document presents experimental and finite element analysis methods to analyze the limit load of a pressure vessel with an oblique nozzle. Distortion measurement tests were conducted on a physical model pressure vessel with a 45° nozzle by measuring changes in diameter at various locations under increasing internal pressure. The experimental data was used to calculate the limit load using the twice elastic slope method and tangent intersection method, and was compared to results from finite element analysis of an equivalent model. Both methods showed good agreement between experimental and finite element results, validating the accuracy of finite element analysis for predicting failure locations in pressure vessels with lateral nozzle connections.
On pairs of Special Polygonal numbers with Unit differenceIJMER
This document presents formulas to determine the ranks of different polygonal numbers (e.g. triangular, hexagonal, etc.) where the difference between any two numbers is unity. Explicit formulas with recurrence relations are given for the ranks of centered hexagonal-triangular, centered heptagonal-triangular, and other pairs of polygonal numbers with a unit difference. The ranks are expressed using generalized solutions to Pell-type equations.
Study of Performance of Different Blends of Biodiesel Prepared From Waste Co...IJMER
1. The document discusses the production of biodiesel from waste cottonseed oil through transesterification and its use as a fuel in compression ignition engines. Different blends of biodiesel (B10, B20, B30) were tested in a diesel engine and their performance was compared to petrodiesel.
2. Biodiesel production parameters like reaction temperature, catalyst percentage, and alcohol percentage were optimized. Fuel properties of the biodiesel like density, viscosity, and flash point were determined and found to be close to diesel standards.
3. Engine tests showed that while biodiesel blends had slightly lower performance than petrodiesel, B10 and B20 bl
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of Multilevel Inverter using Bipolar and Unipolar Switching Schemes ...ijsrd.com
Cascaded H-bridge Multilevel Inverter (MLI) is most efficient topology for medium and high voltage DC-AC conversion, having less output harmonics and less commutation losses. Disadvantages are their complexity, more number of power devices, passive components and a complex control circuitry. Here a Cascaded Hybrid Multilevel Inverter is used to produce a three phase 9-level output voltages. Now a day inverter is also know as a DC-AC converter, is one of the most popular part of electrical device. This proposed inverter widely used in industries application such as speed control of induction motor. This thesis focus on three phase 9-level bipolar and unipolar switching inverter with characteristics like output voltage boosting ability and also we discus about the bipolar and unipolar switching scheme along with capacitor voltage control. The modified topology uses Cascaded H-bridge (CHB) with bidirectional and unidirectional switches producing boost up output voltage. Here a hybrid Pulse Width Modulation (PWM) technique is applied to control the power devices. This modulation technique uses a sine wave and a repeating wave, these waves are combined and a complete reference wave is generated. There is comparative study between CHB and modified topology between number of power devices used and Total Harmonic Distortions (THD). THD of modified topology is reduced and analyzed by FFT window. The results are observed by MATLAB/SIMULINK software.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Analysis of 7-Level Cascaded & MLDCLI with Sinusoidal PWM & Modified Referenc...IJMTST Journal
This document compares the performance of a 7-level cascaded multilevel inverter and a 7-level multilevel DC link inverter (MLDCLI) using sinusoidal PWM and modified reference PWM control techniques. Simulation results show that the 7-level MLDCLI with modified reference PWM produces the highest fundamental output voltage with the lowest total harmonic distortion. The MLDCLI topology requires fewer switches and components than other multilevel inverter topologies as the number of voltage levels increases, making it advantageous for higher level designs.
This document analyzes a transistor clamped H-bridge split phase PWM inverter. It presents the circuit diagram of the proposed inverter which uses coupled inductors to prevent short circuits and reduce reverse recovery losses. A double reference single carrier modulation technique is used to generate PWM signals from two reference signals and a triangular carrier, producing a five-level output voltage. Simulation results in MATLAB Simulink show the five-level output voltage waveform and total harmonic distortion of 8.43%, demonstrating reduced harmonics compared to conventional inverters. The proposed inverter topology and modulation control method aim to improve efficiency, reliability and output waveform quality.
A Comparison Analysis of Unipolar and Bipolar Switching modulated Cascade H-B...IJERA Editor
This paper discusses controlling of cascaded H-bridge multi inverter with sinusoidal modulation based PWM methods. Multi-level inverters are used to reduce the THD in the output wave form without reduction in power output of inverter. Increase in voltage level in the output voltage of an inverter increases numbers of components to be used in inverter configuration. This in turn increases the switching loss. But results in good harmonic distortion and provide better quality fundamental wave. Carrier based PWM schemes are used for control of switching operation of multi-level inverters. Many kinds of PWM schemes are available to control inverter switches. In this paper uniploar carrier based PWM, bipolar carrier based PWM schemes are considered for generation of carrier signals. The carrier signals thus generated are compared with sinusoidal and third harmonic based sinusoidal modulating signals for production of switching Pulses. Switching schemes are designed for a 3 Phase 3, 5, 7, 9 and 11 Level inverters. The proposed switching schemes are applied to Cascaded H-Bridge Multi Level inverters. The circuit is simulated with MATLAB Simulink environment for verification of total harmonic distortion.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium voltage grid, to connect only one power semiconductor switch directly is a not practically successful concept. To overcome this multilevel power converter structure has been introduced and studied as an alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic, wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications. In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter. This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/SIMULINK. Experimental results are presented to validate the effectiveness of the operation of the diode clamped multilevel inverter using field programmable gate array.
This document provides an overview of different multi-level inverter techniques to reduce harmonic distortion in inverters. It describes three main types of multi-level inverters: diode-clamped, flying capacitor, and cascaded H-bridge. Diode-clamped inverters use clamping diodes to limit voltage stress on devices, but require many clamping diodes at high levels. Flying capacitor inverters balance voltages using capacitors but require balancing control. Cascaded H-bridge inverters connect H-bridge cells in series, requiring fewer components than other types. The document compares the components required for each type and concludes cascaded H-bridge has the least components and potential for utility applications.
A Comparative Study between Different Types of Multilevel InverterIRJET Journal
This document compares different topologies of cascaded H-bridge multilevel inverters. It summarizes a study that analyzes four types of cascaded H-bridge multilevel inverters: a single-phase 3rd level, 5th level, and 7th level inverter as well as their output waveforms and total harmonic distortion. The document outlines the operating modes of each inverter topology through switching combinations and presents simulation results for the output voltage waveform and THD for each.
This document describes the modeling and design of a five-level cascaded H-bridge multilevel inverter with a DC/DC boost converter. It begins with an introduction to multilevel inverters and their advantages over traditional two-level inverters. It then discusses the specific topology of a five-level cascaded H-bridge inverter and describes the operation and components of a DC/DC boost converter. Simulation results in MATLAB/Simulink are presented, showing the output voltage waveform both with and without filtering. The total harmonic distortion of the output is analyzed, showing less than 5% distortion. The conclusion is that this five-level inverter topology with boost converter provides high efficiency of 95% and improved power
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
This document summarizes three topologies of cascaded H-bridge multilevel inverters: the existing topology, proposed topology I, and proposed topology II. The existing topology uses two DC sources per phase. Proposed topology I uses one DC source for all three phases and transformers. Proposed topology II also uses one DC source for all phases and reduces the number of switches compared to the other topologies. MATLAB simulations were performed and results were compared in terms of voltage THD and equipment requirements. The existing topology had the best performance based on FFT analysis, but proposed topology II is best in terms of cost and switching losses when considering single DC source topologies.
IRJET- Study of Unsymmetrical Cascade H-Bridge Multilevel Inverter Design for...IRJET Journal
This document presents a study on an unsymmetrical cascade multilevel inverter design for an induction motor. It discusses using a 7-level and 9-level unsymmetrical cascade multilevel inverter with level shifted pulse width modulation to drive a single phase induction motor. Simulation results in MATLAB/Simulink show that the 9-level inverter produces lower total harmonic distortion in the output voltage compared to the 7-level inverter, with smaller variation in the motor's current, speed, and torque. The study concludes the 9-level inverter provides better performance for driving the induction motor load.
Analysis and hardware implementation of five level cascaded H Bridge inverterIJERA Editor
The cascaded multilevel inverter (CMLI) has gained much attention in recent years due to its advantages in high
voltage and high power with low harmonics applications. A standard cascaded multilevel inverter requires n DC
sources for 2n+1levels at the output, where n is the number of inverter stages. This paper presents a topology to
control cascaded multilevel inverter that is implemented with multiple DC sources to get 2"+1_ 1 levels. Without
using Pulse Width Modulation (PWM) technique, the firing circuit can be implemented using Microcontroller
which greatly reduces the Total Harmonic Distortion (THD) and switching losses. To develop the model of a
cascaded hybrid multilevel inverter, a simulation is done based on MATLAB/SIMULINK software and
hardware implementation was also done. Their integration makes the design and analysis of a hybrid multilevel
inverter more complete and detailed.
Asymmetrical Nine-level Inverter Topology with Reduce Power Semicondutor DevicesTELKOMNIKA JOURNAL
In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is
capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging
available switches and dc sources in a fashion such that the maximum combination of addition and
subtraction of the input dc sources can be obtained. To verify the viability of the proposed topology, the
circuit model is developed and simulated in Matlab-Simulink software. Experimental testing results of the
proposed nine-level inverter topology, developed in the laboratory, are presented. A low frequency
switching strategy is employed in this work. The results show that the proposed topology is capable to
produce a nine-level output voltage, capable in handling inductive load and yields acceptable harmonic
distortion content.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Similar to Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Various PWM Strategies (20)
A Study on Translucent Concrete Product and Its Properties by Using Optical F...IJMER
- Translucent concrete is a concrete based material with light-transferring properties,
obtained due to embedded light optical elements like Optical fibers used in concrete. Light is conducted
through the concrete from one end to the other. This results into a certain light pattern on the other
surface, depending on the fiber structure. Optical fibers transmit light so effectively that there is
virtually no loss of light conducted through the fibers. This paper deals with the modeling of such
translucent or transparent concrete blocks and panel and their usage and also the advantages it brings
in the field. The main purpose is to use sunlight as a light source to reduce the power consumption of
illumination and to use the optical fiber to sense the stress of structures and also use this concrete as an
architectural purpose of the building
Developing Cost Effective Automation for Cotton Seed DelintingIJMER
A low cost automation system for removal of lint from cottonseed is to be designed and
developed. The setup consists of stainless steel drum with stirrer in which cottonseeds having lint is mixed
with concentrated sulphuric acid. So lint will get burn. This lint free cottonseed treated with lime water to
neutralize acidic nature. After water washing this cottonseeds are used for agriculter purpose
Study & Testing Of Bio-Composite Material Based On Munja FibreIJMER
The incorporation of natural fibres such as munja fiber composites has gained
increasing applications both in many areas of Engineering and Technology. The aim of this study is to
evaluate mechanical properties such as flexural and tensile properties of reinforced epoxy composites.
This is mainly due to their applicable benefits as they are light weight and offer low cost compared to
synthetic fibre composites. Munja fibres recently have been a substitute material in many weight-critical
applications in areas such as aerospace, automotive and other high demanding industrial sectors. In
this study, natural munja fibre composites and munja/fibreglass hybrid composites were fabricated by a
combination of hand lay-up and cold-press methods. A new variety in munja fibre is the present work
the main aim of the work is to extract the neat fibre and is characterized for its flexural characteristics.
The composites are fabricated by reinforcing untreated and treated fibre and are tested for their
mechanical, properties strictly as per ASTM procedures.
Hybrid Engine (Stirling Engine + IC Engine + Electric Motor)IJMER
Hybrid engine is a combination of Stirling engine, IC engine and Electric motor. All these 3 are
connected together to a single shaft. The power source of the Stirling engine will be a Solar Panel. The aim of
this is to run the automobile using a Hybrid engine
Fabrication & Characterization of Bio Composite Materials Based On Sunnhemp F...IJMER
This document summarizes research on the fabrication and characterization of bio-composite materials using sunnhemp fibre. The document discusses how sunnhemp fibre was used to reinforce an epoxy matrix through hand lay-up methods. Various mechanical properties of the bio-composites were tested, including tensile, flexural, and impact properties. The results of the mechanical tests on the bio-composite specimens are presented. Potential applications of the sunnhemp fibre bio-composites are also suggested, such as in fall ceilings, partitions, packaging, automotive interiors, and toys.
Geochemistry and Genesis of Kammatturu Iron Ores of Devagiri Formation, Sandu...IJMER
The Greenstone belts of Karnataka are enriched in BIFs in Dharwar craton, where Iron
formations are confined to the basin shelf, clearly separated from the deeper-water iron formation that
accumulated at the basin margin and flanking the marine basin. Geochemical data procured in terms of
major, trace and REE are plotted in various diagrams to interpret the genesis of BIFs. Al2O3, Fe2O3 (T),
TiO2, CaO, and SiO2 abundances and ratios show a wide variation. Ni, Co, Zr, Sc, V, Rb, Sr, U, Th,
ΣREE, La, Ce and Eu anomalies and their binary relationships indicate that wherever the terrigenous
component has increased, the concentration of elements of felsic such as Zr and Hf has gone up. Elevated
concentrations of Ni, Co and Sc are contributed by chlorite and other components characteristic of basic
volcanic debris. The data suggest that these formations were generated by chemical and clastic
sedimentary processes on a shallow shelf. During transgression, chemical precipitation took place at the
sediment-water interface, whereas at the time of regression. Iron ore formed with sedimentary structures
and textures in Kammatturu area, in a setting where the water column was oxygenated.
Experimental Investigation on Characteristic Study of the Carbon Steel C45 in...IJMER
In this paper, the mechanical characteristics of C45 medium carbon steel are investigated
under various working conditions. The main characteristic to be studied on this paper is impact toughness
of the material with different configurations and the experiment were carried out on charpy impact testing
equipment. This study reveals the ability of the material to absorb energy up to failure for various
specimen configurations under different heat treated conditions and the corresponding results were
compared with the analysis outcome
Non linear analysis of Robot Gun Support Structure using Equivalent Dynamic A...IJMER
Robot guns are being increasingly employed in automotive manufacturing to replace
risky jobs and also to increase productivity. Using a single robot for a single operation proves to be
expensive. Hence for cost optimization, multiple guns are mounted on a single robot and multiple
operations are performed. Robot Gun structure is an efficient way in which multiple welds can be done
simultaneously. However mounting several weld guns on a single structure induces a variety of
dynamic loads, especially during movement of the robot arm as it maneuvers to reach the weld
locations. The primary idea employed in this paper, is to model those dynamic loads as equivalent G
force loads in FEA. This approach will be on the conservative side, and will be saving time and
subsequently cost efficient. The approach of the paper is towards creating a standard operating
procedure when it comes to analysis of such structures, with emphasis on deploying various technical
aspects of FEA such as Non Linear Geometry, Multipoint Constraint Contact Algorithm, Multizone
meshing .
Static Analysis of Go-Kart Chassis by Analytical and Solid Works SimulationIJMER
This paper aims to do modelling, simulation and performing the static analysis of a go
kart chassis consisting of Circular beams. Modelling, simulations and analysis are performed using 3-D
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In récent year various vehicle introduced in market but due to limitation in
carbon émission and BS Séries limitd speed availability vehicle in the market and causing of
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content and temperature on the stresses in the composite cylinder has been analyzed. The study
revealed that the stress distributions in the cylinder do not vary significantly for various combinations
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varying particle content. Functionally Graded Materials (FGMs) emerged and led to the development
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In this investigation, studied the technical aspects of the various measures along with its cost benefit
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Investigation found that major areas of energy conservation are-
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Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Various PWM Strategies
1. www.ijmer.com
International Journal of Modern Engineering Research (IJMER)
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2758-2766
ISSN: 2249-6645
Performance Evaluation of Nine Level Modified CHB
Multilevel Inverter for Various PWM Strategies
P. Satheesh Kumar1, Dr. S. P. Natarajan2, Dr. Alamelu Nachiappan 3, Dr. B. Shanthi4
*(Associate professor, Department of Electrical and Electronics Engineering, Mailam Engineering College,
Mailam, Tamilnadu-604304, India,)
**(Professor & Head, Department of Instrumentation Engineering, Annamalai University, Annamalai Nagar,
Tamilnadu-608002, India,)
*** (Professor, Department of Electrical and Electronics Engineering, Pondicherry Engineering College,
Pondicherry- 605014, India,)
**** (Professor, Centralized Instrumentation and Service Laboratory, Annamalai University, Annamalai Nagar,
Tamilnadu-608002, India,)
ABSTRACT: In this paper nine level Modified Cascaded H-Bridge Multilevel Inverter (CHB-MLI) is analyzed for the
various multi-carrier Pulse Width Modulation strategies. For the same nine level inverter output this particular topology has
reduced count of switches, on comparing with the conventional Cascaded H Bridge Multilevel Inverter. For a single phase,
nine level inverter output this topology requires one H-bridge and a multi conversion cell. Four equal voltage sources with
four controlled switches and four diodes comprise a multi conversion cell. Instead of sixteen controlled switches as in
conventional method, this topology requires only eight switches to obtain nine level output. The reduction of switches lowers
switching losses, cost and total harmonic distortions. Performance parameters have been analyzed for the nine level CHBMLI.
Keywords: Alternate phase opposition disposition, Modified Cascaded Multilevel Inverter H-bridge Inverter, Phase
disposition, Phase opposition disposition, Phase shift Pulse width Modulation, Sinusoidal Pulse Width Modulation.
I. INTRODUCTION
Multilevel inverter (MLI) has wide range of high-power applications and feeds demands in industries in recent
years. The aptness of MLI attracts the hot researchers in the direction of renewable energy sources for its numerous benefits.
As renewable energy sources such as photovoltaic, wind and fuel cells can be easily interfaced to a multilevel inverter
system of high power applications, MLI still gains further credit to its field. MLI can operate at high switching frequencies
while producing lower order harmonic components.
A multilevel inverter is a power-electronic system that generates a desired output voltage by synthesizing several
levels of dc input voltages. The main advantages of multilevel inverters are lower cost, higher performance, less
electromagnetic interference, and lower harmonic content [1].The most common multilevel inverter topologies are the diodeclamped, flying-capacitor, and cascaded H-bridge inverters with separate dc voltage sources [2]. The diode clamped
multilevel inverter topology, restricts the use of it to the high power range of operation. Moreover flying capacitor based
multilevel inverter also exhibits a disadvantage including more number of capacitors [3].
In recent years, the cascaded H-bridge inverters have wide applications. The merit includes modularity and the
ability to operate at higher voltage levels and as the number of levels increases, the quality of the output signal will be
improved. In addition inverter output voltage waveform will be closer to a sinusoidal waveform [4]. Moreover, high voltages
can be managed at the dc and ac sides of the inverter, while each unit endures only a part of the total dc voltage. Needs of
high number of semiconductor switches, involvement of separate DC source for each of H-bridge, voltage balancing issues
are the notable drawbacks of cascaded H bridge inverter.
On comparing with the usual Cascaded H-Bridge multilevel inverters, for the same nine level output, this Modified
cascaded multilevel inverter topology, the number of switches used reduced from 16 switches to 8 switches. Therefore for
this reason, this Modified cascaded multilevel inverter has some value of importance. Hence this paper focuses on applying
various multi carrier based PWM techniques to this Modified cascaded H Bridge multilevel inverter to analyze and compare
the various parameters like THD & Vrms.
II. MODIFIED CASCADED MULTILEVEL INVERTER TOPOLOGY DESCRIPTION
The general structure of the Modified cascaded multilevel inverter is shown in Figure 1. This inverter consists of an
H Bridge and multi conversion cell which consists of four separate voltage sources (Vdc1, Vdc2, Vdc3 and V dc4), four switches
and four diodes. Each source connected in cascade with other sources through a circuit consists of one active switch and one
diode that can make the output voltage source only in positive polarity with several levels. Only one H-bridge is connected
with multi conversion cell to acquire both positive and negative polarity.
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2758 | Page
2. www.ijmer.com
International Journal of Modern Engineering Research (IJMER)
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2758-2766
ISSN: 2249-6645
Figure 1: 9-Level Modified-Cascaded multilevel inverter
By turning on controlled switches S1 (S2, S3 and S4 turn off) the output voltage +1V dc (first level) is produced
across the load. Similarly turning on of switches S1, S2 (S3 & S4 turn off) +2V dc (second level) output is produced across
the load. Similarly +3Vdc levels can be achieved by turning on S1, S2, S3 switches ( S4 turn off) and +4V dc levels can be
achieved by turning on S1, S2, S3 & S4 as shown in below Table 1.
S.
No
Multi conversion Cell
H-Bridge
Voltage
levels
On switches
Off switches
On
switches
1
S1, S2, S3, S4
D1,D2,D3,D4
Q1,Q2
Q3,Q4
+4Vdc
2
S1, S2, S3, D4
S4,D1,D2,D3
Q1,Q2
Q3,Q4
+3Vdc
3
S1, S2, D3, D4
S3, S4,D1,D2
Q1,Q2
Q3,Q4
+2Vdc
4
S1, D2, D3,D4
S2, S3, S4,D1
Q1,Q2
Q3,Q4
+1Vdc
5
D1, D2, D3,D4
S1, S2, S3,S4
Q1,Q2
Q3,Q4
0
6
S1, D2, D3,D4
S2, S3, S4,D1
Q3,Q4
Q1,Q2
-1Vdc
7
S1, S2, D3,D4
S3, S4,D1,D2
Q3,Q4
Q1,Q2
-2Vdc
8
S1, S2, S3, D4
S4,D1,D2,D3
Q3,Q4
Q1,Q2
-3Vdc
9
S1, S2, S3, S4
D1,D2,D3,D4
Q3,Q4
Q1,Q2
-4Vdc
Off switches
Table: 1 Switching Patterns for 9 levels MC-MLI
From the above table, it is observed that for each voltage level, among the paralleled switches only one switch is
switched ON. The input DC voltage is converted into a stepped DC voltage, by the multi conversion cell, which is further
processed by the H Bridge and outputted as a stepped or approximately sinusoidal AC waveform. In the H Bridge, during the
positive cycle, only the switches Q1 and Q3 are switched on. And during the negative half cycle, only the switches Q2 and
Q4 are switched on.
The S number of DC sources or stages and the associated number output level can be calculated by using the
equation as follows,
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3. International Journal of Modern Engineering Research (IJMER)
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2758-2766
ISSN: 2249-6645
N level = 2S+1 …………………………………………………….. (1)
For an example, if S=3, the output wave form will have seven levels (±3Vdc, ±2Vdc, ±1Vdc and 0). Similarly voltage on
each stage can be calculated by using the equation as given,
Ai = 1 V dc (1, 2, 3,) ……………………………………………….. (2)
The main advantage of proposed modified cascaded multilevel inverter is seven levels with only use of seven
switches. For an example, if S=3, the output wave form will have seven levels (±3V dc, ±2Vdc, ±1Vdc and 0). The number
switches used in this topology is given by the equation as follows
N Switch = 2S+ 4 …………………………………………….……….. (3)
III. MULTIPLE CARRIER PULSE WIDTH MODULATION TECHNIQUES
In this PWM technique, more than one carrier wave which be either triangular or saw tooth wave form can be used.
This paper focuses on various strategies.utilising more than one triangular wave as carrier and the reference wave is
sinusoidal. Though there are many carrier wave arrangements, in this paper, the following four arrangements have been
carried out. THD and Vrms values for these four strategies for various modulation indexes are compared.
1.
2.
3.
4.
Phase disposition PWM strategy.
Phase Opposition Disposition PWM strategy.
Alternate Phase Opposition Disposition PWM strategy
Phase Shift PWM strategy.
In these Multicarrier PWM schemes, several triangular carrier waves are compared with the single Sinusoidal
reference wave. The number of carriers required to produce N level output is (m-1) where m is the number of carrier
waveforms. The single sinusoidal reference waveform has peak to peak amplitude of A m and a frequency fm. The multiple
triangular carrier waves are having same peak to peak amplitude Ac and same frequency fc. The single sinusoidal reference
signal is continuously compared with all the carrier waveforms. A pulse is generated, whenever the single sinusoidal
reference signal is greater than the carrier signal. The frequency ratio mf is as follows: fc / fm
3.1. Phase Disposition PWM strategy (PDPWM)
Figure 2: Carrier arrangement for Phase Disposition PWM strategy
The above fig. 2 shows, Phase Disposition PWM strategy (PDPWM), where (m-1) carrier signal with the same
frequency fc and same amplitude Ac are positioned such that the bands they occupy are contiguous. The reference wave form
is single sinusoidal. During the continuous comparison, if the reference wave form is more than a carrier waveform, then the
active switching device corresponding to that carrier is switched on. Otherwise, that concerned device is switched off.
The below fig: 3 shows Complete Gate signal for 9-level MC-MLI using Phase Disposition PWM strategy
Amplitude of modulation index for PDPWM is
ma = 2A m / (m-1) Ac …………………… (5)
www.ijmer.com
2760 | Page
4. www.ijmer.com
International Journal of Modern Engineering Research (IJMER)
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2758-2766
ISSN: 2249-6645
Figure 3 – Complete Gate signal for 9-level MC-MLI using Phase Disposition PWM strategy
3.2. Phase Opposition Disposition PWM strategy (PODPWM)
Figure 4: Carrier arrangement for Phase Opposition Disposition PWM strategy
POD PWM strategy is shown in fig.4, where the carrier waveforms, above the zero reference are in phase. The carrier
waveforms below are also in phase, but are 180 degrees phase shifted from those above zero. The reference wave form is
single sinusoidal. During the continuous comparison, if the reference wave form is more than a carrier waveform, then the
active switching device corresponding to that carrier is switched on. Otherwise, that concerned device is switched off. The
below fig: 5 shows Complete Gate signal for 9-level MC-MLI using Phase Opposition Disposition PWM strategy.
Amplitude of modulation index for PODPWM is
ma = 2Am / (m-1)* Ac …………………… (6)
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Figure 5: Complete Gate signal for 9-level MC-MLI using Phase Opposition Disposition PWM strategy
3.3. Alternate Phase Opposition Disposition PWM strategy (APODWM)
Figure 6: Carrier arrangement for Alternate Phase Opposition Disposition PWM strategy
The above fig. 6 shows APOD strategy where the multiple carriers having same amplitude are phase displaced from
each other by 180 degrees alternately. During the continuous comparison, if the reference wave form is more than a carrier
waveform, then the active switching device corresponding to that carrier is switched on. Otherwise, that concerned device is
switched off. The below fig: 7 shows Complete Gate signal for 9-level MC-MLI using Alternate Phase Opposition
Disposition PWM strategy.
Amplitude of modulation index for PODPWM is
ma = 2Am / (m-1)* Ac ……………………(7)
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Figure 7: Complete Gate signal for 9-level MC-MLI using Alternate Phase Opposition Disposition PWM strategy
3.4. Phase shift PWM strategy (PSPWM)
Figure 8: Carrier arrangement for Phase shift PWM strategy
The above fig. 8 shows PSPWM strategy where the multiple carriers having the same amplitude and
frequency which are shifted to one another by certain degrees decided by the No. of levels. Thus for nine level output, 8
triangular carrier waves which are phase shifted by 45 degrees is utilized .The reference waveform is single sinusoidal (i) for
odd mf the waveforms have odd symmetry resulting in even and odd harmonics and (ii) for even m f , PSPWM waves have
quarter wave symmetry resulting in odd harmonics only. Amplitude of modulation index for PSPWM is
ma = Am / (Ac /2). …………………(4)
The below fig.9 shows complete gate signal for 9-level MC-MLI using Phase shift PWM strategy
Figure: 9 – Complete Gate signal for 9-level MC-MLI using Phase shift PWM strategy
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IV. SIMULATION RESULTS
The fig. 6 shown below is the simulink model of the 9 –level Modified cascaded H Bridge Multilevel inverter using
power system block set. The following parameter values are used for simulation: V1 =100v, V2 =100v, V3 = 100v, V4= 100v
fc =2000 Hz and fm=50Hz .Gating signals for Phase shifted carrier wave arrangement and three different, level shifted
carrier wave arrangements are simulated for 9 levels MC MLI. Simulations are done for various values of ma and the
corresponding THD% are observed using FFT block and listed in Table 2 The V r ms (fundamental) of the output voltage for
various values of ma and the corresponding Voltages are listed in Table3.
Figure 8: Simulink Model of the 9 level - Modified Cascaded Multilevel Inverter-MC-MLI
Table 2: THD comparison
Table 3: Vrms comparison
Ma
PD
PWM
POD
PWM
APOD
PWM
PS PWM
13.66
1
399
397.8
397
399
16.89
16.65
0.9
358.6
356.6
356.7
358.7
17.02
17.14
0.8
318.4
316.5
316.8
318.3
Ma
PD
PWM
POD
PWM
APOD
PWM
PS PWM
1
13.63
13.48
14.04
0.9
16.74
16.72
0.8
17.1
16.85
COMPARISON OF THD
Comparison of Vrms
18
420
PD
400
16
POD
380
15
APOD
PS
14
Vrms
THD (%)
17
PD
POD
360
APOD
340
PS
320
13
1
0.9
300
0.8
1
MODULATION INDEX
0.9
0.8
Modulation Index
Figure 9 Comparison of THD
Figure 10 Comparison of Vrms
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The Simulated 9-level Output Voltage waveform of MC-MLI using PDPWM Strategy is shown in fig. 11 and Fig.
12 shows the FFT plot of 9-level MC-MLI Using PDPWM using PDPWM Strategy. The Simulated 9-level Output Voltage
waveform of MC-MLI using PODPWM Strategy is shown in fig 13 and Fig: 14 shows the FFT plot of 9-level MC-MLI
using PDPWM Using PODPWM Strategy. The Simulated 9-level Output Voltage waveform of MC-MLI using APODPWM
Strategy is shown in fig 15 and Figure: 16 shows the FFT plot of 9-level MC-MLI Using APDPWM using PODPWM
Strategy. The Simulated 9-level Output Voltage waveform of MC-MLI using PSPWM Strategy is shown in fig 17 and Fig:
18 shows the FFT plot of 9-level MC-MLI Using PDPWM using PSPWM Strategy.
Figure 11: Simulated 9-level Output Voltage waveform Figure 12: FFT plot of 9-level Output Voltage waveform
of MC-MLI Using PDPWM Strategy
MC-MLI Using PDPWM Strategy
Figure 13: Simulated 9-level Output Voltage waveform of
MC-MLI Using PODPWM Strategy
Figure 14: FFT plot of 9-level MC-MLI Using PODPWM
Strategy
Figure 15: Simulated 9-level Output Voltage
waveform of MC-MLI Using APODPWM Strategy
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Figure 16: FFT plot of 9-level MC-MLI Using
APODPWM Strategy
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2758-2766
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Figure 17: Simulated 9-level Output Voltage
waveform of MC-MLI Using PSPWM Strategy
Figure 18: FFT plot of 9-level MC-MLI Using
PSPWM Strategy
V. CONCLUSION
Single phase nine levels Modified cascaded multilevel inverter has been analyzed for various multi carrier
sinusoidal Pulse Width Modulation strategies. This topology has the credit of having only eight switches with four diodes,
instead of 18 switches in the conventional plants, which support reduction in switching losses, cost and circuit complexity.
Performance factors like %THD and VRMS have been measured, and analyzed for Phase shifted carrier wave
arrangement and three different, level shifted carrier wave arrangements both applied to the Single phase nine levels
Modified cascaded multilevel inverter. The values have been measured for various modulation indexes. It is found that the
PDPWM strategy provides appreciable %THD and acceptable VRMS. In addition, it is also observed that it has less number of
dominant harmonics than the other strategies.
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