Fast delay estimation methods, as compared to
simulation techniques, are needed for incremental
performance-driven layout synthesis. On-chip inductive and
conductive effects are becoming predominant in deep
submicron (DSM) interconnects due to increasing clock
speeds; circuit complexity and interconnect lengths.
Inductance causes noise in the signal waveforms, which can
adversely affect the performance of the circuit and signal
integrity. Elmore delay-based estimation methods, although
efficient, fails to accurately estimate the delay for RLCG
interconnect lines. This paper presents an analytical delay
model, based on first and second moments of RLCG
interconnection lines, that considers the effect of inductance
and conductance for the estimation of delay in interconnection
lines. Simulation results justify the efficacy of the proposed
delay modelling approach.
Coupling Aware Explicit Delay Metric for On- Chip RLC Interconnect for Ramp i...IDES Editor
Recent years have seen significant research in
finding closed form expressions for the delay of the RLC
interconnect which improves upon the Elmore delay
model. However, several of these formulae assume a step
excitation. But in practice, the input waveform does have
a non zero time of flight. There are few works reported so
far which do consider the ramp inputs but lacks in the
explicit nature which could work for a wide range of
possible input slews. Elmore delay has been widely used
as an analytical estimate of interconnect delays in the
performance-driven synthesis and layout of VLSI routing
topologies. However, for typical RLC interconnections
with ramp input, Elmore delay can deviate by up to 100%
or more than SPICE computed delay since it is
independent of rise time of the input ramp signal. We
develop a novel analytical delay model based on the first
and second moments of the interconnect transfer function
when the input is a ramp signal with finite rise/fall time.
Delay estimate using our first moment based analytical
model is within 4% of SPICE-computed delay, and model
based on first two moments is within 2.3% of SPICE,
across a wide range of interconnects parameter values.
Evaluation of our analytical model is several orders of
magnitude faster than simulation using SPICE. We also
discuss the possible extensions of our approach for
estimation of source-sink delays for an arbitrary
interconnects trees.
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Log...IDES Editor
The high-speed dynamic True Single Phase
Clock (TSPC) logic design style offer fully pipelined logic
circuits using only one clock signal, which makes clock
distribution simple and compact. The conversion of simple
logic gates to pipelined TSPC logic gates increases transistor
count since standard cell implementation for a logic function
uses both N-block as well as P-block to remove transparency
between pipelined stages, despite the fact that logic
functions are only implemented with N-block. In this paper
we present a technique in which a TSPC logic cell are
implemented both as cell_N and cell_P cells, where each cell
block is performing a logic function along with only one
type latching operation. Such an implementation allows a
systematic approach for converting un-pipelined circuits to
fully pipelined circuits. The alternate cell_N and cell_P
behaves as dynamic register and removes transparency
between pipelined stages. The appropriate numbers of
dynamic registers are used to equalize stage delays for all
paths and to remove transparency between pipelined stages.
The modified TSPC implementation shows almost 40% to
50% reduction in transistor counts and almost 50%
reduction in clock cycles as compared to worst-case
standard TSPC implementation. The worst-case standard
TSPC implementation assumes that no logic merging is
possible with P-block, since input to any cell appears after
different cycle delays. The modified TSPC logic circuit
implementation preserves all the advantages of standard
TSPC logic implementation and in addition offers the
reduced circuit complexity due to reduced transistor count
per logic cell. The proposed logic design style reduces layout
area and average power consumption as compared to the
standard TSPC pipelined circuit implementation.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
Coupling Aware Explicit Delay Metric for On- Chip RLC Interconnect for Ramp i...IDES Editor
Recent years have seen significant research in
finding closed form expressions for the delay of the RLC
interconnect which improves upon the Elmore delay
model. However, several of these formulae assume a step
excitation. But in practice, the input waveform does have
a non zero time of flight. There are few works reported so
far which do consider the ramp inputs but lacks in the
explicit nature which could work for a wide range of
possible input slews. Elmore delay has been widely used
as an analytical estimate of interconnect delays in the
performance-driven synthesis and layout of VLSI routing
topologies. However, for typical RLC interconnections
with ramp input, Elmore delay can deviate by up to 100%
or more than SPICE computed delay since it is
independent of rise time of the input ramp signal. We
develop a novel analytical delay model based on the first
and second moments of the interconnect transfer function
when the input is a ramp signal with finite rise/fall time.
Delay estimate using our first moment based analytical
model is within 4% of SPICE-computed delay, and model
based on first two moments is within 2.3% of SPICE,
across a wide range of interconnects parameter values.
Evaluation of our analytical model is several orders of
magnitude faster than simulation using SPICE. We also
discuss the possible extensions of our approach for
estimation of source-sink delays for an arbitrary
interconnects trees.
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Log...IDES Editor
The high-speed dynamic True Single Phase
Clock (TSPC) logic design style offer fully pipelined logic
circuits using only one clock signal, which makes clock
distribution simple and compact. The conversion of simple
logic gates to pipelined TSPC logic gates increases transistor
count since standard cell implementation for a logic function
uses both N-block as well as P-block to remove transparency
between pipelined stages, despite the fact that logic
functions are only implemented with N-block. In this paper
we present a technique in which a TSPC logic cell are
implemented both as cell_N and cell_P cells, where each cell
block is performing a logic function along with only one
type latching operation. Such an implementation allows a
systematic approach for converting un-pipelined circuits to
fully pipelined circuits. The alternate cell_N and cell_P
behaves as dynamic register and removes transparency
between pipelined stages. The appropriate numbers of
dynamic registers are used to equalize stage delays for all
paths and to remove transparency between pipelined stages.
The modified TSPC implementation shows almost 40% to
50% reduction in transistor counts and almost 50%
reduction in clock cycles as compared to worst-case
standard TSPC implementation. The worst-case standard
TSPC implementation assumes that no logic merging is
possible with P-block, since input to any cell appears after
different cycle delays. The modified TSPC logic circuit
implementation preserves all the advantages of standard
TSPC logic implementation and in addition offers the
reduced circuit complexity due to reduced transistor count
per logic cell. The proposed logic design style reduces layout
area and average power consumption as compared to the
standard TSPC pipelined circuit implementation.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Sparse Random Network Coding for Reliable Multicast ServicesAndrea Tassi
Point-to-Multipoint communications are expected to play a pivotal role in next-generation networks. This talk refers to a cellular system transmitting layered multicast services to a Multicast Group (MG) of users. Reliability of communications is ensured via different Random Linear Network Coding (RLNC) techniques. We deal with a fundamental problem: the computational complexity of the RLNC decoder. The higher the number of decoding operations is, the more the user's computational overhead grows and, consequently, the faster the batteries of mobile devices drain. By referring to several sparse RLNC techniques, and without any assumption on the implementation of the RLNC decoder in use, we provide an efficient way to characterize the performance of users targeted by ultra-reliable layered multicast services. The proposed modeling allows to efficiently derive the average number of coded packet transmissions needed to recover one or more service layers. We design a convex resource allocation framework that allows to minimize the complexity of the RLNC decoder by jointly optimizing the transmission parameters and the sparsity of the code. The designed optimization framework also ensures service guarantees to predetermined fractions of users. Performance of the proposed optimization framework is then investigated in a LTE-A eMBMS network multicasting H.264/SVC video.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance analysis of gated ring oscillator designed for audio frequency ra...VLSICS Design
This paper presents performance analysis of Gated Ring Oscillator (GRO). Proposed GRO is designed to
employ in implementation of Time to Digital Converter (TDC) block of Asynchronous ADC. For an audio
frequency range ADC, minimum GRO stages are designed using asynchronous technique. So leads to
reduced area and power. Compared to conventional Ring Oscillator (RO), we avoided to employ the gated
clock; to evade clock design related problems like jitter, additional area and power. Instead we preferred
gating of ring oscillator itself. Consequently during sleep mode, GRO disables automatically which saves
the dynamic power. Furthermore it also provides first order noise shaping of the quantization and
mismatch noise. Proposed GRO is implemented with 0.18μm CMOS Digital Technology in Cadence
Virtuso environment. GRO performance analysis shows oscillation frequency as 286 KHz with 327ps jitter
and average power consumption of 1.08μW
Cancellation of Zigbee interference in OFDM based WLAN for multipath channelIDES Editor
Zigbee is one of the major sources of interference
in 2.4GHz band for WLANs. It is seen whenever any Zigbee
system is operating near to the WLAN system and
transmitting signal at same frequency, time as of WLAN’s, the
later ones performance detoriate severely. So in this paper an
algorithm is proposed to estimate Zigbee interference
component present in all OFDM based WLANs sub-carriers
and cancel out the Zigbee interference from the received
signal of WLANs receiver for multipath fading channels in
frequency domain. Simulation results shows for high SNR
values full cancellation of Zigbee interference or zero BER is
possible.
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
Performance Comparison of Rerouting Schemes of Multi Protocol Label Switching...IDES Editor
In this paper, we attempt to present a comparison
through rigorous studies (existing conventional models)
following software based modeling and verifications through
simulations in terms of various traffic parameters such as
packet loss, Recovery Time (Latency), reordering of packets
including recovery time for various widely used path recovery
models for the purpose of end-to-end recovery of LSPs in
MPLS domains using NS2 simulator.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Quadrangular Bézier Patches in Modeling and Modification of the Curvilinear B...IDES Editor
This paper proposes the use of quadrangular Bézier
patches to model and modify the shape of the boundary for
linear elasticity problems in 3D. The representation of the
boundary in this way derives directly from computer graphics
and have been analytically included in developed by the
authors parametric integral equation systems (PIES). PIES
are the modified classical boundary integral equations (BIE)
in which the shape of the boundary can be modeled using a
wide range of parametric curves and surfaces. The proposed
approach eliminates the need for domain and boundary
discretization in the process of solving boundary value
problems, in contrast to popular traditional methods like FEM
and BEM. On the basis of the proposed approach, a computer
code has been written and examined through numerical
examples.
Modern Enterprise Software Systems (MESS) is all
about envisioning, developing, managing and evolving
enterprise applications to fulfill business requirements. This
may entail many challenges like rapidly changing business
scenario, increase in complexity, shorter time to market and
business agility. In order to deal with this natural evolution,
achieving modularity across MESS is essential. In this paper,
we describe by way of an example application, some of the
common problems encountered while delivering & managing
enterprise software. We demonstrate that one of the root causes
for these is inadequate support for modularity at the physical
level viz. packaging & deployment. We look at the different
options available for extending the modularity across packaging
and deployment e.g. Impala and Open Service Gateway
initiative (OSGi). Based on our explorations and experiments
we provide a comparison between the two. We conclude the
paper with a note on the future directions for physical
modularity.
Optimal Synthesis of Array Pattern for Concentric Circular Antenna Array Usin...IDES Editor
In this paper one optimization heuristic search
technique, Hybrid Evolutionary Programming (HEP) is
applied to the process of synthesizing three-ring Concentric
Circular Antenna Array (CCAA) focused on maximum
sidelobe-level reduction. This paper assumes non-uniform
excitations and uniform spacing of excitation elements in each
three-ring CCAA design. Experimental results reveal that the
design of non-uniformly excited CCAAs with optimal current
excitations using the method of HEP provides a considerable
sidelobe level reduction with respect to the uniform current
excitation with d=λ/2 element-to-element spacing. Among the
various CCAA designs, the design containing central element
and 4, 6 and 8 elements in three successive concentric rings
proves to be such global optimal design with global minimum
SLL (-40.22 dB) as determined by HEP.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Sparse Random Network Coding for Reliable Multicast ServicesAndrea Tassi
Point-to-Multipoint communications are expected to play a pivotal role in next-generation networks. This talk refers to a cellular system transmitting layered multicast services to a Multicast Group (MG) of users. Reliability of communications is ensured via different Random Linear Network Coding (RLNC) techniques. We deal with a fundamental problem: the computational complexity of the RLNC decoder. The higher the number of decoding operations is, the more the user's computational overhead grows and, consequently, the faster the batteries of mobile devices drain. By referring to several sparse RLNC techniques, and without any assumption on the implementation of the RLNC decoder in use, we provide an efficient way to characterize the performance of users targeted by ultra-reliable layered multicast services. The proposed modeling allows to efficiently derive the average number of coded packet transmissions needed to recover one or more service layers. We design a convex resource allocation framework that allows to minimize the complexity of the RLNC decoder by jointly optimizing the transmission parameters and the sparsity of the code. The designed optimization framework also ensures service guarantees to predetermined fractions of users. Performance of the proposed optimization framework is then investigated in a LTE-A eMBMS network multicasting H.264/SVC video.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance analysis of gated ring oscillator designed for audio frequency ra...VLSICS Design
This paper presents performance analysis of Gated Ring Oscillator (GRO). Proposed GRO is designed to
employ in implementation of Time to Digital Converter (TDC) block of Asynchronous ADC. For an audio
frequency range ADC, minimum GRO stages are designed using asynchronous technique. So leads to
reduced area and power. Compared to conventional Ring Oscillator (RO), we avoided to employ the gated
clock; to evade clock design related problems like jitter, additional area and power. Instead we preferred
gating of ring oscillator itself. Consequently during sleep mode, GRO disables automatically which saves
the dynamic power. Furthermore it also provides first order noise shaping of the quantization and
mismatch noise. Proposed GRO is implemented with 0.18μm CMOS Digital Technology in Cadence
Virtuso environment. GRO performance analysis shows oscillation frequency as 286 KHz with 327ps jitter
and average power consumption of 1.08μW
Cancellation of Zigbee interference in OFDM based WLAN for multipath channelIDES Editor
Zigbee is one of the major sources of interference
in 2.4GHz band for WLANs. It is seen whenever any Zigbee
system is operating near to the WLAN system and
transmitting signal at same frequency, time as of WLAN’s, the
later ones performance detoriate severely. So in this paper an
algorithm is proposed to estimate Zigbee interference
component present in all OFDM based WLANs sub-carriers
and cancel out the Zigbee interference from the received
signal of WLANs receiver for multipath fading channels in
frequency domain. Simulation results shows for high SNR
values full cancellation of Zigbee interference or zero BER is
possible.
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
Performance Comparison of Rerouting Schemes of Multi Protocol Label Switching...IDES Editor
In this paper, we attempt to present a comparison
through rigorous studies (existing conventional models)
following software based modeling and verifications through
simulations in terms of various traffic parameters such as
packet loss, Recovery Time (Latency), reordering of packets
including recovery time for various widely used path recovery
models for the purpose of end-to-end recovery of LSPs in
MPLS domains using NS2 simulator.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Quadrangular Bézier Patches in Modeling and Modification of the Curvilinear B...IDES Editor
This paper proposes the use of quadrangular Bézier
patches to model and modify the shape of the boundary for
linear elasticity problems in 3D. The representation of the
boundary in this way derives directly from computer graphics
and have been analytically included in developed by the
authors parametric integral equation systems (PIES). PIES
are the modified classical boundary integral equations (BIE)
in which the shape of the boundary can be modeled using a
wide range of parametric curves and surfaces. The proposed
approach eliminates the need for domain and boundary
discretization in the process of solving boundary value
problems, in contrast to popular traditional methods like FEM
and BEM. On the basis of the proposed approach, a computer
code has been written and examined through numerical
examples.
Modern Enterprise Software Systems (MESS) is all
about envisioning, developing, managing and evolving
enterprise applications to fulfill business requirements. This
may entail many challenges like rapidly changing business
scenario, increase in complexity, shorter time to market and
business agility. In order to deal with this natural evolution,
achieving modularity across MESS is essential. In this paper,
we describe by way of an example application, some of the
common problems encountered while delivering & managing
enterprise software. We demonstrate that one of the root causes
for these is inadequate support for modularity at the physical
level viz. packaging & deployment. We look at the different
options available for extending the modularity across packaging
and deployment e.g. Impala and Open Service Gateway
initiative (OSGi). Based on our explorations and experiments
we provide a comparison between the two. We conclude the
paper with a note on the future directions for physical
modularity.
Optimal Synthesis of Array Pattern for Concentric Circular Antenna Array Usin...IDES Editor
In this paper one optimization heuristic search
technique, Hybrid Evolutionary Programming (HEP) is
applied to the process of synthesizing three-ring Concentric
Circular Antenna Array (CCAA) focused on maximum
sidelobe-level reduction. This paper assumes non-uniform
excitations and uniform spacing of excitation elements in each
three-ring CCAA design. Experimental results reveal that the
design of non-uniformly excited CCAAs with optimal current
excitations using the method of HEP provides a considerable
sidelobe level reduction with respect to the uniform current
excitation with d=λ/2 element-to-element spacing. Among the
various CCAA designs, the design containing central element
and 4, 6 and 8 elements in three successive concentric rings
proves to be such global optimal design with global minimum
SLL (-40.22 dB) as determined by HEP.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Dynamic Spectrum Derived Mfcc and Hfcc Parameters and Human Robot Speech Inte...IDES Editor
Using the Mel-frequency cepstral coefficients
(MFCC), Human Factor cepstral coefficients (HFCC) and
their new parameters derived from log dynamic spectrum and
dynamic log spectrum, these features are widely used for
speech recognition in various applications. But, speech
recognition systems based on these features do not perform
efficiently in the noisy conditions, mobile environment and
for speech variation between users of different genders and
ages. To maximize the recognition rate of speaker independent
isolated word recognition system, we combine both of the above
features and proposed a hybrid feature set of them. We tested
the system for this hybrid feature vector and we gained results
with accuracy of 86.17% in clean condition (closed window),
82.33% in class room open window environment, and 73.67%
in outdoor with noisy environment.
Context Driven Technique for Document ClassificationIDES Editor
In this paper we present an innovative hybrid Text
Classification (TC) system that bridges the gap between
statistical and context based techniques. Our algorithm
harnesses contextual information at two stages. First it extracts
a cohesive set of keywords for each category by using lexical
references, implicit context as derived from LSA and wordvicinity
driven semantics. And secondly, each document is
represented by a set of context rich features whose values are
derived by considering both lexical cohesion as well as the extent
of coverage of salient concepts via lexical chaining. After
keywords are extracted, a subset of the input documents is
apportioned as training set. Its members are assigned categories
based on their keyword representation. These labeled
documents are used to train binary SVM classifiers, one for
each category. The remaining documents are supplied to the
trained classifiers in the form of their context-enhanced feature
vectors. Each document is finally ascribed its appropriate
category by an SVM classifier.
Modelling of Crosstalk and Delay for Distributed RLCG On-Chip Interconnects F...IDES Editor
In order to accurately model high frequency affects,
inductance has been taken into consideration. No longer can
interconnects be treated as mere delays or lumped RC networks.
In that frequency range, the most accurate simulation model for
on-chip VLSI interconnects is the distributed RLC model.
Unfortunately, this model has many limitations at much higher
of operating frequency used in today’s VLSI design. The reduction
in cross-sectional dimension leads to more tightly couple
interconnects and therefore, a higher probability of unwanted
crosstalk interference. This can lead to inaccurate simulations
if not modelled properly. At even higher frequency, the aggressor
net carries a signal that couples to the victim net through the
parasitic capacitances. To determine the effects that this crosstalk
will have on circuit operation, the resulting delays and logic
levels for the victim nets must be computed. This paper proposes
a difference model approach to derive crosstalk and delay in the
transform domain. A closed form solution for crosstalk and delay
is obtained by incorporating initial conditions using difference
model approach for distributed RLCG interconnects. The
simulation is performed in 0.18μm technology node and an error
of less than 1% has been achieved with the proposed model when
compared with SPICE.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN...VLSICS Design
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Due to increasing complexity, space and cost of communication network, the Electric Power Network has been considered a great option for the solution of all problems. Power line communications (PLC) term stands for the technologies for the data communication over the electrical power supply network. Existing power system is not designed for having data transfer. In this paper we have developed a simulation model of power-line for low voltage distribution network in home. Impulse response of the channel is generated in order to characterize the behavior of power line channel for high speed data communication purpose. To represent Multi-branch network mathematically, ABCD matrix parameters are used. Load mismatching is experimented on three parameters multiple loading, multi branch and different cable length and analysis is presented of its effect on impulse response. All the simulation work has been done using MATLAB.
A XOR THRESHOLD LOGIC IMPLEMENTATION THROUGH RESONANT TUNNELING DIODEVLSICS Design
Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics. The design and fabrication of linear threshold gates will be presented based on a monostable bistable transition logic element. Each of its input terminals consist out of a resonant tunnelling diode merged with a transistor device. The circuit models of RTD and MOSFET are simulated in HSPICE. Two input XOR gate is designed and tested.
BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED VLSICS Design
Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron technologies (DSM), on-chip inductive effects have increased due to faster clock speeds, smaller signal rise times and longer length of on-chip interconnects. All these issues raise the concern for crosstalk, propagation delay and power dissipation of overall. Therefore, this research work introduces an efficient Bus Encoder using Bus Inverting (BI) method. The proposed design dramatically reduces both crosstalk and power dissipation in RLC modeled interconnects which makes it suitable for current high-speed low-power VLSI interconnects. The proposed model demonstrates an overall reduction of power dissipation and crosstalk induced delay by 55.43% and 45.87%, respectively.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
Reach and Operating Time Correction of Digital Distance Relay Yayah Zakaria
Current and voltage signals recieved from conventional iron core Current Transformer (CT) and Voltage Transformer plays very important role for correct operation of Distance Distance Relay (DDR). Increase in secondary burden connected to CT causes it to saturate at earlier stage. The saturated CT produces distorted secondary current, causing DDR to under reach and to operate by certain time delay. Rogowski Coils (RCs) are attaining increased acceptance and use in electrical power system due to their inherent linearity, greater accuracy and wide operating current range. This paper presents use of RC as an advanced measurement device suitable for DDR. Case study for validation of use of RC is carried out on low voltage system. The simulation results of Distance protection scheme used for protection of part of 220kV AC system shows excellent performance of RC over CT under abnormal conditions.
Reach and Operating Time Correction of Digital Distance Relay IJECEIAES
Current and voltage signals recieved from conventional iron core Current Transformer (CT) and Voltage Transformer plays very important role for correct operation of Distance Distance Relay (DDR). Increase in secondary burden connected to CT causes it to saturate at earlier stage. The saturated CT produces distorted secondary current, causing DDR to under reach and to operate by certain time delay. Rogowski Coils (RCs) are attaining increased acceptance and use in electrical power system due to their inherent linearity, greater accuracy and wide operating current range. This paper presents use of RC as an advanced measurement device suitable for DDR. Case study for validation of use of RC is carried out on low voltage system. The simulation results of Distance protection scheme used for protection of part of 220kV AC system shows excellent performance of RC over CT under abnormal conditions.
An Explicit Approach for Dynamic Power Evaluation for Deep submicron Global I...IDES Editor
As the VLSI process technology is shrinking to the
nanometer regime, power consumption of on-chip VLSI
interconnects has become a crucial and an important issue.
There are several methodologies proposed to estimate the onchip
power consumption using Voltage Mode Signaling
technique (VMS). But the major drawback of VMS is that it
increases the power consumption of on-chip interconnects
compared to current mode signaling (CMS). A closed form
formula is, thus, necessary for current mode signaling to
accurately estimate the power dissipation in the distributed
line. In this paper, we derived an explicit dynamic power
formula in S-domain based on Modified Nodal Analysis
(MNA) formulation. The usefulness of our approach is that
dynamic power consumption of an interconnect line can be
estimated accurately and efficiently at any operating
frequency. By substituting s=0 in the vector of node voltages
in our model results similar solution as that of Bashirullah
et. al. Comparison of simulation results with other
established models justifies the accuracy of our approach.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI In...VLSICS Design
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
Similar to Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for Different Pole Conditions (20)
Power System State Estimation - A ReviewIDES Editor
The aim of this article is to provide a comprehensive
survey on power system state estimation techniques. The
algorithms used for finding the system states under both static
and dynamic state estimations are discussed in brief. The
authors are opinion that the scope of pursuing research in the
area of state estimation with PMU and SCADA measurements
is the state of the art and timely.
Artificial Intelligence Technique based Reactive Power Planning Incorporating...IDES Editor
Reactive Power Planning is a major concern in the
operation and control of power systems This paper compares
the effectiveness of Evolutionary Programming (EP) and
New Improved Differential Evolution (NIMDE) to solve
Reactive Power Planning (RPP) problem incorporating
FACTS Controllers like Static VAR Compensator (SVC),
Thyristor Controlled Series Capacitor (TCSC) and Unified
power flow controller (UPFC) considering voltage stability.
With help of Fast Voltage Stability Index (FVSI), the critical
lines and buses are identified to install the FACTS controllers.
The optimal settings of the control variables of the generator
voltages,transformer tap settings and allocation and parameter
settings of the SVC,TCSC,UPFC are considered for reactive
power planning. The test and Validation of the proposed
algorithm are conducted on IEEE 30–bus system and 72-bus
Indian system.Simulation results shows that the UPFC gives
better results than SVC and TCSC and the FACTS controllers
reduce the system losses.
Design and Performance Analysis of Genetic based PID-PSS with SVC in a Multi-...IDES Editor
Damping of power system oscillations with the help
of proposed optimal Proportional Integral Derivative Power
System Stabilizer (PID-PSS) and Static Var Compensator
(SVC)-based controllers are thoroughly investigated in this
paper. This study presents robust tuning of PID-PSS and
SVC-based controllers using Genetic Algorithms (GA) in
multi machine power systems by considering detailed model
of the generators (model 1.1). The effectiveness of FACTSbased
controllers in general and SVC-based controller in
particular depends upon their proper location. Modal
controllability and observability are used to locate SVC–based
controller. The performance of the proposed controllers is
compared with conventional lead-lag power system stabilizer
(CPSS) and demonstrated on 10 machines, 39 bus New England
test system. Simulation studies show that the proposed genetic
based PID-PSS with SVC based controller provides better
performance.
Optimal Placement of DG for Loss Reduction and Voltage Sag Mitigation in Radi...IDES Editor
This paper presents the need to operate the power
system economically and with optimum levels of voltages has
further led to an increase in interest in Distributed
Generation. In order to reduce the power losses and to improve
the voltage in the distribution system, distributed generators
(DGs) are connected to load bus. To reduce the total power
losses in the system, the most important process is to identify
the proper location for fixing and sizing of DGs. It presents a
new methodology using a new population based meta heuristic
approach namely Artificial Bee Colony algorithm(ABC) for
the placement of Distributed Generators(DG) in the radial
distribution systems to reduce the real power losses and to
improve the voltage profile, voltage sag mitigation. The power
loss reduction is important factor for utility companies because
it is directly proportional to the company benefits in a
competitive electricity market, while reaching the better power
quality standards is too important as it has vital effect on
customer orientation. In this paper an ABC algorithm is
developed to gain these goals all together. In order to evaluate
sag mitigation capability of the proposed algorithm, voltage
in voltage sensitive buses is investigated. An existing 20KV
network has been chosen as test network and results are
compared with the proposed method in the radial distribution
system.
Line Losses in the 14-Bus Power System Network using UPFCIDES Editor
Controlling power flow in modern power systems
can be made more flexible by the use of recent developments
in power electronic and computing control technology. The
Unified Power Flow Controller (UPFC) is a Flexible AC
transmission system (FACTS) device that can control all the
three system variables namely line reactance, magnitude and
phase angle difference of voltage across the line. The UPFC
provides a promising means to control power flow in modern
power systems. Essentially the performance depends on proper
control setting achievable through a power flow analysis
program. This paper presents a reliable method to meet the
requirements by developing a Newton-Raphson based load
flow calculation through which control settings of UPFC can
be determined for the pre-specified power flow between the
lines. The proposed method keeps Newton-Raphson Load Flow
(NRLF) algorithm intact and needs (little modification in the
Jacobian matrix). A MATLAB program has been developed to
calculate the control settings of UPFC and the power flow
between the lines after the load flow is converged. Case studies
have been performed on IEEE 5-bus system and 14-bus system
to show that the proposed method is effective. These studies
indicate that the method maintains the basic NRLF properties
such as fast computational speed, high degree of accuracy and
good convergence rate.
Study of Structural Behaviour of Gravity Dam with Various Features of Gallery...IDES Editor
The size and shape of opening in dam causes the
stress concentration, it also causes the stress variation in the
rest of the dam cross section. The gravity method of the analysis
does not consider the size of opening and the elastic property
of dam material. Thus the objective of study is comprises of
the Finite Element Method which considers the size of
opening, elastic property of material, and stress distribution
because of geometric discontinuity in cross section of dam.
Stress concentration inside the dam increases with the opening
in dam which results in the failure of dam. Hence it is
necessary to analyses large opening inside the dam. By making
the percentage area of opening constant and varying size and
shape of opening the analysis is carried out. For this purpose
a section of Koyna Dam is considered. Dam is defined as a
plane strain element in FEM, based on geometry and loading
condition. Thus this available information specified our path
of approach to carry out 2D plane strain analysis. The results
obtained are then compared mutually to get most efficient
way of providing large opening in the gravity dam.
Assessing Uncertainty of Pushover Analysis to Geometric ModelingIDES Editor
Pushover Analysis a popular tool for seismic
performance evaluation of existing and new structures and is
nonlinear Static procedure where in monotonically increasing
loads are applied to the structure till the structure is unable
to resist the further load .During the analysis, whatever the
strength of concrete and steel is adopted for analysis of
structure may not be the same when real structure is
constructed and the pushover analysis results are very sensitive
to material model adopted, geometric model adopted, location
of plastic hinges and in general to procedure followed by the
analyzer. In this paper attempt has been made to assess
uncertainty in pushover analysis results by considering user
defined hinges and frame modeled as bare frame and frame
with slab modeled as rigid diaphragm and results compared
with experimental observations. Uncertain parameters
considered includes the strength of concrete, strength of steel
and cover to the reinforcement which are randomly generated
and incorporated into the analysis. The results are then
compared with experimental observations.
Secure Multi-Party Negotiation: An Analysis for Electronic Payments in Mobile...IDES Editor
This paper is an attempt to base on auctions which
presents a frame work for the secure multi-party decision
protocols. In addition to the implementations which are very
light weighted, the main focus is on synchronizing security
features for avoiding agreements manipulations and reducing
the user traffic. Through this paper one can understand that
this different auction protocols on top of the frame work can
be collaborated using mobile devices. This paper present the
negotiation between auctioneer and the proffered and this
negotiation shows that multiparty security is far better than
the existing system.
Selfish Node Isolation & Incentivation using Progressive ThresholdsIDES Editor
The problems associated with selfish nodes in
MANET are addressed by a collaborative watchdog approach
which reduces the detection time for selfish nodes thereby
improves the performance and accuracy of watchdogs[1]. In
the related works they make use of credit based systems, reputation
based mechanisms, pathrater and watchdog mechanism
to detect such selfish nodes. In this paper we follow an approach
of collaborative watchdog which reduces the detection
time for selfish nodes and also involves the removal of such
selfish nodes based on some progressively assessed thresholds.
The threshold gives the nodes a chance to stop misbehaving
before it is permanently deleted from the network.
The node passes through several isolation processes before it
is permanently removed. Another version of AODV protocol
is used here which allows the simulation of selfish nodes in
NS2 by adding or modifying log files in the protocol.
Various OSI Layer Attacks and Countermeasure to Enhance the Performance of WS...IDES Editor
Wireless sensor networks are networks having non
wired infrastructure and dynamic topology. In OSI model each
layer is prone to various attacks, which halts the performance
of a network .In this paper several attacks on four layers of
OSI model are discussed and security mechanism is described
to prevent attack in network layer i.e wormhole attack. In
Wormhole attack two or more malicious nodes makes a covert
channel which attracts the traffic towards itself by depicting a
low latency link and then start dropping and replaying packets
in the multi-path route. This paper proposes promiscuous mode
method to detect and isolate the malicious node during
wormhole attack by using Ad-hoc on demand distance vector
routing protocol (AODV) with omnidirectional antenna. The
methodology implemented notifies that the nodes which are
not participating in multi-path routing generates an alarm
message during delay and then detects and isolate the
malicious node from network. We also notice that not only
the same kind of attacks but also the same kind of
countermeasures can appear in multiple layer. For example,
misbehavior detection techniques can be applied to almost all
the layers we discussed.
Responsive Parameter based an AntiWorm Approach to Prevent Wormhole Attack in...IDES Editor
The recent advancements in the wireless technology
and their wide-spread deployment have made remarkable
enhancements in efficiency in the corporate and industrial
and Military sectors The increasing popularity and usage of
wireless technology is creating a need for more secure wireless
Ad hoc networks. This paper aims researched and developed
a new protocol that prevents wormhole attacks on a ad hoc
network. A few existing protocols detect wormhole attacks but
they require highly specialized equipment not found on most
wireless devices. This paper aims to develop a defense against
wormhole attacks as an Anti-worm protocol which is based on
responsive parameters, that does not require as a significant
amount of specialized equipment, trick clock synchronization,
no GPS dependencies.
Cloud Security and Data Integrity with Client Accountability FrameworkIDES Editor
The Cloud based services provide much efficient
and seamless ways for data sharing across the cloud. The fact
that the data owners no longer possess data makes it very
difficult to assure data confidentiality and to enable secure
data sharing in the cloud. Despite of all its advantages this
will remain a major limitation that acts as a barrier to the
wider deployment of cloud based services. One of the possible
ways for ensuring trust in this aspect is the introduction of
accountability feature in the cloud computing scenario. The
Cloud framework requires promotion of distributed
accountability for such dynamic environment[1]. In some
works, there‘s an accountable framework suggested to ensure
distributed accountability for data sharing by the generation
of only a log of data access, but without any embedded feedback
mechanism for owner permission towards data
protection[2].The proposed system is an enhanced client
accountability framework which provides an additional client
side verification for each access towards enhanced security of
data. The integrity of content of data which resides in the
cloud service provider is also maintained by secured
outsourcing. Besides, the authentication of JAR(Java Archive)
files are done to ensure file protection and to maintain a safer
environment for data sharing. The analysis of various
functionalities of the framework depicts both the
accountability and security feature in an efficient manner.
Genetic Algorithm based Layered Detection and Defense of HTTP BotnetIDES Editor
A System state in HTTP botnet uses HTTP protocol
for the creation of chain of Botnets thereby compromising
other systems. By using HTTP protocol and port number 80,
attacks can not only be hidden but also pass through the
firewall without being detected. The DPR based detection
leads to better analysis of botnet attacks [3]. However, it
provides only probabilistic detection of the attacker and also
time consuming and error prone. This paper proposes a Genetic
algorithm based layered approach for detecting as well as
preventing botnet attacks. The paper reviews p2p firewall
implementation which forms the basis of filtering.
Performance evaluation is done based on precision, F-value
and probability. Layered approach reduces the computation
and overall time requirement [7]. Genetic algorithm promises
a low false positive rate.
Enhancing Data Storage Security in Cloud Computing Through SteganographyIDES Editor
in cloud computing data storage is a significant issue
because the entire data reside over a set of interconnected
resource pools that enables the data to be accessed through
virtual machines. It moves the application software’s and
databases to the large data centers where the management of
data is actually done. As the resource pools are situated over
various corners of the world, the management of data and
services may not be fully trustworthy. So, there are various
issues that need to be addressed with respect to the
management of data, service of data, privacy of data, security
of data etc. But the privacy and security of data is highly
challenging. To ensure privacy and security of data-at-rest in
cloud computing, we have proposed an effective and a novel
approach to ensure data security in cloud computing by means
of hiding data within images following is the concept of
steganography. The main objective of this paper is to prevent
data access from cloud data storage centers by unauthorized
users. This scheme perfectly stores data at cloud data storage
centers and retrieves data from it when it is needed.
The main tasks of a Wireless Sensor Network
(WSN) are data collection from its nodes and communication
of this data to the base station (BS). The protocols used for
communication among the WSN nodes and between the WSN
and the BS, must consider the resource constraints of nodes,
battery energy, computational capabilities and memory. The
WSN applications involve unattended operation of the network
over an extended period of time. In order to extend the lifetime
of a WSN, efficient routing protocols need to be adopted. The
proposed low power routing protocol based on tree-based
network structure reliably forwards the measured data towards
the BS using TDMA. An energy consumption analysis of the
WSN making use of this protocol is also carried out. It is
found that the network is energy efficient with an average
duty cycle of 0:7% for the WSN nodes. The OmNET++
simulation platform along with MiXiM framework is made
use of.
Permutation of Pixels within the Shares of Visual Cryptography using KBRP for...IDES Editor
The security of authentication of internet based
co-banking services should not be susceptible to high risks.
The passwords are highly vulnerable to virus attacks due to
the lack of high end embedding of security methods. In order
for the passwords to be more secure, people are generally
compelled to select jumbled up character based passwords
which are not only less memorable but are also equally prone
to insecurity. Multiple use of distributed shares has been
studied to solve the problem of authentication by algorithms
based on thresholding of pixels in image processing and visual
cryptography concepts where the subset of shares is considered
for the recovery of the original image for authentication using
correlation function[1][2].The main disadvantage in the above
study is the plain storage of shares and also one of the shares
is being supplied to the customer, which will lead to the
possibility of misuse by a third party. This paper proposes a
technique for scrambling of pixels by key based random
permutation (KBRP) within the shares before the
authentication has been attempted. Total number of shares to
be created is dependent on the multiplicity of ownership of
the account. By this method the problem of uncertainty among
the customers with regard to security, storage, retrieval of
holding of half of the shares is minimized.
This paper presents a trifocal Rotman Lens Design
approach. The effects of focal ratio and element spacing on
the performance of Rotman Lens are described. A three beam
prototype feeding 4 element antenna array working in L-band
has been simulated using RLD v1.7 software. Simulated
results show that the simulated lens has a return loss of –
12.4dB at 1.8GHz. Beam to array port phase error variation
with change in the focal ratio and element spacing has also
been investigated.
Band Clustering for the Lossless Compression of AVIRIS Hyperspectral ImagesIDES Editor
Hyperspectral images can be efficiently compressed
through a linear predictive model, as for example the one
used in the SLSQ algorithm. In this paper we exploit this
predictive model on the AVIRIS images by individuating,
through an off-line approach, a common subset of bands, which
are not spectrally related with any other bands. These bands
are not useful as prediction reference for the SLSQ 3-D
predictive model and we need to encode them via other
prediction strategies which consider only spatial correlation.
We have obtained this subset by clustering the AVIRIS bands
via the clustering by compression approach. The main result
of this paper is the list of the bands, not related with the
others, for AVIRIS images. The clustering trees obtained for
AVIRIS and the relationship among bands they depict is also
an interesting starting point for future research.
Microelectronic Circuit Analogous to Hydrogen Bonding Network in Active Site ...IDES Editor
A microelectronic circuit of block-elements
functionally analogous to two hydrogen bonding networks is
investigated. The hydrogen bonding networks are extracted
from â-lactamase protein and are formed in its active site.
Each hydrogen bond of the network is described in equivalent
electrical circuit by three or four-terminal block-element.
Each block-element is coded in Matlab. Static and dynamic
analyses are performed. The resultant microelectronic circuit
analogous to the hydrogen bonding network operates as
current mirror, sine pulse source, triangular pulse source as
well as signal modulator.
Texture Unit based Monocular Real-world Scene Classification using SOM and KN...IDES Editor
In this paper a method is proposed to discriminate
real world scenes in to natural and manmade scenes of similar
depth. Global-roughness of a scene image varies as a function
of image-depth. Increase in image depth leads to increase in
roughness in manmade scenes; on the contrary natural scenes
exhibit smooth behavior at higher image depth. This particular
arrangement of pixels in scene structure can be well explained
by local texture information in a pixel and its neighborhood.
Our proposed method analyses local texture information of a
scene image using texture unit matrix. For final classification
we have used both supervised and unsupervised learning using
K-Nearest Neighbor classifier (KNN) and Self Organizing
Map (SOM) respectively. This technique is useful for online
classification due to very less computational complexity.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.