As the VLSI process technology is shrinking to the
nanometer regime, power consumption of on-chip VLSI
interconnects has become a crucial and an important issue.
There are several methodologies proposed to estimate the onchip
power consumption using Voltage Mode Signaling
technique (VMS). But the major drawback of VMS is that it
increases the power consumption of on-chip interconnects
compared to current mode signaling (CMS). A closed form
formula is, thus, necessary for current mode signaling to
accurately estimate the power dissipation in the distributed
line. In this paper, we derived an explicit dynamic power
formula in S-domain based on Modified Nodal Analysis
(MNA) formulation. The usefulness of our approach is that
dynamic power consumption of an interconnect line can be
estimated accurately and efficiently at any operating
frequency. By substituting s=0 in the vector of node voltages
in our model results similar solution as that of Bashirullah
et. al. Comparison of simulation results with other
established models justifies the accuracy of our approach.
Power dissipation has emerged an important parameter in design of Low Power CMOS circuits. For this level
converter and dual supply voltage assignments are used to reduce the power dissipation and propagation delay.
In this paper, variable supply-voltage scheme (dual-VS scheme) for dual power supplies along with voltage
level converter is presented. Also paper presents an overall comparative analysis among various methods to
achieve voltage level shifter even in lower technology comparative to higher ones and help user to select the
best methods for same at this technology.
Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for ...IDES Editor
Fast delay estimation methods, as compared to
simulation techniques, are needed for incremental
performance-driven layout synthesis. On-chip inductive and
conductive effects are becoming predominant in deep
submicron (DSM) interconnects due to increasing clock
speeds; circuit complexity and interconnect lengths.
Inductance causes noise in the signal waveforms, which can
adversely affect the performance of the circuit and signal
integrity. Elmore delay-based estimation methods, although
efficient, fails to accurately estimate the delay for RLCG
interconnect lines. This paper presents an analytical delay
model, based on first and second moments of RLCG
interconnection lines, that considers the effect of inductance
and conductance for the estimation of delay in interconnection
lines. Simulation results justify the efficacy of the proposed
delay modelling approach.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
This document analyzes site selection diversity transmission (SSDT) for 3GPP WCDMA forward link and compares it to hard handover (HHO) and soft handover (SHO). It finds that SSDT can provide performance gains over HHO and SHO, but these gains may be reduced by feedback bit errors. The performance of each method is modeled and analyzed mathematically to derive bit error probability expressions as a function of signal-to-noise ratio. Feedback bit errors are also accounted for in the SSDT analysis.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
Interleaving Technique in Multiphase Buck & Boost ConverterIDES Editor
Some of the recent applications in the field of the
power supplies use multiphase converters to achieve fast
dynamic response, smaller input/output filters or better
packaging. Typically, these converters have several paralleled
power stages with a current loop in each phase and a unique
voltage loop. The presence of the current loops is necessary to
increase dynamic response (by using Current mode control)
and to avoid current unbalance among phases.
Power dissipation has emerged an important parameter in design of Low Power CMOS circuits. For this level
converter and dual supply voltage assignments are used to reduce the power dissipation and propagation delay.
In this paper, variable supply-voltage scheme (dual-VS scheme) for dual power supplies along with voltage
level converter is presented. Also paper presents an overall comparative analysis among various methods to
achieve voltage level shifter even in lower technology comparative to higher ones and help user to select the
best methods for same at this technology.
Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for ...IDES Editor
Fast delay estimation methods, as compared to
simulation techniques, are needed for incremental
performance-driven layout synthesis. On-chip inductive and
conductive effects are becoming predominant in deep
submicron (DSM) interconnects due to increasing clock
speeds; circuit complexity and interconnect lengths.
Inductance causes noise in the signal waveforms, which can
adversely affect the performance of the circuit and signal
integrity. Elmore delay-based estimation methods, although
efficient, fails to accurately estimate the delay for RLCG
interconnect lines. This paper presents an analytical delay
model, based on first and second moments of RLCG
interconnection lines, that considers the effect of inductance
and conductance for the estimation of delay in interconnection
lines. Simulation results justify the efficacy of the proposed
delay modelling approach.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
This document analyzes site selection diversity transmission (SSDT) for 3GPP WCDMA forward link and compares it to hard handover (HHO) and soft handover (SHO). It finds that SSDT can provide performance gains over HHO and SHO, but these gains may be reduced by feedback bit errors. The performance of each method is modeled and analyzed mathematically to derive bit error probability expressions as a function of signal-to-noise ratio. Feedback bit errors are also accounted for in the SSDT analysis.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
Interleaving Technique in Multiphase Buck & Boost ConverterIDES Editor
Some of the recent applications in the field of the
power supplies use multiphase converters to achieve fast
dynamic response, smaller input/output filters or better
packaging. Typically, these converters have several paralleled
power stages with a current loop in each phase and a unique
voltage loop. The presence of the current loops is necessary to
increase dynamic response (by using Current mode control)
and to avoid current unbalance among phases.
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...IRJET Journal
This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This chapter discusses CMOS active inductors, including the principles of gyrator-C based synthesis of inductors. Section 2.1 examines single-ended and floating configurations of lossless and lossy gyrator-C active inductors. Section 2.2 characterizes important performance metrics of active inductors such as frequency range, quality factor, noise, and power consumption. Section 2.3 details implementation of single-ended gyrator-C inductors while Section 2.4 examines floating configurations. Class AB active inductors are covered in Section 2.5 and the chapter is summarized in Section 2.6.
This paper presents a new simplified cascade multiphase DC-DC buck power converter suitable for low voltage and large current applications. Cascade connection enables very low voltage ratio without using very small duty cycles nor transformers. Large current with very low ripple content is achieved by using the multiphase technique. The proposed converter needs smaller number of components compared to conventional cascade multiphase DC-DC buck power converters. This paper also presents useful analysis of the proposed DC-DC buck power converter with a method to optimize the phase and cascade number. Simulation and experimental results are included to verify the basic performance of the proposed DC-DC buck power converter.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
This document discusses Matlab/Simulink implementation for reducing motor derating and torque pulsation of an induction motor using a matrix converter. It provides background on how non-sinusoidal supply from traditional inverters causes harmonic losses and torque pulsation in induction motors. The document summarizes simulation results showing that a matrix converter can provide a pure sinusoidal supply, reducing harmonic losses and torque pulsation. Simulations of a matrix converter driving an induction motor in Matlab/Simulink are presented, showing sinusoidal voltage/current waveforms and reduced torque pulsation at steady state.
Analysis of switching and matching stubs in reconfigurable power divider with...TELKOMNIKA JOURNAL
In this paper, performance analysis of switching and matching stubs was done to a reconfigurable power divider with Single Pole Double Throw (SPDT) switch function. Two designs (Design A and Design B) with different positions of switches and matching stubs were proposed. Rogers RO4350 (er=3.48, h=0.508 mm) was used in this analysis as a substrate material with copper thickness of 0.035 mm. The performance analysis was carried out based on insertion loss, return loss and isolation parameters. The simulated results showed that Design B had a better performance than Design A and was able to work as a reconfigurable power divider with SPDT switch function.
This document analyzes the dimensioning space of a parallel tuned integrated circuit amplifier that was previously designed and implemented. It begins by introducing the circuit topology being analyzed, which includes an output capacitor, bias inductor, and parallel resonator. Equations are then derived to calculate the admittances, load resistance, resonant frequency, and component values based on varying design parameters. Performance contours are shown for both an ideal resistive load and with ideal low-pass and high-pass matching networks. The maximum efficiency increased from 77% to 81% with matching networks, while maximum output power increased from 4.1W to 4.9W.
This document discusses cascaded H-bridge multilevel inverters and their symmetrical and asymmetrical configurations. It begins by introducing two-level and multilevel inverters, noting that multilevel inverters are better suited for high power and voltage applications as they reduce harmonics. There are three main multilevel inverter topologies: neutral-point-clamped, flying capacitors, and cascaded H-bridges. The cascaded H-bridge topology connects H-bridge cells in series to generate stepped voltage waveforms. Symmetrical configurations use equal DC voltages for each cell, while asymmetrical configurations use unequal voltages, allowing more voltage levels with the same number of cells. The document presents simulations of
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
Neuro-Fuzzy Five-level Cascaded Multilevel Inverter for Active Power FilterIDES Editor
This paper presents an investigation of five-Level
Cascaded H-bridge(CHB) inverter as Active Power Filter in
Power System (PS) for compensation of reactive power and
harmonics. The advantages of CHB inverter are low harmonic
distortion, reduced number of switches and suppression of
switching losses. The Active Power Filter helps to improve
the power factor and eliminate the Total Harmonics Distortion
(THD) drawn from a Non-Liner Diode Rectifier Load (NLDRL).
The D-Q reference frame theory is used to generate the
reference compensating currents for Active Power Filter
while Neuro-Fuzzy controller(NFC) is used for capacitor dc
voltage regulation. A CHB Inverter is considered for shunt
compensation of a 11 kV distribution system. Finally a level
shifted PWM (LSPWM) technique adopted to investigate the
performance of CHB Inverter. The results are obtained through
Mat lab / Simulink .
ETDCC: Energy-Efficient Transmission Scheme for Dynamic Climatic Conditions i...TELKOMNIKA JOURNAL
In this paper, an energy-efficient transmission scheme for dynamic climatic conditions (ETDCC)
has been proposed in wireless sensor networks (WSNs). This scheme is based on IEEE802.15.4 standard.
In this method, open-loop and closed-loop feedback systems are used for snowfall variation. An open-loop
system is utilized for snowfall-aware link quality compensation and estimation. However, closed-loop system
aids to split the network into two logical regions, resulting the overhead of total control packets is minimized.
According to link quality changes due to snowfall variation, the transmitting power is decided on the basis of
current number of neighbor nodes and threshold power loss for each region. The simulated results depict
that the proposed scheme with reduced control packets overhead adjusts transmitting power level (Plevel) to
compensate link quality. This scheme based on threshold level is compared with the conventional approach
that comprises the division of regions without threshold level.
10 17sep 8310 10079-1-ed pulse density (edit ari)IAESIJEECS
Switched mode power supply (SMPS) converter is a dc-dc power electronic converter which is used to step up or step down the dc output voltage. A dimmable driver circuit for Light Emitting Diode (LED) lamp for automotive lighting with dimming feature is used in this paper. A flyback converter is used as a driver circuit operated in discontinuous conduction mode to perform dimming control of LEDs. High overall circuit efficiency is achieved by regulating the current through the LED lamps using pulse density modulation scheme. The LED driver circuit design and operating principle is discussed in detail. A gentle current control feature is achieved by pulse density modulation technique. The high performance driver circuit is designed for 25 W LED lamps.
A New Soft-Switched Resonant DC-DC ConverterIDES Editor
This paper presents a new soft-switched resonant
dc-dc converter using a passive snubber circuit. The
proposed converter uses a new zero voltage and zero current
switching (ZVZCS) strategies to get ZVZCS function.
Besides operating at constant frequency, all semiconductor
devices operate at soft-switching without additional voltage
and current stresses. In order to validate the proposed
converter, computer simulations and experimental results
were conducted. The paper indicates the effective converter
operation region of the soft-switching action and its
efficiency improvement results on the basis of experimental
evaluations using laboratory prototype.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Enabling relay selection in non-orthogonal multiple access networks: direct a...TELKOMNIKA JOURNAL
In this paper, we consider downlink non-orthogonal multiple access (NOMA) in which the relay selection (RS) scheme is enabled for cooperative networks. In particular, we investigate impact of the number of relays on system performance in term of outage probability. The main factors affecting on cooperative NOMA performance are fixed power allocations coefficients and the number of relay. This paper also indicate performance gap of the outage probabilities among two users the context of NOMA. To exhibit the exactness of derived formula, we match related results between simulation and analytical methods. Numerical results confirms that cooperative NOMA networks benefit from increasing the number of relay.
Low Complex-Hierarchical Coding Compression Approach for Arial ImagesIDES Editor
Image compression is an extended research area
from a long time. Various compression schemes were
developed for the compression of image in gray scaling and
color image compression. Basically the compression is
focused for lossy or lossless color image compression based
on the need of applications. Where lossy compression are
higher in compression ratio but are observed to be lower in
retrieval accuracy. Various compression techniques such as
JPEG and JPEG-2K architectures are developed to realize
such and method. But with the need in high accuracy
retreivation these techniques[8] are not suitable. To achieve
nearby lossless compression[1] various other coding methods
were suggested like lifting scheme coding. This coding result
in very high retrieval accuracy but gives low compression
ratio. This limitation is a bottleneck in current image
compression architectures. So, there is a need in the
development of a compressing approach where both higher
compression as well as higher retrieval accuracy is obtained.
Treatment of NOx from Diesel Engine Exhaust by Dielectric Barrier Discharge M...IDES Editor
This document summarizes research on using a dielectric barrier discharge method to treat NOx emissions from diesel engine exhaust. Key points:
1) Experiments were conducted using a cross-flow dielectric barrier discharge reactor to treat exhaust from a 3.75 kW diesel generator set. NOx removal was tested at different gas flow rates and voltages.
2) The discharge plasma reactor showed promising results in removing NOx at high flow rates of up to 10 L/min. NO was converted to NO2 and then reduced to N2 via reaction with radicals generated by the plasma.
3) Over 76% removal of NOx was achieved at a specific energy density of 97 J/L and a flow rate of 10 L
Hybrid Particle Swarm Optimization for Multi-objective Reactive Power Optimiz...IDES Editor
This paper proposes a hybrid particle swarm optimization (HPSO) method to solve the multi-objective reactive power dispatch problem of minimizing transmission losses and maximizing voltage stability. The HPSO method expands on PSO and genetic algorithms to handle mixed integer and nonlinear optimization problems with both continuous and discrete control variables. The method is evaluated on the IEEE 30-bus and 57-bus test systems. Results show the HPSO approach improves voltage stability compared to conventional, genetic algorithm, and particle swarm optimization methods.
A Simple Novel Method of Torque Ripple Minimization in Fuel Cell Based PMSM D...IDES Editor
Non-Conventional energy sources are the
promising alternatives for future energy crisis. Fuel cells
are upcoming non-conventional energy sources nowadays.
Fuel cell based PMSM drives are used as Hybrid Electric
Vehicles. PMSM drives are nowadays replacing the
induction motor drives for they have many advantages
such as high speed, high efficiency, high torque to inertia
ratio, high power density etc.,. However the main problem
in PMSM drives is the ripples produced in the torque. Also
if these PMSM’S are used as such for HEV applications,
then the performance of the HEV will not be satisfactory
and the life span of the same will be short. Many methods
have been proposed in literatures for the minimization of
these ripples. In this paper a novel method of reduction of
torque ripples has been proposed. Further the main source
of energy supply is the fuel cells. Hence this method is as a
whole useful for PMSM drives which have their source of
energy as fuel cells. The proposed method is validated by
using MATLAB/SIMULINK. The proposed circuit and a
conventional circuit are simulated and the simulated
results are shown. It has been observed that the proposed
method gives rise to very much minimized torque ripples
than when compared with the conventional circuit.
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...IRJET Journal
This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This chapter discusses CMOS active inductors, including the principles of gyrator-C based synthesis of inductors. Section 2.1 examines single-ended and floating configurations of lossless and lossy gyrator-C active inductors. Section 2.2 characterizes important performance metrics of active inductors such as frequency range, quality factor, noise, and power consumption. Section 2.3 details implementation of single-ended gyrator-C inductors while Section 2.4 examines floating configurations. Class AB active inductors are covered in Section 2.5 and the chapter is summarized in Section 2.6.
This paper presents a new simplified cascade multiphase DC-DC buck power converter suitable for low voltage and large current applications. Cascade connection enables very low voltage ratio without using very small duty cycles nor transformers. Large current with very low ripple content is achieved by using the multiphase technique. The proposed converter needs smaller number of components compared to conventional cascade multiphase DC-DC buck power converters. This paper also presents useful analysis of the proposed DC-DC buck power converter with a method to optimize the phase and cascade number. Simulation and experimental results are included to verify the basic performance of the proposed DC-DC buck power converter.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
This document discusses Matlab/Simulink implementation for reducing motor derating and torque pulsation of an induction motor using a matrix converter. It provides background on how non-sinusoidal supply from traditional inverters causes harmonic losses and torque pulsation in induction motors. The document summarizes simulation results showing that a matrix converter can provide a pure sinusoidal supply, reducing harmonic losses and torque pulsation. Simulations of a matrix converter driving an induction motor in Matlab/Simulink are presented, showing sinusoidal voltage/current waveforms and reduced torque pulsation at steady state.
Analysis of switching and matching stubs in reconfigurable power divider with...TELKOMNIKA JOURNAL
In this paper, performance analysis of switching and matching stubs was done to a reconfigurable power divider with Single Pole Double Throw (SPDT) switch function. Two designs (Design A and Design B) with different positions of switches and matching stubs were proposed. Rogers RO4350 (er=3.48, h=0.508 mm) was used in this analysis as a substrate material with copper thickness of 0.035 mm. The performance analysis was carried out based on insertion loss, return loss and isolation parameters. The simulated results showed that Design B had a better performance than Design A and was able to work as a reconfigurable power divider with SPDT switch function.
This document analyzes the dimensioning space of a parallel tuned integrated circuit amplifier that was previously designed and implemented. It begins by introducing the circuit topology being analyzed, which includes an output capacitor, bias inductor, and parallel resonator. Equations are then derived to calculate the admittances, load resistance, resonant frequency, and component values based on varying design parameters. Performance contours are shown for both an ideal resistive load and with ideal low-pass and high-pass matching networks. The maximum efficiency increased from 77% to 81% with matching networks, while maximum output power increased from 4.1W to 4.9W.
This document discusses cascaded H-bridge multilevel inverters and their symmetrical and asymmetrical configurations. It begins by introducing two-level and multilevel inverters, noting that multilevel inverters are better suited for high power and voltage applications as they reduce harmonics. There are three main multilevel inverter topologies: neutral-point-clamped, flying capacitors, and cascaded H-bridges. The cascaded H-bridge topology connects H-bridge cells in series to generate stepped voltage waveforms. Symmetrical configurations use equal DC voltages for each cell, while asymmetrical configurations use unequal voltages, allowing more voltage levels with the same number of cells. The document presents simulations of
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
Neuro-Fuzzy Five-level Cascaded Multilevel Inverter for Active Power FilterIDES Editor
This paper presents an investigation of five-Level
Cascaded H-bridge(CHB) inverter as Active Power Filter in
Power System (PS) for compensation of reactive power and
harmonics. The advantages of CHB inverter are low harmonic
distortion, reduced number of switches and suppression of
switching losses. The Active Power Filter helps to improve
the power factor and eliminate the Total Harmonics Distortion
(THD) drawn from a Non-Liner Diode Rectifier Load (NLDRL).
The D-Q reference frame theory is used to generate the
reference compensating currents for Active Power Filter
while Neuro-Fuzzy controller(NFC) is used for capacitor dc
voltage regulation. A CHB Inverter is considered for shunt
compensation of a 11 kV distribution system. Finally a level
shifted PWM (LSPWM) technique adopted to investigate the
performance of CHB Inverter. The results are obtained through
Mat lab / Simulink .
ETDCC: Energy-Efficient Transmission Scheme for Dynamic Climatic Conditions i...TELKOMNIKA JOURNAL
In this paper, an energy-efficient transmission scheme for dynamic climatic conditions (ETDCC)
has been proposed in wireless sensor networks (WSNs). This scheme is based on IEEE802.15.4 standard.
In this method, open-loop and closed-loop feedback systems are used for snowfall variation. An open-loop
system is utilized for snowfall-aware link quality compensation and estimation. However, closed-loop system
aids to split the network into two logical regions, resulting the overhead of total control packets is minimized.
According to link quality changes due to snowfall variation, the transmitting power is decided on the basis of
current number of neighbor nodes and threshold power loss for each region. The simulated results depict
that the proposed scheme with reduced control packets overhead adjusts transmitting power level (Plevel) to
compensate link quality. This scheme based on threshold level is compared with the conventional approach
that comprises the division of regions without threshold level.
10 17sep 8310 10079-1-ed pulse density (edit ari)IAESIJEECS
Switched mode power supply (SMPS) converter is a dc-dc power electronic converter which is used to step up or step down the dc output voltage. A dimmable driver circuit for Light Emitting Diode (LED) lamp for automotive lighting with dimming feature is used in this paper. A flyback converter is used as a driver circuit operated in discontinuous conduction mode to perform dimming control of LEDs. High overall circuit efficiency is achieved by regulating the current through the LED lamps using pulse density modulation scheme. The LED driver circuit design and operating principle is discussed in detail. A gentle current control feature is achieved by pulse density modulation technique. The high performance driver circuit is designed for 25 W LED lamps.
A New Soft-Switched Resonant DC-DC ConverterIDES Editor
This paper presents a new soft-switched resonant
dc-dc converter using a passive snubber circuit. The
proposed converter uses a new zero voltage and zero current
switching (ZVZCS) strategies to get ZVZCS function.
Besides operating at constant frequency, all semiconductor
devices operate at soft-switching without additional voltage
and current stresses. In order to validate the proposed
converter, computer simulations and experimental results
were conducted. The paper indicates the effective converter
operation region of the soft-switching action and its
efficiency improvement results on the basis of experimental
evaluations using laboratory prototype.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Enabling relay selection in non-orthogonal multiple access networks: direct a...TELKOMNIKA JOURNAL
In this paper, we consider downlink non-orthogonal multiple access (NOMA) in which the relay selection (RS) scheme is enabled for cooperative networks. In particular, we investigate impact of the number of relays on system performance in term of outage probability. The main factors affecting on cooperative NOMA performance are fixed power allocations coefficients and the number of relay. This paper also indicate performance gap of the outage probabilities among two users the context of NOMA. To exhibit the exactness of derived formula, we match related results between simulation and analytical methods. Numerical results confirms that cooperative NOMA networks benefit from increasing the number of relay.
Low Complex-Hierarchical Coding Compression Approach for Arial ImagesIDES Editor
Image compression is an extended research area
from a long time. Various compression schemes were
developed for the compression of image in gray scaling and
color image compression. Basically the compression is
focused for lossy or lossless color image compression based
on the need of applications. Where lossy compression are
higher in compression ratio but are observed to be lower in
retrieval accuracy. Various compression techniques such as
JPEG and JPEG-2K architectures are developed to realize
such and method. But with the need in high accuracy
retreivation these techniques[8] are not suitable. To achieve
nearby lossless compression[1] various other coding methods
were suggested like lifting scheme coding. This coding result
in very high retrieval accuracy but gives low compression
ratio. This limitation is a bottleneck in current image
compression architectures. So, there is a need in the
development of a compressing approach where both higher
compression as well as higher retrieval accuracy is obtained.
Treatment of NOx from Diesel Engine Exhaust by Dielectric Barrier Discharge M...IDES Editor
This document summarizes research on using a dielectric barrier discharge method to treat NOx emissions from diesel engine exhaust. Key points:
1) Experiments were conducted using a cross-flow dielectric barrier discharge reactor to treat exhaust from a 3.75 kW diesel generator set. NOx removal was tested at different gas flow rates and voltages.
2) The discharge plasma reactor showed promising results in removing NOx at high flow rates of up to 10 L/min. NO was converted to NO2 and then reduced to N2 via reaction with radicals generated by the plasma.
3) Over 76% removal of NOx was achieved at a specific energy density of 97 J/L and a flow rate of 10 L
Hybrid Particle Swarm Optimization for Multi-objective Reactive Power Optimiz...IDES Editor
This paper proposes a hybrid particle swarm optimization (HPSO) method to solve the multi-objective reactive power dispatch problem of minimizing transmission losses and maximizing voltage stability. The HPSO method expands on PSO and genetic algorithms to handle mixed integer and nonlinear optimization problems with both continuous and discrete control variables. The method is evaluated on the IEEE 30-bus and 57-bus test systems. Results show the HPSO approach improves voltage stability compared to conventional, genetic algorithm, and particle swarm optimization methods.
A Simple Novel Method of Torque Ripple Minimization in Fuel Cell Based PMSM D...IDES Editor
Non-Conventional energy sources are the
promising alternatives for future energy crisis. Fuel cells
are upcoming non-conventional energy sources nowadays.
Fuel cell based PMSM drives are used as Hybrid Electric
Vehicles. PMSM drives are nowadays replacing the
induction motor drives for they have many advantages
such as high speed, high efficiency, high torque to inertia
ratio, high power density etc.,. However the main problem
in PMSM drives is the ripples produced in the torque. Also
if these PMSM’S are used as such for HEV applications,
then the performance of the HEV will not be satisfactory
and the life span of the same will be short. Many methods
have been proposed in literatures for the minimization of
these ripples. In this paper a novel method of reduction of
torque ripples has been proposed. Further the main source
of energy supply is the fuel cells. Hence this method is as a
whole useful for PMSM drives which have their source of
energy as fuel cells. The proposed method is validated by
using MATLAB/SIMULINK. The proposed circuit and a
conventional circuit are simulated and the simulated
results are shown. It has been observed that the proposed
method gives rise to very much minimized torque ripples
than when compared with the conventional circuit.
Automatic Relative Radiometric Normalization for Change Detection of Satellit...IDES Editor
Several relative radiometric normalization (RRN)
techniques have been proposed till date most of which involve
selection of pseudo invariant features whose reflectance are
nearly invariant from image to image and are independent of
seasonal cycles. Extraction of such points is quiet tedious and
human operator has to provide mutual correspondence by
choosing easily recognizable and time invariant points. In
this paper, we intend to propose a new automatic radiometric
normalization technique to select PIFs in panchromatic
images known as Bin-Division Method. For multispectral
images, MAD (Multivariate Alteration Detection) has been
employed for selecting PIFs based on the assumption that
MAD components are invariant to affine transformation. This,
followed by robust linear regression constitutes the whole
automatic radiometric normalization procedure.
This paper presents a frequency domain degraded
image restoration practical method. We call it practical wiener
filter. Using this filter, the value for K parameter of wiener
filter is determined experimentally that is so difficult and
time consuming. Furthermore, there is no any absolute remark
to claim that the obtained images by restoration process are
the best could be possible. In order to find a solution for this
problem, we use genetic algorithm to obtain the best value for
K. Therefore, this paper presents an image restoration method
which employs a Computer Aided Design (CAD) to image
restoration where there is no need to original safe image. It
means that, degraded image is as input and restored one is as
output of CAD. Simulation results confirm that this method
is successful and has executive ability in most applications.
FIR Filter Design using Particle Swarm Optimization with Constriction Factor ...IDES Editor
This paper presents an alternative approach for the
design of linear phase digital low pass FIR filter using Particle
Swarm Optimization with Constriction Factor and Inertia
Weight Approach (PSO-CFIWA). FIR filter design is a multimodal
optimization problem. The conventional gradient based
optimization techniques are not efficient for digital filter
design. Given the filter specification to be realized, PSO
algorithm generates a set of filter coefficients and tries to
meet the ideal frequency characteristic. In this paper, for the
given problem, the realization of the FIR filters of different
order has been performed. The simulation results have been
compared with the well accepted evolutionary algorithm such
as genetic algorithm (GA). The results justify that the proposed
filter design approach using PSO-CFIWA outperforms to that
of GA, not only in the accuracy of the designed filter but also
in the convergence speed and solution quality.
Power System State Estimation - A ReviewIDES Editor
This document provides a review of power system state estimation techniques. It discusses both static and dynamic state estimation algorithms. For static state estimation, it covers weighted least squares, decoupled, and robust estimation methods. Weighted least squares is commonly used but can have numerical instability issues. Decoupled state estimation approximates the gain matrix for faster computation. Robust estimation uses M-estimators and other techniques to handle outliers and bad data. Dynamic state estimation applies Kalman filtering, leapfrog algorithms, and other methods to continuously monitor system states over time.
Artificial Intelligence Technique based Reactive Power Planning Incorporating...IDES Editor
This document summarizes a research paper that proposes using artificial intelligence techniques and FACTS controllers for reactive power planning in real-time power transmission systems. The paper formulates the reactive power planning problem and incorporates flexible AC transmission system (FACTS) devices like static VAR compensators (SVC), thyristor controlled series capacitors (TCSC), and unified power flow controllers (UPFC). Evolutionary algorithms like evolutionary programming (EP) and differential evolution (DE) are applied to find the optimal locations and settings of the FACTS controllers to minimize losses and costs. Simulation results on IEEE 30-bus and 72-bus Indian test systems show that UPFC performs best in reducing losses compared to SVC and TCSC.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJCER, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, research and review articles, IJCER Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathematics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer review journal, indexed journal, research and review articles, engineering journal, www.ijceronline.com, research journals,
yahoo journals, bing journals, International Journal of Computational Engineering Research, Google journals, hard copy of Certificate,
journal of engineering, online Submission
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
1) The document proposes techniques for reducing power consumption in VLSI circuits, including minimizing bus transitions using coding schemes, resistive feedback paths to eliminate glitches, and voltage scaling.
2) A resistive feedback method is developed to eliminate glitches in CMOS circuits which reduces power consumption and improves performance.
3) Simulation results show that the proposed resistive feedback technique is effective at minimizing glitches and reducing unnecessary power dissipation compared to a design without feedback paths.
The strategy is based on an autonomous distributed control
scheme in which the DC bus voltage level is used as an indicator of the power balance in the
microgrid. The autonomous control strategy does not rely on communication links or a
central controller, resulting in reduced costs and enhanced reliability. As part of the control
strategy, an adaptive droop control technique is proposed for PV sources in order to
maximize the utilization of power available from these sources while ensuring acceptable
levels of system voltage regulation
The document discusses transistor modeling for small-signal analysis. It introduces two common transistor models - the hybrid equivalent model and the re model. The re model represents the transistor with a diode and controlled current source. Important small-signal parameters for analysis are also defined, including input impedance Zi, output impedance Zo, voltage gain Av, and current gain Ai. The phase relationship between input and output signals is also addressed.
This document summarizes a research paper on modeling DC-DC converters with high frequencies using state space analysis. The paper presents an approach to modeling that avoids assuming constant current ripples, allowing for a better representation at high frequencies. State space averaging is commonly used to model PWM DC-DC converters but has limitations. The presented approach generalizes state space averaging to account for harmonics' effects, transforming time-varying models into time-invariant linear models. Equations for the state space model of a buck converter are provided both when operating and when turned off, and the average state model is derived. The goal is to improve performance for load and input variations through implicit feedforward compensation.
Comparative Evaluation of Three Phase Three Level Neutral Point Clamped Z-So...NAGARAJARAOS
The Z-impedance network coThree-level Z-source inverters are recent single-stage topological solutions
proposed for buck-boost energy conversion with all favorable advantages of
three-level switching retained. Despite their effectiveness in achieving voltage
buck-boost conversion, existing three-level Z-source inverters use two
impedance networks and two isolated dc sources, which can significantly
increase the overall system cost and require a more complex modulator for
balancing the network inductive voltage boosting. Offering a number of less
costly alternatives, this paper presents the design and control of two threelevel Z-source inverters, whose output voltage can be stepped down or up
using only a single impedance network connected between the dc input source
and either a neutral-point-clamped (NPC) or dc-link cascaded inverter
circuitry.
This paper investigates the carrier based modulation schemes (SPWM and
Modified SVPWM) of three-level three phase Z-source inverters with either
two Z-source networks or single Z-source network connected between the dc
sources and inverter circuitry. With the proper offset added for achieving both
optimized harmonic performance and fundamental output voltage, the
proposed modulation schemes of three-level Z-source inverters can satisfy the
expected boost operation under unbalanced modulation conditions. The
Simulation has been performed through Matlab/Simulink and relative
simulation results with conventional method have been presented to validate
the proposed methodnsists of L and C components connected in an X fashion.
The firing control of the Z-source inverter includes the shoot through states. The Zsource inverter advantageously utilizes the shoot-through state to boost the DC bus
voltage by gating on both the upper and lower switches of a phase leg. Three-level
neutral-point-clamped (NPC) inverters, having many inherent advantages, are
commonly used as the preferred topology for medium voltage ac drives [1], and have
recently been explored for other low-voltage applications including grid-interfacing
power converters and high-speed drive converters [2], [3]. Despite their generally
favorable output performance, NPC inverters are constrained by their ability to
perform only voltage-buck operation with buck-boost energy conversion, usually
achieved by connecting various dc-dc boost converters to the front ends of the dc-ac
inverters. These two-stage solutions are usually more costly and can be harder to
control, since they involve more active and passive components. Offering a singlestage solution, [4], [5] propose the buck-boost Z-source NPC inverter, whose
topology is illustrated in Fig. 1 (can be viewed as an extension from the two-level Zsource inverter proposed in [6]).
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
This document summarizes simulation techniques for power integrity in FPGAs using S-parameter models. It discusses power distribution networks and the need to simulate their frequency-dependent self-impedance profiles. Key concepts covered include series and parallel resonance, frequency components of electrical signals, and using S-parameter models of decoupling capacitors. The document provides an example simulation in Agilent ADS comparing cases with and without PCB decoupling capacitors for an Xilinx 7-series FPGA. Measurement results from an oscilloscope show equivalent jitter performance between the two cases.
The document proposes a Power Controlled Dual Channel (PCDC) medium access protocol for wireless ad hoc networks that aims to increase channel utilization and network throughput while decreasing energy consumption. The protocol builds on IEEE 802.11 by allowing simultaneous transmissions in a neighborhood through dynamic power control based on directional and channel gain information from overheard RTS and CTS packets. Simulation results show the proposed protocol achieves significant increases in channel utilization and end-to-end throughput as well as significant decreases in total energy consumption compared to IEEE 802.11.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
This document presents a new method for analyzing transient voltage distributions in transformer windings. It models the electric, magnetic, and current fields as equivalent circuits consisting of interconnected electric and magnetic networks.
The electric network models the voltage distribution within each winding section using resistances and emfs derived from the geometry. The magnetic network models the flux paths using reluctances, which is then converted to an equivalent inductance network. Capacitances model the electric fields within and between sections.
The electric, magnetic, and capacitance networks are coupled through ideal transformers to form a single overall mathematical model without mutual inductances. The model can analyze transient voltages inside the windings resulting from any applied terminal overvoltage waveform. An example application
Modelling of Crosstalk and Delay for Distributed RLCG On-Chip Interconnects F...IDES Editor
In order to accurately model high frequency affects,
inductance has been taken into consideration. No longer can
interconnects be treated as mere delays or lumped RC networks.
In that frequency range, the most accurate simulation model for
on-chip VLSI interconnects is the distributed RLC model.
Unfortunately, this model has many limitations at much higher
of operating frequency used in today’s VLSI design. The reduction
in cross-sectional dimension leads to more tightly couple
interconnects and therefore, a higher probability of unwanted
crosstalk interference. This can lead to inaccurate simulations
if not modelled properly. At even higher frequency, the aggressor
net carries a signal that couples to the victim net through the
parasitic capacitances. To determine the effects that this crosstalk
will have on circuit operation, the resulting delays and logic
levels for the victim nets must be computed. This paper proposes
a difference model approach to derive crosstalk and delay in the
transform domain. A closed form solution for crosstalk and delay
is obtained by incorporating initial conditions using difference
model approach for distributed RLCG interconnects. The
simulation is performed in 0.18μm technology node and an error
of less than 1% has been achieved with the proposed model when
compared with SPICE.
Small Signal Modelling of a Buck Converter using State Space Averaging for Ma...paperpublications3
This document presents a small-signal model of a buck converter operating in continuous conduction mode (CCM) with a magnetic load. It uses state-space averaging methodology to derive dynamic equations for the converter. The model is linearized around an operating point to obtain a linear time-invariant small-signal model. Transfer functions are derived in the s-domain to characterize the frequency response of the power stage dynamics. The model is validated through simulations in MATLAB using illustrative system parameters. It can be used to design robust closed-loop controllers for DC-DC buck regulators.
The high penetration of power electronic based distributed energy resources (DERs) has increased the importance and attention given to voltage security of distribution systems. Voltage control in the electrical power system is critical for a proper operating condition. Therefore, distribution systems must have the ability to maintain a secure voltage profile. Using inverters for Volt/VAR control (VVC) can provide a faster response for voltage regulation than traditional voltage regulation devices, such as transformer load tap changers and voltage regulators. The primary objective of this paper is to demonstrate how smart inverters can be used to eliminate the voltage deviation by solving a mixed-integer quadratic program to determine the amount of reactive power that should be injected or absorbed at the appropriate nodes. The proposed method incorporates capacitor banks connected to the network and determines whether to turn on or off the capacitor bank for voltage regulation. These processes will be demonstrated in several cases that are focused on mitigating voltage-dips and swells.
The high penetration of power electronic based distributed energy resources (DERs) has increased the importance and attention given to voltage security of distribution systems. Voltage control in the electrical power system is critical for a proper operating condition. Therefore, distribution systems must have the ability to maintain a secure voltage profile. Using inverters for Volt/VAR control (VVC) can provide a faster response for voltage regulation than traditional voltage regulation devices, such as transformer load tap changers and voltage regulators. The primary objective of this paper is to demonstrate how smart inverters can be used to eliminate the voltage deviation by solving a mixed-integer quadratic program to determine the amount of reactive power that should be injected or absorbed at the appropriate nodes. The proposed method incorporates capacitor banks connected to the network and determines whether to turn on or off the capacitor bank for voltage regulation. These processes will be demonstrated in several cases that are focused on mitigating voltage-dips and swells.
State-space averaged modeling and transfer function derivation of DC-DC boost...TELKOMNIKA JOURNAL
This paper presents dynamic analysis of a boost type DC-DC converter for high-brightness LED (HBLED) driving applications. The steady state operation in presence of all system parasitics has been discussed for continuous conduction mode (CCM). The state-space averaging, energy conservation principle and standard linearization are used to derive ac small signal control to inductor current open-loop transfer function of the converter. The derived transfer function can be further used in designing a robust feed-back control network for the system. In the end frequency and transient responses of the derived transfer function are obtained for a given set of component values, hence to provide a useful guide for control design engineers.
This document presents a new mesh analytical method for symbolic simulation of linear RLC circuits in the frequency domain. The method formulates the circuit equations as a set of mesh equations that account for both the steady-state impedances of the circuit elements as well as the initialization effects of non-zero initial conditions in the capacitors and inductors. It derives the mesh equations for a simple three-node, three-mesh example circuit and shows that the circuit equations can be expressed in matrix form with impedance matrices representing the steady-state and initialization impedances. The method aims to provide a simple yet robust way to simulate transient responses of linear circuits symbolically in the frequency domain.
Comparative Evaluation of Generalized Multicell Impedance Source Inverter for...IJPEDS-IAES
Voltage-Source Inverter is limited by its only voltage step-down operation. In adding with extra boosting the flexibility is kept active for the number of semiconductors which is unchanged, voltage-type Z-source inverter was earlier proposed. This new class of inverter is generally less sensitive to electromagnetic noises. However, their boosting capabilities are anyhow less with high component stresses and poorer spectral performances caused by low modulation index ratios. Their boosting gains are, therefore, restricted in practice. To overcome these we use the generalized switched-inductor Z- source inverter is proposed, By comparing with PWM technique and SPWM technique, whose extra boosting abilities and other advantages have been verified in simulation analysis and experiment.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Due to increasing complexity, space and cost of communication network, the Electric Power Network has been considered a great option for the solution of all problems. Power line communications (PLC) term stands for the technologies for the data communication over the electrical power supply network. Existing power system is not designed for having data transfer. In this paper we have developed a simulation model of power-line for low voltage distribution network in home. Impulse response of the channel is generated in order to characterize the behavior of power line channel for high speed data communication purpose. To represent Multi-branch network mathematically, ABCD matrix parameters are used. Load mismatching is experimented on three parameters multiple loading, multi branch and different cable length and analysis is presented of its effect on impulse response. All the simulation work has been done using MATLAB.
Similar to An Explicit Approach for Dynamic Power Evaluation for Deep submicron Global Interconnects with Current Mode Signaling Technique (20)
Design and Performance Analysis of Genetic based PID-PSS with SVC in a Multi-...IDES Editor
Damping of power system oscillations with the help
of proposed optimal Proportional Integral Derivative Power
System Stabilizer (PID-PSS) and Static Var Compensator
(SVC)-based controllers are thoroughly investigated in this
paper. This study presents robust tuning of PID-PSS and
SVC-based controllers using Genetic Algorithms (GA) in
multi machine power systems by considering detailed model
of the generators (model 1.1). The effectiveness of FACTSbased
controllers in general and SVC-based controller in
particular depends upon their proper location. Modal
controllability and observability are used to locate SVC–based
controller. The performance of the proposed controllers is
compared with conventional lead-lag power system stabilizer
(CPSS) and demonstrated on 10 machines, 39 bus New England
test system. Simulation studies show that the proposed genetic
based PID-PSS with SVC based controller provides better
performance.
Optimal Placement of DG for Loss Reduction and Voltage Sag Mitigation in Radi...IDES Editor
This paper presents the need to operate the power
system economically and with optimum levels of voltages has
further led to an increase in interest in Distributed
Generation. In order to reduce the power losses and to improve
the voltage in the distribution system, distributed generators
(DGs) are connected to load bus. To reduce the total power
losses in the system, the most important process is to identify
the proper location for fixing and sizing of DGs. It presents a
new methodology using a new population based meta heuristic
approach namely Artificial Bee Colony algorithm(ABC) for
the placement of Distributed Generators(DG) in the radial
distribution systems to reduce the real power losses and to
improve the voltage profile, voltage sag mitigation. The power
loss reduction is important factor for utility companies because
it is directly proportional to the company benefits in a
competitive electricity market, while reaching the better power
quality standards is too important as it has vital effect on
customer orientation. In this paper an ABC algorithm is
developed to gain these goals all together. In order to evaluate
sag mitigation capability of the proposed algorithm, voltage
in voltage sensitive buses is investigated. An existing 20KV
network has been chosen as test network and results are
compared with the proposed method in the radial distribution
system.
Line Losses in the 14-Bus Power System Network using UPFCIDES Editor
Controlling power flow in modern power systems
can be made more flexible by the use of recent developments
in power electronic and computing control technology. The
Unified Power Flow Controller (UPFC) is a Flexible AC
transmission system (FACTS) device that can control all the
three system variables namely line reactance, magnitude and
phase angle difference of voltage across the line. The UPFC
provides a promising means to control power flow in modern
power systems. Essentially the performance depends on proper
control setting achievable through a power flow analysis
program. This paper presents a reliable method to meet the
requirements by developing a Newton-Raphson based load
flow calculation through which control settings of UPFC can
be determined for the pre-specified power flow between the
lines. The proposed method keeps Newton-Raphson Load Flow
(NRLF) algorithm intact and needs (little modification in the
Jacobian matrix). A MATLAB program has been developed to
calculate the control settings of UPFC and the power flow
between the lines after the load flow is converged. Case studies
have been performed on IEEE 5-bus system and 14-bus system
to show that the proposed method is effective. These studies
indicate that the method maintains the basic NRLF properties
such as fast computational speed, high degree of accuracy and
good convergence rate.
Study of Structural Behaviour of Gravity Dam with Various Features of Gallery...IDES Editor
The size and shape of opening in dam causes the
stress concentration, it also causes the stress variation in the
rest of the dam cross section. The gravity method of the analysis
does not consider the size of opening and the elastic property
of dam material. Thus the objective of study is comprises of
the Finite Element Method which considers the size of
opening, elastic property of material, and stress distribution
because of geometric discontinuity in cross section of dam.
Stress concentration inside the dam increases with the opening
in dam which results in the failure of dam. Hence it is
necessary to analyses large opening inside the dam. By making
the percentage area of opening constant and varying size and
shape of opening the analysis is carried out. For this purpose
a section of Koyna Dam is considered. Dam is defined as a
plane strain element in FEM, based on geometry and loading
condition. Thus this available information specified our path
of approach to carry out 2D plane strain analysis. The results
obtained are then compared mutually to get most efficient
way of providing large opening in the gravity dam.
Assessing Uncertainty of Pushover Analysis to Geometric ModelingIDES Editor
Pushover Analysis a popular tool for seismic
performance evaluation of existing and new structures and is
nonlinear Static procedure where in monotonically increasing
loads are applied to the structure till the structure is unable
to resist the further load .During the analysis, whatever the
strength of concrete and steel is adopted for analysis of
structure may not be the same when real structure is
constructed and the pushover analysis results are very sensitive
to material model adopted, geometric model adopted, location
of plastic hinges and in general to procedure followed by the
analyzer. In this paper attempt has been made to assess
uncertainty in pushover analysis results by considering user
defined hinges and frame modeled as bare frame and frame
with slab modeled as rigid diaphragm and results compared
with experimental observations. Uncertain parameters
considered includes the strength of concrete, strength of steel
and cover to the reinforcement which are randomly generated
and incorporated into the analysis. The results are then
compared with experimental observations.
Secure Multi-Party Negotiation: An Analysis for Electronic Payments in Mobile...IDES Editor
This document summarizes and analyzes secure multi-party negotiation protocols for electronic payments in mobile computing. It presents a framework for secure multi-party decision protocols using lightweight implementations. The main focus is on synchronizing security features to avoid agreement manipulation and reduce user traffic. The paper describes negotiation between an auctioneer and bidders, showing multiparty security is better than existing systems. It analyzes the performance of encryption algorithms like ECC, XTR, and RSA for use in the multiparty negotiation protocols.
Selfish Node Isolation & Incentivation using Progressive ThresholdsIDES Editor
The problems associated with selfish nodes in
MANET are addressed by a collaborative watchdog approach
which reduces the detection time for selfish nodes thereby
improves the performance and accuracy of watchdogs[1]. In
the related works they make use of credit based systems, reputation
based mechanisms, pathrater and watchdog mechanism
to detect such selfish nodes. In this paper we follow an approach
of collaborative watchdog which reduces the detection
time for selfish nodes and also involves the removal of such
selfish nodes based on some progressively assessed thresholds.
The threshold gives the nodes a chance to stop misbehaving
before it is permanently deleted from the network.
The node passes through several isolation processes before it
is permanently removed. Another version of AODV protocol
is used here which allows the simulation of selfish nodes in
NS2 by adding or modifying log files in the protocol.
Various OSI Layer Attacks and Countermeasure to Enhance the Performance of WS...IDES Editor
Wireless sensor networks are networks having non
wired infrastructure and dynamic topology. In OSI model each
layer is prone to various attacks, which halts the performance
of a network .In this paper several attacks on four layers of
OSI model are discussed and security mechanism is described
to prevent attack in network layer i.e wormhole attack. In
Wormhole attack two or more malicious nodes makes a covert
channel which attracts the traffic towards itself by depicting a
low latency link and then start dropping and replaying packets
in the multi-path route. This paper proposes promiscuous mode
method to detect and isolate the malicious node during
wormhole attack by using Ad-hoc on demand distance vector
routing protocol (AODV) with omnidirectional antenna. The
methodology implemented notifies that the nodes which are
not participating in multi-path routing generates an alarm
message during delay and then detects and isolate the
malicious node from network. We also notice that not only
the same kind of attacks but also the same kind of
countermeasures can appear in multiple layer. For example,
misbehavior detection techniques can be applied to almost all
the layers we discussed.
Responsive Parameter based an AntiWorm Approach to Prevent Wormhole Attack in...IDES Editor
The recent advancements in the wireless technology
and their wide-spread deployment have made remarkable
enhancements in efficiency in the corporate and industrial
and Military sectors The increasing popularity and usage of
wireless technology is creating a need for more secure wireless
Ad hoc networks. This paper aims researched and developed
a new protocol that prevents wormhole attacks on a ad hoc
network. A few existing protocols detect wormhole attacks but
they require highly specialized equipment not found on most
wireless devices. This paper aims to develop a defense against
wormhole attacks as an Anti-worm protocol which is based on
responsive parameters, that does not require as a significant
amount of specialized equipment, trick clock synchronization,
no GPS dependencies.
Cloud Security and Data Integrity with Client Accountability FrameworkIDES Editor
This document summarizes a proposed cloud security and data integrity framework that provides client accountability. The framework aims to address issues like lack of user control over cloud data, need for data transparency and tracking, and ensuring data integrity. It proposes using JAR (Java Archive) files for data sharing due to benefits like portability. The framework incorporates client-side verification using MD5 hashing, digital signature-based authentication of JAR files, and use of HMAC to ensure data integrity. It also uses password-based encryption of log files to keep them tamper-proof. The framework is intended to provide both accountability and security for data sharing in cloud environments.
Genetic Algorithm based Layered Detection and Defense of HTTP BotnetIDES Editor
A System state in HTTP botnet uses HTTP protocol
for the creation of chain of Botnets thereby compromising
other systems. By using HTTP protocol and port number 80,
attacks can not only be hidden but also pass through the
firewall without being detected. The DPR based detection
leads to better analysis of botnet attacks [3]. However, it
provides only probabilistic detection of the attacker and also
time consuming and error prone. This paper proposes a Genetic
algorithm based layered approach for detecting as well as
preventing botnet attacks. The paper reviews p2p firewall
implementation which forms the basis of filtering.
Performance evaluation is done based on precision, F-value
and probability. Layered approach reduces the computation
and overall time requirement [7]. Genetic algorithm promises
a low false positive rate.
Enhancing Data Storage Security in Cloud Computing Through SteganographyIDES Editor
This document summarizes a research paper that proposes a method for enhancing data security in cloud computing through steganography. The method hides user data in digital images stored on cloud servers. When data needs to be accessed, it is extracted from the images. The document outlines the cloud architecture and security issues addressed. It then describes the proposed system architecture, security model, and data storage and retrieval process. Data is partitioned and hidden in multiple images to improve security. The goal is to prevent unauthorized access to user data stored on cloud servers.
The main tasks of a Wireless Sensor Network
(WSN) are data collection from its nodes and communication
of this data to the base station (BS). The protocols used for
communication among the WSN nodes and between the WSN
and the BS, must consider the resource constraints of nodes,
battery energy, computational capabilities and memory. The
WSN applications involve unattended operation of the network
over an extended period of time. In order to extend the lifetime
of a WSN, efficient routing protocols need to be adopted. The
proposed low power routing protocol based on tree-based
network structure reliably forwards the measured data towards
the BS using TDMA. An energy consumption analysis of the
WSN making use of this protocol is also carried out. It is
found that the network is energy efficient with an average
duty cycle of 0:7% for the WSN nodes. The OmNET++
simulation platform along with MiXiM framework is made
use of.
Permutation of Pixels within the Shares of Visual Cryptography using KBRP for...IDES Editor
The security of authentication of internet based
co-banking services should not be susceptible to high risks.
The passwords are highly vulnerable to virus attacks due to
the lack of high end embedding of security methods. In order
for the passwords to be more secure, people are generally
compelled to select jumbled up character based passwords
which are not only less memorable but are also equally prone
to insecurity. Multiple use of distributed shares has been
studied to solve the problem of authentication by algorithms
based on thresholding of pixels in image processing and visual
cryptography concepts where the subset of shares is considered
for the recovery of the original image for authentication using
correlation function[1][2].The main disadvantage in the above
study is the plain storage of shares and also one of the shares
is being supplied to the customer, which will lead to the
possibility of misuse by a third party. This paper proposes a
technique for scrambling of pixels by key based random
permutation (KBRP) within the shares before the
authentication has been attempted. Total number of shares to
be created is dependent on the multiplicity of ownership of
the account. By this method the problem of uncertainty among
the customers with regard to security, storage, retrieval of
holding of half of the shares is minimized.
This paper presents a trifocal Rotman Lens Design
approach. The effects of focal ratio and element spacing on
the performance of Rotman Lens are described. A three beam
prototype feeding 4 element antenna array working in L-band
has been simulated using RLD v1.7 software. Simulated
results show that the simulated lens has a return loss of –
12.4dB at 1.8GHz. Beam to array port phase error variation
with change in the focal ratio and element spacing has also
been investigated.
Band Clustering for the Lossless Compression of AVIRIS Hyperspectral ImagesIDES Editor
Hyperspectral images can be efficiently compressed
through a linear predictive model, as for example the one
used in the SLSQ algorithm. In this paper we exploit this
predictive model on the AVIRIS images by individuating,
through an off-line approach, a common subset of bands, which
are not spectrally related with any other bands. These bands
are not useful as prediction reference for the SLSQ 3-D
predictive model and we need to encode them via other
prediction strategies which consider only spatial correlation.
We have obtained this subset by clustering the AVIRIS bands
via the clustering by compression approach. The main result
of this paper is the list of the bands, not related with the
others, for AVIRIS images. The clustering trees obtained for
AVIRIS and the relationship among bands they depict is also
an interesting starting point for future research.
Microelectronic Circuit Analogous to Hydrogen Bonding Network in Active Site ...IDES Editor
A microelectronic circuit of block-elements
functionally analogous to two hydrogen bonding networks is
investigated. The hydrogen bonding networks are extracted
from â-lactamase protein and are formed in its active site.
Each hydrogen bond of the network is described in equivalent
electrical circuit by three or four-terminal block-element.
Each block-element is coded in Matlab. Static and dynamic
analyses are performed. The resultant microelectronic circuit
analogous to the hydrogen bonding network operates as
current mirror, sine pulse source, triangular pulse source as
well as signal modulator.
Texture Unit based Monocular Real-world Scene Classification using SOM and KN...IDES Editor
In this paper a method is proposed to discriminate
real world scenes in to natural and manmade scenes of similar
depth. Global-roughness of a scene image varies as a function
of image-depth. Increase in image depth leads to increase in
roughness in manmade scenes; on the contrary natural scenes
exhibit smooth behavior at higher image depth. This particular
arrangement of pixels in scene structure can be well explained
by local texture information in a pixel and its neighborhood.
Our proposed method analyses local texture information of a
scene image using texture unit matrix. For final classification
we have used both supervised and unsupervised learning using
K-Nearest Neighbor classifier (KNN) and Self Organizing
Map (SOM) respectively. This technique is useful for online
classification due to very less computational complexity.
Mental Stress Evaluation using an Adaptive ModelIDES Editor
Chronic stress can have serious physiological and
psychological impact on an individual’s health. Wearable
sensor systems can enable physicians to monitor physiological
variables and observe the impact of stress over long periods of
time. To correlate an individual’s physiological measures with
their perception of psychological stress, it is essential that
the stress monitoring system accounts for individual
differences in self-reporting. Self-reporting of stress is highly
subjective as it is dependent on an individual’s perception of
stress and thus prone to errors. In addition, subjects can tailor
their answers to present their behavior more favorably. In
this paper we present an adaptive model which allows recorded
stress scores and physiological variables to be tuned to remove
biases in self-reported scores. The model takes an individual’s
physiological and psychological responses into account and
adapts to the user’s variations. Using our adaptive model,
physiological data is mapped efficiently to perceived stress
levels with 90% accuracy.
Genetic Algorithm based Mosaic Image Steganography for Enhanced SecurityIDES Editor
The document summarizes previous work on mosaic image steganography and proposes using genetic algorithms and key-based random permutation to improve the technique. Mosaic image steganography hides a secret image by dividing it into fragments and embedding the fragments into a target image to create a mosaic. Previous methods required a large database of images or allowed only arbitrary target image selection. The proposed method uses genetic algorithms to generate a mapping sequence for embedding tile images without a database, improving clarity and reducing computational complexity. It also applies a key-based random permutation to the mapping sequence for enhanced security and robustness. The mosaic image can be recovered using the same key and mapping sequence, making it a lossless data hiding method.
TrustArc Webinar - 2024 Global Privacy SurveyTrustArc
How does your privacy program stack up against your peers? What challenges are privacy teams tackling and prioritizing in 2024?
In the fifth annual Global Privacy Benchmarks Survey, we asked over 1,800 global privacy professionals and business executives to share their perspectives on the current state of privacy inside and outside of their organizations. This year’s report focused on emerging areas of importance for privacy and compliance professionals, including considerations and implications of Artificial Intelligence (AI) technologies, building brand trust, and different approaches for achieving higher privacy competence scores.
See how organizational priorities and strategic approaches to data security and privacy are evolving around the globe.
This webinar will review:
- The top 10 privacy insights from the fifth annual Global Privacy Benchmarks Survey
- The top challenges for privacy leaders, practitioners, and organizations in 2024
- Key themes to consider in developing and maintaining your privacy program
Have you ever been confused by the myriad of choices offered by AWS for hosting a website or an API?
Lambda, Elastic Beanstalk, Lightsail, Amplify, S3 (and more!) can each host websites + APIs. But which one should we choose?
Which one is cheapest? Which one is fastest? Which one will scale to meet our needs?
Join me in this session as we dive into each AWS hosting service to determine which one is best for your scenario and explain why!
Trusted Execution Environment for Decentralized Process MiningLucaBarbaro3
Presentation of the paper "Trusted Execution Environment for Decentralized Process Mining" given during the CAiSE 2024 Conference in Cyprus on June 7, 2024.
Main news related to the CCS TSI 2023 (2023/1695)Jakub Marek
An English 🇬🇧 translation of a presentation to the speech I gave about the main changes brought by CCS TSI 2023 at the biggest Czech conference on Communications and signalling systems on Railways, which was held in Clarion Hotel Olomouc from 7th to 9th November 2023 (konferenceszt.cz). Attended by around 500 participants and 200 on-line followers.
The original Czech 🇨🇿 version of the presentation can be found here: https://www.slideshare.net/slideshow/hlavni-novinky-souvisejici-s-ccs-tsi-2023-2023-1695/269688092 .
The videorecording (in Czech) from the presentation is available here: https://youtu.be/WzjJWm4IyPk?si=SImb06tuXGb30BEH .
Nunit vs XUnit vs MSTest Differences Between These Unit Testing Frameworks.pdfflufftailshop
When it comes to unit testing in the .NET ecosystem, developers have a wide range of options available. Among the most popular choices are NUnit, XUnit, and MSTest. These unit testing frameworks provide essential tools and features to help ensure the quality and reliability of code. However, understanding the differences between these frameworks is crucial for selecting the most suitable one for your projects.
This presentation provides valuable insights into effective cost-saving techniques on AWS. Learn how to optimize your AWS resources by rightsizing, increasing elasticity, picking the right storage class, and choosing the best pricing model. Additionally, discover essential governance mechanisms to ensure continuous cost efficiency. Whether you are new to AWS or an experienced user, this presentation provides clear and practical tips to help you reduce your cloud costs and get the most out of your budget.
5th LF Energy Power Grid Model Meet-up SlidesDanBrown980551
5th Power Grid Model Meet-up
It is with great pleasure that we extend to you an invitation to the 5th Power Grid Model Meet-up, scheduled for 6th June 2024. This event will adopt a hybrid format, allowing participants to join us either through an online Mircosoft Teams session or in person at TU/e located at Den Dolech 2, Eindhoven, Netherlands. The meet-up will be hosted by Eindhoven University of Technology (TU/e), a research university specializing in engineering science & technology.
Power Grid Model
The global energy transition is placing new and unprecedented demands on Distribution System Operators (DSOs). Alongside upgrades to grid capacity, processes such as digitization, capacity optimization, and congestion management are becoming vital for delivering reliable services.
Power Grid Model is an open source project from Linux Foundation Energy and provides a calculation engine that is increasingly essential for DSOs. It offers a standards-based foundation enabling real-time power systems analysis, simulations of electrical power grids, and sophisticated what-if analysis. In addition, it enables in-depth studies and analysis of the electrical power grid’s behavior and performance. This comprehensive model incorporates essential factors such as power generation capacity, electrical losses, voltage levels, power flows, and system stability.
Power Grid Model is currently being applied in a wide variety of use cases, including grid planning, expansion, reliability, and congestion studies. It can also help in analyzing the impact of renewable energy integration, assessing the effects of disturbances or faults, and developing strategies for grid control and optimization.
What to expect
For the upcoming meetup we are organizing, we have an exciting lineup of activities planned:
-Insightful presentations covering two practical applications of the Power Grid Model.
-An update on the latest advancements in Power Grid -Model technology during the first and second quarters of 2024.
-An interactive brainstorming session to discuss and propose new feature requests.
-An opportunity to connect with fellow Power Grid Model enthusiasts and users.
Digital Marketing Trends in 2024 | Guide for Staying AheadWask
https://www.wask.co/ebooks/digital-marketing-trends-in-2024
Feeling lost in the digital marketing whirlwind of 2024? Technology is changing, consumer habits are evolving, and staying ahead of the curve feels like a never-ending pursuit. This e-book is your compass. Dive into actionable insights to handle the complexities of modern marketing. From hyper-personalization to the power of user-generated content, learn how to build long-term relationships with your audience and unlock the secrets to success in the ever-shifting digital landscape.
Ivanti’s Patch Tuesday breakdown goes beyond patching your applications and brings you the intelligence and guidance needed to prioritize where to focus your attention first. Catch early analysis on our Ivanti blog, then join industry expert Chris Goettl for the Patch Tuesday Webinar Event. There we’ll do a deep dive into each of the bulletins and give guidance on the risks associated with the newly-identified vulnerabilities.
Dive into the realm of operating systems (OS) with Pravash Chandra Das, a seasoned Digital Forensic Analyst, as your guide. 🚀 This comprehensive presentation illuminates the core concepts, types, and evolution of OS, essential for understanding modern computing landscapes.
Beginning with the foundational definition, Das clarifies the pivotal role of OS as system software orchestrating hardware resources, software applications, and user interactions. Through succinct descriptions, he delineates the diverse types of OS, from single-user, single-task environments like early MS-DOS iterations, to multi-user, multi-tasking systems exemplified by modern Linux distributions.
Crucial components like the kernel and shell are dissected, highlighting their indispensable functions in resource management and user interface interaction. Das elucidates how the kernel acts as the central nervous system, orchestrating process scheduling, memory allocation, and device management. Meanwhile, the shell serves as the gateway for user commands, bridging the gap between human input and machine execution. 💻
The narrative then shifts to a captivating exploration of prominent desktop OSs, Windows, macOS, and Linux. Windows, with its globally ubiquitous presence and user-friendly interface, emerges as a cornerstone in personal computing history. macOS, lauded for its sleek design and seamless integration with Apple's ecosystem, stands as a beacon of stability and creativity. Linux, an open-source marvel, offers unparalleled flexibility and security, revolutionizing the computing landscape. 🖥️
Moving to the realm of mobile devices, Das unravels the dominance of Android and iOS. Android's open-source ethos fosters a vibrant ecosystem of customization and innovation, while iOS boasts a seamless user experience and robust security infrastructure. Meanwhile, discontinued platforms like Symbian and Palm OS evoke nostalgia for their pioneering roles in the smartphone revolution.
The journey concludes with a reflection on the ever-evolving landscape of OS, underscored by the emergence of real-time operating systems (RTOS) and the persistent quest for innovation and efficiency. As technology continues to shape our world, understanding the foundations and evolution of operating systems remains paramount. Join Pravash Chandra Das on this illuminating journey through the heart of computing. 🌟
Monitoring and Managing Anomaly Detection on OpenShift.pdfTosin Akinosho
Monitoring and Managing Anomaly Detection on OpenShift
Overview
Dive into the world of anomaly detection on edge devices with our comprehensive hands-on tutorial. This SlideShare presentation will guide you through the entire process, from data collection and model training to edge deployment and real-time monitoring. Perfect for those looking to implement robust anomaly detection systems on resource-constrained IoT/edge devices.
Key Topics Covered
1. Introduction to Anomaly Detection
- Understand the fundamentals of anomaly detection and its importance in identifying unusual behavior or failures in systems.
2. Understanding Edge (IoT)
- Learn about edge computing and IoT, and how they enable real-time data processing and decision-making at the source.
3. What is ArgoCD?
- Discover ArgoCD, a declarative, GitOps continuous delivery tool for Kubernetes, and its role in deploying applications on edge devices.
4. Deployment Using ArgoCD for Edge Devices
- Step-by-step guide on deploying anomaly detection models on edge devices using ArgoCD.
5. Introduction to Apache Kafka and S3
- Explore Apache Kafka for real-time data streaming and Amazon S3 for scalable storage solutions.
6. Viewing Kafka Messages in the Data Lake
- Learn how to view and analyze Kafka messages stored in a data lake for better insights.
7. What is Prometheus?
- Get to know Prometheus, an open-source monitoring and alerting toolkit, and its application in monitoring edge devices.
8. Monitoring Application Metrics with Prometheus
- Detailed instructions on setting up Prometheus to monitor the performance and health of your anomaly detection system.
9. What is Camel K?
- Introduction to Camel K, a lightweight integration framework built on Apache Camel, designed for Kubernetes.
10. Configuring Camel K Integrations for Data Pipelines
- Learn how to configure Camel K for seamless data pipeline integrations in your anomaly detection workflow.
11. What is a Jupyter Notebook?
- Overview of Jupyter Notebooks, an open-source web application for creating and sharing documents with live code, equations, visualizations, and narrative text.
12. Jupyter Notebooks with Code Examples
- Hands-on examples and code snippets in Jupyter Notebooks to help you implement and test anomaly detection models.
Fueling AI with Great Data with Airbyte WebinarZilliz
This talk will focus on how to collect data from a variety of sources, leveraging this data for RAG and other GenAI use cases, and finally charting your course to productionalization.
Generating privacy-protected synthetic data using Secludy and MilvusZilliz
During this demo, the founders of Secludy will demonstrate how their system utilizes Milvus to store and manipulate embeddings for generating privacy-protected synthetic data. Their approach not only maintains the confidentiality of the original data but also enhances the utility and scalability of LLMs under privacy constraints. Attendees, including machine learning engineers, data scientists, and data managers, will witness first-hand how Secludy's integration with Milvus empowers organizations to harness the power of LLMs securely and efficiently.