Reconfigurable floating impedance using single digitally programmable cmos dvcc

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Reconfigurable floating impedance using single digitally programmable cmos dvcc

  1. 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN INTERNATIONAL JOURNAL OF ELECTRONICS AND 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMECOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 2, March – April, 2013, pp. 31-40 IJECET© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI) ©IAEMEwww.jifactor.com RECONFIGURABLE FLOATING IMPEDANCE USING SINGLE DIGITALLY PROGRAMMABLE CMOS DVCC Iqbal A. Khan1, Ahmed M. Nahhas2 1 (Department of Electrical Engineering, Faculty of Engineering and Islamic Architecture, Umm Al Qura University, Makkah, Saudi Arabia 2 (Department of Electrical Engineering, Faculty of Engineering and Islamic Architecture, Umm Al Qura University, Makkah, Saudi Arabia ABSTRACT A general scheme is presented to convert any grounded impedance into reconfigurable floating impedance using single digitally programmable CMOS differential voltage current conveyor without any component matching constraint. The reconfigurable floating impedance module is suitable for field programmable analog array. To verify the scheme a reconfigurable floating resistor and a reconfigurable floating capacitor are designed and simulated using PSPICE and the results thus obtained justify the theory. Keywords: Current conveyors, DVCC, Impedance simulators, Filters I. INTRODUCTION In recent years the current conveyors have been dominating in the area of analog signal processing due to their functional versatility in addition to higher signal bandwidth and greater linearity. As a result vast variety of linear and nonlinear analog signal processing applications are reported in technical literature [1-38]. The introduction of digital control to the current conveyor (CCII) has eased the on chip control of continuous time systems with high resolution capability and reconfigurability [17-28]. Such reconfigurable modules are suitable for realizing the field programmable analog array [38-41]. In analog signal processing applications the component simulators play an important role in realizing integrable and low sensitive analog modules. As a result several grounded and floating component simulators are reported in technical literature employing current conveyors as well [29-37]. However, many of them use a complex circuitry and component matching constraints. The component matching constraints increase the system parameter sensitivity to the unacceptable level [35]. 31
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME In this paper a scheme is presented to convert any grounded impedance into digitally programmable floating impedance (DPFI) using single CMOS digitally programmable differential voltage current conveyor (DPDVCC) without any component matching constraint. All the DPFI based simulated floating components can be digitally controlled and possess low sensitivity. To verify the proposed theory the DPFI is used to simulate a digitally programmable floating resistor (DPFR) and digitally programmable floating capacitor (DPFC). The simulated DPFR and DPFC respectively have been used to realize the prototype first order low pass filter (LPF) and high pass filter (HPF). These the DPFI based LPF and HPF are designed and verified using PSPICE and the results thus obtained justify the theory.II. THE CMOS DPDVCC The digitally programmable differential voltage current conveyor (DPDVCC) symbol is shown in figure 1(a) and its CMOS implementation with 4-bit current summing network (CSN) at port-Z is shown in figure 1(b) [37]. Figure 1(a): Symbol for DPDVCC Figure 1(b): The CMOS implementation of a DPDVCC with 4-bit CSN at Z+ and Z-terminals [37] 32
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME The transfer matrix of the DPDVCC can be expressed as IY1  0 0 0 0 0 V  I     Y1   Y 2  0 0 0 0 0 V  Y2  VX  = 1 − 1 0 0 0  I X      ................................................(1) I Z +  0 0 N m 0 0 VZ +    I Z −  0 0 − N m 0 0 VZ −      Thus the port voltages and currents for the DPDVCC can be expressed as IY 1 = IY 2 = 0 VX = VY 1 − VY 2 IZ+ = +N mI X .......................................................(2) I Z − = −N m I X where, N is an n-bit digital control word. The power integer ‘m = 1’ for current summing network (CSN) at port-Z and m = -1 for the CSN at port-X of the DPDVCC [22-28].III. THE DPFI CIRCUIT The realization of grounded to floating positive and negative impedance converters without digital control is given in reference [2]. Here, the grounded impedance is converted into digitally programmable floating impedance (DPFI) using single DPDVCC as shown in figure 2(a). The grounded impedance (Zg) to be converted as DPFI (Zf) is connected at port-X of the DPDVCC [2]. Zg Zf = Nm Figure 2(a): The DPFI circuit 33
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEThe routine analysis yields its admittance matrix as follows.  I 1  N  1 − 1 V1   I  = Z  − 1 1  V  …………………….. (3)  2 g   2 Thus the equivalent floating impedance Zf can be expressed as Zg Z f = ………………………………… (4) NThe realized floating impedance given in equation (4) can result the digitally programmablefloating ideal element simulators through appropriate termination of grounded impedance Zg.Two cases are demonstrated as follows. (i) Digitally programmable ideal floating resistor (DPFR) (Rf): If Zg = Rg, then Zf = Rf = Rg/N. (ii) Digitally programmable ideal floating capacitor (DPFC) (Cf): If Zg = 1/sCg, then Zf = 1/sCgN, with Cf = Cg N.Thus, the digitally programmable floating resistor Rf is inversely proportional to control wordN, while the digitally programmable floating capacitor Cf is directly proportional to thecontrol word N. Similarly, any grounded active or passive impedance terminated at port-X ofthe DPDVCC of figure 2(a) will be transformed into its reconfigurable floating impedanceform without any component matching constraint. It is also to be noted that just byinterchanging the Y1 and Y2 terminals of the DPDVCC in figure 2(a), the circuit realizesdigitally programmable negative floating impedance (DPNFI) as shown in figure 2(b). − Zg Zf = Nm Figure 2(b): The DPNFI circuit 34
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME The incremental sensitivity measure of the realized floating impedance with respect to passive element is analyzed and given as follows. Z S Zgf , N = | 1 | ………………………………..……(5) From equation (5), it is evident that the incremental sensitivity measure of the realized floating impedance with respect to passive element is unity in magnitude [35]. Taking the tracking errors of the DPDVCC into account, the relationship of the terminal voltages and currents of the DPDVCC can be rewritten as IY1 = IY 2 = 0 VX = β (VY1 −VY 2 ) I Z + = +αNIX I Z − = −αNIX .......................................................(6) where, β is the voltage transfer gain from Y to X terminal and α is the current transfer gain of the DPDVCC from X to Z terminal. The above transfer gains slightly deviate from unity and the deviations are quite small and technology dependent [15]. By including these non-ideal effects the DPDVCC the floating impedance given in equation (4) is modified as follows. Zg Z f = αβ ……………………………………….. N (7) Thus, from equation (7) it is observed that the magnitude of the floating impedance Zf may get slightly affected due to non idealities of the DPDVCC.IV. DESIGN AND VERIFICATION The realized DPFI of figure 2 was designed and verified by performing PSPICE simulation with supply voltage ± 2.5 V, using CMOS TSMC 0.25 µm technology parameters. The aspect ratios used are given in the Table 1. The DPFI was used to design a digitally programmable ideal floating resistor (DPFR) and a digitally programmable ideal floating capacitor (DPFC), respectively used in first order low pass filter (LPF) and high pass filter (HPF) as shown in figure 3(a) and figure 3(b). 35
  6. 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Table 1: The aspect ratios of the MOSFETs of the DPCCII W L MOSFETs µm µm M1, M2, M3, M4 0.8 0.25 M5, M6 4 0.25 M7, M8, 14 0.25 M9, M13, M14,, M11, M25, M17, M39 25 0.25 M19, M26, M33, M40 50 0.25 M20, M27, M34, M41 100 0.25 M21, M28, M35, M42 200 0.25 M10, M15, M16, M12, M29, M18, M43 10 0.25 M22, M30, M36, M44 20 0.25 M23, M31, M37, M45 40 0.25 M24, M32, M38, M46 80 0.25 Figure 3(a): The prototype and its DPFR based first order LPFThe cutoff frequency (f0) of the LPF with Rg= R and Rf = R/N, can be expressed as follows. N f0 = ……….…..…………………………. (8) 2 π RCSimilarly, the cutoff frequency (f0) of the HPF with Cg =C and Cf = CN, can be expressed asfollows. 1 f0 = …..……..……………………………(9) 2 π RCN 36
  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Figure 3(b): The prototype and its DPFC based first order HPFThus from equation (8) and (9) it is evident that the cutoff frequency f0 of the LPF is directlyproportional to the digital control word N, while for HPF it is inversely proportional to N.Initially, the LPF was designed for a cutoff frequency f0 = 100 KHz, at N = 1. Using equation Figure 4(a): The frequency response of the LPF using DPFR, at different control word N(8), the designed values were found as R =3.7K , C=0.43nF. Then to control the cutofffrequency f0, the digital control word N was changed to 2, 4, 8 and 15. Thus, the resultsobserved are shown in figure 4(a). It is to be noted that in LPF of figure 3(a), at node 3, highpass response is also available and given in figure 4(a). Similarly, the DPFC based HPF offigure 3(b) was also designed for a cutoff frequency f0 = 100 KHz at N = 1. Using equation(9), the designed values were found as C=0.43nF, R=3.7K . Then to control the cutofffrequency f0, the digital control word N was changed to 2, 4, 8 and 15. The results observedfor HPF are shown in figure 4(b). Again, it is to be noted that in HPF of figure 3(b), at node 3low pass response is also available with same cutoff frequency as that of LPF, and shown infigure 4(b). Thus the observed results of figure 4 show the close conformity with the theory. 37
  8. 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Figure 4(b): The frequency response of the HPF using DPFC, at different control word NV. CONCLUSION The grounded impedance is converted into a reconfigurable floating impedance using single CMOS digitally programmable differential voltage current conveyor without any component matching constraint. The realized reconfigurable floating impedance can be digitally controlled and possesses low sensitivity. To verify the proposed theory the reconfigurable floating impedance is used to realize a digitally programmable floating resistor and digitally programmable floating capacitor. The realized digitally programmable floating resistor and capacitor respectively were used to implement prototype first order low pass filter and high pass filter. The digitally programmable floating impedance based low pass and high pass filters were designed and verified using PSPICE and the results thus obtained justify the theory. REFERENCES [1] B. Wilson, Recent developments in current conveyors and current-mode circuits, IEE Proceedings-G, 137(2), 1990, 63–77. [2] H. Q. Elwan, and A. M. Soliman, Novel CMOS differential voltage current conveyor and its applications, IEE Proc. Circuits Devices Systems, 144(3), 1997, 195-200. [3] C. Toumazou, F. J. Lidgey and D. G. Haigh, Analogue IC Design: The Current-Mode Approach (IEE, York, UK, 1998). [4] I. A. Khan and S. Maheshwari, Simple first order all-pass section using a single CCII, International Journal of Electronics, 87(3), 2000, 303-306. [5] I. A. Khan and M. H. Zaidi, Multifunctional translinear-C current-mode filter, International Journal of Electronics, 87(9), 2000, 1047–1051. [6] R. Mita, G. Palumbo and S. Pennisi, 1.5-V CMOS CCII+ with high current-drive capability, IEEE Trans. CAS-II, 50(4), 2003, 187-190. 38
  9. 9. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME[7] S. Minaei, M. A. Ibrahim and H. Kuntman, DVCC based current-mode first order all-pass filter and its application, Proceedings of The 10th IEEE International Conference on Electronics Circuits and Systems, Turkey, 2003, 276-279.[8] V. Kumar, A. U. Keskin, and K. Pal, DVCC based single element controlled oscillators using all grounded components and simultaneous current voltage mode outputs, Frequenz, 2005, 7–8.[9] I. A. Khan, P. Beg and M. T. Ahmed, First order current mode filters and multiphase sinusoidal oscillators using MOCCIIs, Arabian, Journal of Science and Engineering, Saudi Arabia, 32(2C), 2007, 119-126.[10] T. Tsukutani, Y. Sumi and N. Yabuki, Novel current mode biquadratic circuit using only plus type DO-DVCCs and grounded passive components, International Journal of Electronics, 94(12), 2007, 1137–1146.[11] Y. Sumi, T. Tsukutani and N. Yabuki, Novel current-mode biquadratic circuit using only plus type DO-DVCCCs, Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS-08), 8(11), 2008, 1–4.[12] I. A. Khan and P. Beg, Fully differential sinusoidal quadrature oscillator using CMOS DVCC, Proc. International Conference on Communication, Computers and Power (ICCCP-2009), Muscat, Oman, 2009, ISSN: 1813-419X-101.1-101.3.[13] S. Minaei and M. A. Ibrahim, A mixed-mode KHN-biquad using DVCC and grounded passive elements suitable for direct cascading, International Journal of Circuit Theory and Applications, 37(7), 2009, 793–810.[14] M. S. Ansari and I. A. Khan, Multiphase differential sinusoidal oscillator based on DVCC, Int. J. of Recent Trends in Engineering and Technology, 4(3), 2010, 96-99.[15] B. Chaturvedi and S. Maheshwari, Current mode biquad filter with minimum component count, Active and Passive Electronic Components, 2011, doi:10.1155/2011/391642, 2011, 1-7.[16] P. Beg, I. A. Khan and S. Maheshwari, Biphase amplifier based precision rectifiers using current conveyors, International J. Computer Applications, 42(3), 2012, 14-18.[17] S. A. Mahmoud, M. A. Hashiesh and A. M. Soliman, Low-voltage digitally controlled fully differential current conveyor, IEEE Transactions on Circuits and Systems-I, 52(10), 2005, 2055-2064.[18] I. A. Khan, M. R. Khan and N. Afzal, Digitally programmable multifunctional filters using CCIIs, Journal of Active and Passive Electronic Devices, 1, 2006, 213-220.[19] T. M. Hassan and S. A. Mahmoud, Low voltage digitally programmable band pass filter with independent control, IEEE International Conference on Signal Processing and Communications (ICSPC-2007), Dubai, UAE, 2007, 24-27.[20] S. A. Mahmoud, Low voltage wide range CMOS differential voltage current conveyor and its applications, Contemporary Engineering Sciences, 1(3), 2008, 105-126.[21] I. A. Khan, M. R. Khan and N. Afzal, A Digitally Programmable Impedance Multiplier using CCIIs with High Resolution Capability, Journal of Active and Passive Electronic Devices, 8, 2009, 247-257.[22] T. M. Hassan and S. A. Mahmoud, Fully programmable universal filter with independent gain, ω0 and Q control based on new digitally programmable CMOS CCII, Journal of Circuits, Systems and Computers, 18(5), 2009, 875-897.[23] I. A. Khan and M. T. Simsim, A Novel Impedance Multiplier using Low voltage Digitally Controlled CCII, Proc. IEEE GCC Conference and Exhibition, Dubai, UAE, 2011, 331-334. 39
  10. 10. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME[24] I. A. Khan and A. M. Nahhas, Reconfigurable voltage mode first order multifunctional filter using single low voltage digitally controlled CMOS CCII, International J. Computer Applications, 45(5), 2012, 37-40.[25] I. A. Khan and A. M. Nahhas, Reconfigurable voltage mode phase shifter using low voltage digitally controlled CMOS CCII, Electrical and Electronic Engineering, 2(4), 2012, 226-229.[26] A. M. Nahhas, Reconfigurable current mode programmable multifunctional filter, International J. on Recent Trends in Engineering and Technology, 7(2), 2012, 88-91.[27] M. Z. Khan and M. A. Ansari, Digitally programmable voltage mode universal biquadratic filter, International J. Computer Applications, 54(16), 2012, 26-31.[28] I. A. Khan and M. H. Zaidi, A novel ideal floating inductor using translinear conveyors, Active and Passive Elect. Comp., 26(2), 2003, 87-89.[29] I. A. Khan and M. H. Zaidi, A novel generalized impedance converter using single second generation current conveyor, Active and Passive Elect. Comp., 26(2), 2003, 91-94.[30] A. M. Soliman, On the realization of floating inductors, Nature and Science, 8(5), 2010, 167-180.[31] A. M. Soliman, and R. A. Saad, New families of floating FDNR circuits, Journal of Electrical and Computer Engineering, 1-7, 2010, doi:10.1155/2010/563761.[32] F. Kacar, and H. Kuntman, CFOA-based lossless and lossy inductance simulators, Radio Engineering, 20(3), 2011, 627–631.[33] M. T. Abuelma’atti, New grounded immittance function simulators using single current feedback operational amplifier, Analog Integrated Circuits and Signal Processing, 71(1), 2012, 95–100.[34] M. A. Ibrahim, S. Minaei, E. Yuce, H. Norbert and K. Jaroslav, , Lossy/lossless floating grounded inductance simulation using DDCC, Radio Engineering, 21(1), 2012, 3-10.[35] R. Senani, and D. R. Bhasker, New lossy/loss-less synthetic floating inductance configuration realized with only two CFOAs, Analog Integrated Circuits and Signal Processing, 73, 2012, 981–987.[36] N. Afzal and I. A. Khan, Digitally programmable floating impedance multiplier using DVCC, International Journal of Electronics Communication and Computer Technology, 3(1), 2013, 358-361.[37] A. M. nahhas, Digitally Programmable Floating Impedance Converter using CMOS- DVCC, International J. Computer Applications, March, 2013.[38] I. A. Khan and A. M. Nahhas, Current mode programmable analog modules using low voltage digitally controlled CMOS CCII, International J. Computer Applications, 48(4), 2012, 38-44.[39] T. L. Floyd, Electronic Devices Conventional Current Version (Ninth Edition, Pearson, 2012).[40] S. A. Mahmoud and E. A.Soliman, Low voltage current conveyor-based field programmable analog array, Journal of Circuits, Systems, and Computers, 20(8), 2011, 1677- 1701.[41] http://www.anadigm.com-dynamically programmable Analog Signal Processor or Field Programmable Analog Array.[42] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, “Low Power Design Techniques of CMOS Digital Circuits” International journal of Electronics and Communication Engineering & Technology (IJECET), Volume 3, Issue 2, 2012, pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472, Published by IAEME. 40

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