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Fault-Tolerant Network Interfaces for Networks-on-Chip
ABSTRACT:
As the complexity of designs increases and technology scales down into the deep-submicron
domain, the probability of malfunctions and failures in the networks-on-chip (NoCs)
components increases. In this work, we focus on the study and evaluation of techniques for
increasing reliability and resilience of network interfaces (NIs) within NoC-based
multiprocessor system-on-chip architectures. NIs act as interfaces between intellectual
property cores and the communication infrastructure; the faulty behavior of one of them
could affect, therefore, the overall system. In this work, we propose a functional fault model
for the NI components by evaluating their susceptibility to faults. We present a two-level
fault-tolerant solution that can be employed for mitigating the effects of both permanent and
temporary faults in the NI. Experimental simulations show that with a limited overhead, we
can obtain an NI reliability comparable to the one obtainable by implementing the system by
using standard triple modular redundancy techniques, while saving up to 48 percent in area,
as well as obtaining a significant energy reduction.
EXISTING SYSTEM:
The fault tolerance of NoC-based systems has been addressed by a significant amount of
research effort. On the one hand, the correct communication of data and control data is
studied: in fault-tolerant solutions are proposed to mitigate transmission errors due
forinstance to crosstalk, electromagnetic radiations, or alpha particles. Discussedsolutions are

2. mainly based on the useof error detecting and correcting codes or/and retransmission . In this
work, we address the fault tolerance of NIs. Previous work focused on the definition of a
functional fault model notation or on providing support for error detection in links ,In
multiple Nis connect a core to more than one router, improving the fault tolerance of the
connections between NIs and routers. However, as demonstrated in Section 3, the NoC can
still suffer from errors in the communication due to faulty behaviors of NI components. In
general, previous work about NI can be considered complementary to the solution presented
in this paper. With respect to it, we address not only permanent faults in the link connecting
the core to the NI, but we propose a solution able to deal with both permanent and temporary
faults in all the main architectural elements of the NI.
PROPOSED SYSTEM:
We proposed and discusseda functional fault model for the NI based on the behavior on its
main components, i.e., the lookup table, FIFOs, and the finite-state machines driving NI
operations. We proposed new architectural solutions based on the use of error correcting and
detecting codes and a limited amount of redundancy, and discussed policies for the
reconfiguration of the components that should be applied at the detection of errors. In our
experiments, we obtained a saving of up to 48 percent in the area overhead, as well as a
significant energy reduction, with respect to an alternative standard hardware TMR
implementation of the NI, while maintaining a similar level of robustness to faults.
CONCLUSION:
This paper presented a study on the implementation of fault-tolerant network interfaces for
NoCs. By performing a fault injection campaign on the NoC, NIs, and routers,
wedemonstrated how the NI could be the main source of errors in the NoC, in particular
when the number of nodes in the network increases. Moreover, we showed that the
occurrence of permanent and temporary faults in the network interface could cause an
unwanted behavior that may create unrecoverable situations in the NoC, such as deadlock or
livelock conditions. We proposed and discussed a functional fault model for the NI based on
the behavior on its main components, i.e., the lookup table, FIFOs, and the finite-state
machines driving NI operations. We proposed new architectural solutions based on the use of

3. error correcting and detecting codes and a limited amount of redundancy, and discussed
policies for there configuration of the components that should be applied at the detection of
errors. In our experiments, we obtained a saving of up to 48 percent in the area overhead, as
well as a significant energy reduction, with respect to an alternative standard hardware TMR
implementation of the NI, while maintaining a similar level of robustness to faults.
SYSTEM CONFIGURATION:-
HARDWARE CONFIGURATION:-
 Processor - Pentium –IV
 Speed - 1.1 Ghz
 RAM - 256 MB(min)
 Hard Disk - 20 GB
 Key Board - Standard Windows Keyboard
 Mouse - Two or Three Button Mouse
 Monitor - SVGA
SOFTWARE CONFIGURATION:-
 Operating System : Windows XP
 Programming Language : JAVA
 Java Version : JDK 1.6 & above.