The research center at Stanford Research Institute aims to develop principles for designing computer systems that can augment human intellect. The center has 12 workstations connected to a time-sharing computer. Researchers use the workstations to develop these augmentation systems, making them both the subject and developer of the research. The goal is to eventually do all work online by placing documents, code, and more in the computer and interacting via the workstations.
Google-Wide Profiling (GWP) is a continuous profiling infrastructure that provides performance insights for cloud applications running across Google's data centers. With negligible overhead, GWP collects stable and accurate profiles from thousands of applications running on thousands of servers. It introduces novel applications of the profiles, such as measuring application-platform affinity and identifying platform-specific microarchitectural peculiarities. GWP collects profiles daily from several data centers and stores the compressed data, totaling several terabytes. It faces challenges in verifying the correctness of profiles at this massive scale and making the profile data universally accessible.
FPGA Implementation of Multiplier-less CDF-5/3 Wavelet Transform for Image Pr...IOSRJVSP
Most of the digital image processing application uses various domain transformation technique to convert time domain information to transform domain which will help to simplify the mathematical modeling. Discrete Wavelet Transform is one of the best transformation techniques. The time-frequency resolution makes this transform sensitive to both time and frequency which will give very good compression and decompression. In this paper, we propose FPGA implementation of multiplier-less CDF-5/3 wavelet transform for image processing application using System-Generator tool.To maintain low area and high frequency we use multiplier-less architecture for CDF-5/3 DWT for our implementation. The VHDL code for multiplier-less structure is fed to system generator tool using standard procedure and synthesis the structure to get the area and frequency
Memory allocation for real time operating systemAsma'a Lafi
Memory allocation strategies in real-time operating systems differ from traditional operating systems in order to improve system performance. Real-time operating systems use static and dynamic memory allocation. Static allocation assigns memory at design time while dynamic allocation occurs at runtime using memory managers. Common dynamic allocation algorithms for real-time systems include buddy allocation, indexed fit, bitmapped fit, and two-level segregated fit, which aim to minimize fragmentation and response times. The document compares various allocation algorithms and concludes that dynamic allocation presents challenges for real-time systems to optimize fragmentation, response time, and locality.
Modified Distributive Arithmetic Based DWT-IDWT Processor Design and FPGA Imp...IOSR Journals
1) The document describes a modified distributive arithmetic based discrete wavelet transform (DWT) processor architecture and its FPGA implementation for image compression.
2) The proposed architecture uses four lookup tables to store pre-computed partial products of filter coefficients, achieving a latency of 44 clock cycles and throughput of 4 clock cycles.
3) A software reference model is developed in Matlab to analyze the performance of various wavelets for image compression using the distributive arithmetic based DWT approach. The input image is resized and decomposed into sub-bands using DWT and reconstructed using IDWT.
Heterogeneous computing utilizes a suite of diverse high-performance machines, including parallel machines, to effectively address computationally demanding tasks with diverse needs. It provides a novel approach to overcome limitations of homogeneous systems by coordinating different machine types instead of replacing existing systems. The document discusses challenges posed by heterogeneous computing and surveys some approaches to leverage its opportunities through techniques like profiling code types, generating intermediate code for different machines, and matching portions of code to their optimal machine type.
This document discusses parallel processing and the evolution of computer systems. It covers several topics:
- The evolution of computer systems from vacuum tubes to integrated circuits, organized into generations.
- Concepts of parallel processing including Flynn's classification of computer architectures based on instruction and data streams.
- Parallel processing mechanisms in uniprocessor systems including pipelining and memory hierarchies.
- Three classes of parallel computer structures: pipeline computers, array processors, and multiprocessor systems.
- Architectural classification schemes including Flynn's, Feng's based on serial vs parallel processing, and Handler's based on parallelism levels.
This talk is given at Vizianagaram where many Engineering college faculty were attended. I have introduced developments in multi-core computers along with their architectural developments. Also, I have explained about high performance computing, where these are used. I have introduced the concept of pipelining, Amdahl's law, issues related to pipelining, MIPS architecture.
Data Analytics and Simulation in Parallel with MATLAB*Intel® Software
This talk covers the current parallel capabilities in MATLAB*. Learn about its parallel language and distributed and tall arrays. Interact with GPUs both on the desktop and in the cluster. Combine this information into an interesting algorithmic framework for data analysis and simulation.
Google-Wide Profiling (GWP) is a continuous profiling infrastructure that provides performance insights for cloud applications running across Google's data centers. With negligible overhead, GWP collects stable and accurate profiles from thousands of applications running on thousands of servers. It introduces novel applications of the profiles, such as measuring application-platform affinity and identifying platform-specific microarchitectural peculiarities. GWP collects profiles daily from several data centers and stores the compressed data, totaling several terabytes. It faces challenges in verifying the correctness of profiles at this massive scale and making the profile data universally accessible.
FPGA Implementation of Multiplier-less CDF-5/3 Wavelet Transform for Image Pr...IOSRJVSP
Most of the digital image processing application uses various domain transformation technique to convert time domain information to transform domain which will help to simplify the mathematical modeling. Discrete Wavelet Transform is one of the best transformation techniques. The time-frequency resolution makes this transform sensitive to both time and frequency which will give very good compression and decompression. In this paper, we propose FPGA implementation of multiplier-less CDF-5/3 wavelet transform for image processing application using System-Generator tool.To maintain low area and high frequency we use multiplier-less architecture for CDF-5/3 DWT for our implementation. The VHDL code for multiplier-less structure is fed to system generator tool using standard procedure and synthesis the structure to get the area and frequency
Memory allocation for real time operating systemAsma'a Lafi
Memory allocation strategies in real-time operating systems differ from traditional operating systems in order to improve system performance. Real-time operating systems use static and dynamic memory allocation. Static allocation assigns memory at design time while dynamic allocation occurs at runtime using memory managers. Common dynamic allocation algorithms for real-time systems include buddy allocation, indexed fit, bitmapped fit, and two-level segregated fit, which aim to minimize fragmentation and response times. The document compares various allocation algorithms and concludes that dynamic allocation presents challenges for real-time systems to optimize fragmentation, response time, and locality.
Modified Distributive Arithmetic Based DWT-IDWT Processor Design and FPGA Imp...IOSR Journals
1) The document describes a modified distributive arithmetic based discrete wavelet transform (DWT) processor architecture and its FPGA implementation for image compression.
2) The proposed architecture uses four lookup tables to store pre-computed partial products of filter coefficients, achieving a latency of 44 clock cycles and throughput of 4 clock cycles.
3) A software reference model is developed in Matlab to analyze the performance of various wavelets for image compression using the distributive arithmetic based DWT approach. The input image is resized and decomposed into sub-bands using DWT and reconstructed using IDWT.
Heterogeneous computing utilizes a suite of diverse high-performance machines, including parallel machines, to effectively address computationally demanding tasks with diverse needs. It provides a novel approach to overcome limitations of homogeneous systems by coordinating different machine types instead of replacing existing systems. The document discusses challenges posed by heterogeneous computing and surveys some approaches to leverage its opportunities through techniques like profiling code types, generating intermediate code for different machines, and matching portions of code to their optimal machine type.
This document discusses parallel processing and the evolution of computer systems. It covers several topics:
- The evolution of computer systems from vacuum tubes to integrated circuits, organized into generations.
- Concepts of parallel processing including Flynn's classification of computer architectures based on instruction and data streams.
- Parallel processing mechanisms in uniprocessor systems including pipelining and memory hierarchies.
- Three classes of parallel computer structures: pipeline computers, array processors, and multiprocessor systems.
- Architectural classification schemes including Flynn's, Feng's based on serial vs parallel processing, and Handler's based on parallelism levels.
This talk is given at Vizianagaram where many Engineering college faculty were attended. I have introduced developments in multi-core computers along with their architectural developments. Also, I have explained about high performance computing, where these are used. I have introduced the concept of pipelining, Amdahl's law, issues related to pipelining, MIPS architecture.
Data Analytics and Simulation in Parallel with MATLAB*Intel® Software
This talk covers the current parallel capabilities in MATLAB*. Learn about its parallel language and distributed and tall arrays. Interact with GPUs both on the desktop and in the cluster. Combine this information into an interesting algorithmic framework for data analysis and simulation.
Performance analysis of sobel edge filter on heterogeneous system using opencleSAT Publishing House
This document discusses performance analysis of the Sobel edge detection filter on heterogeneous systems using OpenCL. It begins with an introduction to OpenCL and describes its architecture, including the platform model, execution model, memory model, and programming model. It then provides an overview of GPUs and CPUs, comparing their architectures and number of cores. It also gives mathematical representations of image convolution and describes how the Sobel filter works. The document analyzes the performance of implementing Sobel edge detection using OpenCL on CPUs and GPUs and finds that GPUs provide much higher performance compared to CPUs.
The document discusses Sony's Cell Broadband Engine (Cell/B.E.) and RSX graphics engine. It provides 3 key points:
1) The Cell/B.E. is an asymmetric multi-core processor developed by Sony, IBM, and Toshiba that combines a general-purpose PowerPC core (PPE) with eight specialized compute cores (SPEs) connected by a high-speed bus. It provides high computational performance through parallel processing.
2) The RSX graphics engine, developed with NVIDIA, processes graphics through programmable shaders. It is connected to the Cell/B.E. via a high-speed bus and provides accelerated graphics processing.
Embedded systems developers can reduce costs by consolidating multiple systems onto a single multicore processor hardware platform. Each CPU core can be dedicated to a real-time task, such as motion control or vision processing. This allows real-time and general-purpose operating systems to coexist on individual cores without performance penalties. A virtualization-enabled real-time OS is needed to provide hardware-enforced isolation between OS environments on different cores. Using virtual devices and shared memory, applications can then communicate across OS environments with low interrupt latency comparable to a single-core system.
The document contains a multiple choice quiz with questions about various topics in computer science. There are 47 multiple choice questions testing knowledge about topics like binary, memory, operating systems, programming languages, networks, and security. The questions are short, with single sentences providing the prompts and possible multiple choice answers.
This document discusses the evolution of computing from being compute-centric to data-centric. It introduces concepts like the memory wall problem and concurrent average memory access time (C-AMAT) model which considers data access concurrency. It also discusses solutions for improving parallel I/O performance like prefetching, data layout optimization, and merging of HPC and big data frameworks. The challenges in data-intensive computing and how the author's lab can help with applications and methods are also summarized.
The document discusses different types of computer hardware and peripherals. It describes input devices like keyboards and mice, output devices like monitors and printers, internal components like the CPU and memory, and different categories of computers from microcomputers to mainframes. It then focuses on describing monitors and printers in more detail, contrasting CRT and flat panel monitors and dot matrix versus non-impact printers.
This document provides an overview of the syllabus for the course CS6303 - Computer Architecture. It covers the following key topics in 3 sentences or less:
- Components of a computer system including input, output, memory, datapath, and control. Instructions and their representation. Addressing modes for accessing operands.
- Eight major ideas in computer architecture: designing for Moore's law, using abstraction, optimizing common cases, performance via parallelism and pipelining, performance via prediction, hierarchy of memories, and dependability via redundancy.
- Evolution from uniprocessors to multiprocessors to address power constraints. Instruction formats, operations, logical and control operations, and different addressing modes for specifying operand locations
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Main memory is where programs are loaded to run on the CPU. There are several techniques for managing memory allocation and binding programs to addresses in memory, including compile-time, load-time, and execution-time binding. Memory management is needed to map logical addresses used by programs to physical addresses in memory. Paging is a memory management technique that divides memory into pages to allow non-contiguous allocation and reduce fragmentation.
AVOIDING DUPLICATED COMPUTATION TO IMPROVE THE PERFORMANCE OF PFSP ON CUDA GPUScsandit
The document discusses improving the performance of the Tabu Search algorithm for solving the Permutation Flowshop Scheduling Problem (PFSP) on CUDA GPUs by avoiding duplicated computation among threads. It first provides background on GPU architecture, the PFSP problem, and related parallelization methods. It then observes that if two permutations share the same prefix, their completion time tables will contain identical column data equal to the length of the prefix, leading to duplicated computation. The paper proposes an approach where each thread is assigned a permutation and allocated shared memory to store and compute the completion time table in parallel, avoiding this duplicated work by leveraging the shared prefix property. Experimental results show the new approach runs up to 1.5 times faster than an existing
The document discusses parallel computing over the past 25 years and challenges for using multicore chips in the next decade. It aims to provide context to scale applications effectively to 32-1024 cores. Key challenges include expressing inherent application parallelism while enabling efficient mapping to hardware through programming models and runtime systems. Future work includes developing methods to restore lost parallelism information and tradeoffs between programming effort, generality and performance.
This document provides an overview of parallel computing concepts. It defines parallel computing as using multiple compute resources simultaneously to solve a problem by breaking it into discrete parts that can be solved concurrently. It discusses Flynn's taxonomy for classifying computer architectures based on whether their instruction and data streams are single or multiple. Shared memory, distributed memory, and hybrid memory models are described for parallel computer architectures. Programming models like shared memory, message passing, data parallel and hybrid models are covered. Reasons for using parallel computing include saving time/money, solving larger problems, providing concurrency, and limits of serial computing.
This document provides an overview of topics to be covered in a mid-term exam for a computer graphics course. The topics include introductions and applications of computer graphics, graphics hardware and I/O devices, interactive and non-interactive computer graphics, raster and vector graphics, scan converting lines and shapes, 2D transformations, 2D viewing, and 2D zooming and panning. The document was prepared by Bahadar sher and provides his email for contact.
1. This document introduces parallel computing, which involves dividing large problems into smaller concurrent tasks that can be solved simultaneously using multiple processors to reduce computation time.
2. Parallel computing systems include single machines with multi-core CPUs and computer clusters consisting of multiple interconnected machines. Common parallel programming models involve message passing between distributed memory processors.
3. Performance of parallel programs is measured by metrics like speedup and efficiency. Factors like load balancing, serial fractions of problems, and parallel overhead affect how well a problem can scale with additional processors.
Linux-Based Data Acquisition and Processing On Palmtop ComputerIOSR Journals
This document describes a Linux-based data acquisition and processing system implemented on a palmtop computer. The system uses a PCMCIA data acquisition card and free Linux drivers and libraries to acquire signals from sensors. As a demonstration, a phonometer application was created that can sample 1024 signals at 100 ksamples/s and compute the fast Fourier transform of the signal up to 6 times per second. The document outlines the hardware and software design of the system, including using a custom Linux kernel, COMEDI libraries for device control, and TCL/Tk for the user interface. Experimental results showed the system could successfully implement the phonometer application for acoustic signal analysis on the palmtop computer.
This document presents a task allocation model for balancing resource utilization in a multiprocessor environment. It discusses partitioning a task into modules and allocating the modules to processors to minimize execution time. The model aims to minimize total execution cost while balancing the load across processors and minimizing inter-task communication costs. It presents the mathematical modeling and development of an algorithm to allocate m modules of a task to n processors. The algorithm considers execution costs, communication costs, and task sizes to determine the optimal allocation that balances utilization across processors. An example application of the model to a system with 3 processors and 9 task modules is provided.
The document describes the high-level design of a software rejuvenation system. It discusses how the system is broken down into modular components with dependencies between them. Data flow diagrams are used to design the system at different levels, showing how data flows between processing steps. Level 0 shows the main rejuvenation process, level 1 shows setting threshold values, and level 2 shows more detailed steps like checking aging factors and memory usage. The sequence diagram depicts the variable time and workload policy, with the system updating the rejuvenation time based on workload. Detailed modules are described for OS and VM cold/warm reboot processes.
This document provides an overview of supercomputers including their definition, the top supercomputers in the world by processing speed, India's fastest supercomputer SahasraT, proposed methodology for a prototype supercomputer using a 1-4 node cluster, common network topologies like fat tree and torus, how performance would be analyzed using benchmarking software, basic components of the prototype model, and potential applications of supercomputers in scientific research, data management, and multitasking.
This document contains the questions and answers from a computer architecture and organization exam. It includes questions about the differences between computer architecture and organization, instruction formats, bus definitions, cache memory advantages, and virtual memory. The responses provide detailed explanations of concepts like locality of reference, thrashing, address mapping, cache hits and misses, and hierarchical memory systems. Justification is given for using a hierarchical approach to improve performance across different memory types. The differences between paging and segmentation in virtual memory are also distinguished.
This document provides an overview of Lawrence Livermore National Laboratory's (LLNL) Massively Parallel Computing Initiative (MPCI) and its applications of parallel computing. The MPCI uses clusters of "killer microprocessors" to perform simulations and modeling faster than traditional supercomputers. The document discusses LLNL's implementation of molecular dynamics simulations using a geometric domain decomposition approach across multiple processors. It also briefly mentions applying this same approach to image processing and hydrodynamics simulations.
Performance analysis of sobel edge filter on heterogeneous system using opencleSAT Publishing House
This document discusses performance analysis of the Sobel edge detection filter on heterogeneous systems using OpenCL. It begins with an introduction to OpenCL and describes its architecture, including the platform model, execution model, memory model, and programming model. It then provides an overview of GPUs and CPUs, comparing their architectures and number of cores. It also gives mathematical representations of image convolution and describes how the Sobel filter works. The document analyzes the performance of implementing Sobel edge detection using OpenCL on CPUs and GPUs and finds that GPUs provide much higher performance compared to CPUs.
The document discusses Sony's Cell Broadband Engine (Cell/B.E.) and RSX graphics engine. It provides 3 key points:
1) The Cell/B.E. is an asymmetric multi-core processor developed by Sony, IBM, and Toshiba that combines a general-purpose PowerPC core (PPE) with eight specialized compute cores (SPEs) connected by a high-speed bus. It provides high computational performance through parallel processing.
2) The RSX graphics engine, developed with NVIDIA, processes graphics through programmable shaders. It is connected to the Cell/B.E. via a high-speed bus and provides accelerated graphics processing.
Embedded systems developers can reduce costs by consolidating multiple systems onto a single multicore processor hardware platform. Each CPU core can be dedicated to a real-time task, such as motion control or vision processing. This allows real-time and general-purpose operating systems to coexist on individual cores without performance penalties. A virtualization-enabled real-time OS is needed to provide hardware-enforced isolation between OS environments on different cores. Using virtual devices and shared memory, applications can then communicate across OS environments with low interrupt latency comparable to a single-core system.
The document contains a multiple choice quiz with questions about various topics in computer science. There are 47 multiple choice questions testing knowledge about topics like binary, memory, operating systems, programming languages, networks, and security. The questions are short, with single sentences providing the prompts and possible multiple choice answers.
This document discusses the evolution of computing from being compute-centric to data-centric. It introduces concepts like the memory wall problem and concurrent average memory access time (C-AMAT) model which considers data access concurrency. It also discusses solutions for improving parallel I/O performance like prefetching, data layout optimization, and merging of HPC and big data frameworks. The challenges in data-intensive computing and how the author's lab can help with applications and methods are also summarized.
The document discusses different types of computer hardware and peripherals. It describes input devices like keyboards and mice, output devices like monitors and printers, internal components like the CPU and memory, and different categories of computers from microcomputers to mainframes. It then focuses on describing monitors and printers in more detail, contrasting CRT and flat panel monitors and dot matrix versus non-impact printers.
This document provides an overview of the syllabus for the course CS6303 - Computer Architecture. It covers the following key topics in 3 sentences or less:
- Components of a computer system including input, output, memory, datapath, and control. Instructions and their representation. Addressing modes for accessing operands.
- Eight major ideas in computer architecture: designing for Moore's law, using abstraction, optimizing common cases, performance via parallelism and pipelining, performance via prediction, hierarchy of memories, and dependability via redundancy.
- Evolution from uniprocessors to multiprocessors to address power constraints. Instruction formats, operations, logical and control operations, and different addressing modes for specifying operand locations
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Main memory is where programs are loaded to run on the CPU. There are several techniques for managing memory allocation and binding programs to addresses in memory, including compile-time, load-time, and execution-time binding. Memory management is needed to map logical addresses used by programs to physical addresses in memory. Paging is a memory management technique that divides memory into pages to allow non-contiguous allocation and reduce fragmentation.
AVOIDING DUPLICATED COMPUTATION TO IMPROVE THE PERFORMANCE OF PFSP ON CUDA GPUScsandit
The document discusses improving the performance of the Tabu Search algorithm for solving the Permutation Flowshop Scheduling Problem (PFSP) on CUDA GPUs by avoiding duplicated computation among threads. It first provides background on GPU architecture, the PFSP problem, and related parallelization methods. It then observes that if two permutations share the same prefix, their completion time tables will contain identical column data equal to the length of the prefix, leading to duplicated computation. The paper proposes an approach where each thread is assigned a permutation and allocated shared memory to store and compute the completion time table in parallel, avoiding this duplicated work by leveraging the shared prefix property. Experimental results show the new approach runs up to 1.5 times faster than an existing
The document discusses parallel computing over the past 25 years and challenges for using multicore chips in the next decade. It aims to provide context to scale applications effectively to 32-1024 cores. Key challenges include expressing inherent application parallelism while enabling efficient mapping to hardware through programming models and runtime systems. Future work includes developing methods to restore lost parallelism information and tradeoffs between programming effort, generality and performance.
This document provides an overview of parallel computing concepts. It defines parallel computing as using multiple compute resources simultaneously to solve a problem by breaking it into discrete parts that can be solved concurrently. It discusses Flynn's taxonomy for classifying computer architectures based on whether their instruction and data streams are single or multiple. Shared memory, distributed memory, and hybrid memory models are described for parallel computer architectures. Programming models like shared memory, message passing, data parallel and hybrid models are covered. Reasons for using parallel computing include saving time/money, solving larger problems, providing concurrency, and limits of serial computing.
This document provides an overview of topics to be covered in a mid-term exam for a computer graphics course. The topics include introductions and applications of computer graphics, graphics hardware and I/O devices, interactive and non-interactive computer graphics, raster and vector graphics, scan converting lines and shapes, 2D transformations, 2D viewing, and 2D zooming and panning. The document was prepared by Bahadar sher and provides his email for contact.
1. This document introduces parallel computing, which involves dividing large problems into smaller concurrent tasks that can be solved simultaneously using multiple processors to reduce computation time.
2. Parallel computing systems include single machines with multi-core CPUs and computer clusters consisting of multiple interconnected machines. Common parallel programming models involve message passing between distributed memory processors.
3. Performance of parallel programs is measured by metrics like speedup and efficiency. Factors like load balancing, serial fractions of problems, and parallel overhead affect how well a problem can scale with additional processors.
Linux-Based Data Acquisition and Processing On Palmtop ComputerIOSR Journals
This document describes a Linux-based data acquisition and processing system implemented on a palmtop computer. The system uses a PCMCIA data acquisition card and free Linux drivers and libraries to acquire signals from sensors. As a demonstration, a phonometer application was created that can sample 1024 signals at 100 ksamples/s and compute the fast Fourier transform of the signal up to 6 times per second. The document outlines the hardware and software design of the system, including using a custom Linux kernel, COMEDI libraries for device control, and TCL/Tk for the user interface. Experimental results showed the system could successfully implement the phonometer application for acoustic signal analysis on the palmtop computer.
This document presents a task allocation model for balancing resource utilization in a multiprocessor environment. It discusses partitioning a task into modules and allocating the modules to processors to minimize execution time. The model aims to minimize total execution cost while balancing the load across processors and minimizing inter-task communication costs. It presents the mathematical modeling and development of an algorithm to allocate m modules of a task to n processors. The algorithm considers execution costs, communication costs, and task sizes to determine the optimal allocation that balances utilization across processors. An example application of the model to a system with 3 processors and 9 task modules is provided.
The document describes the high-level design of a software rejuvenation system. It discusses how the system is broken down into modular components with dependencies between them. Data flow diagrams are used to design the system at different levels, showing how data flows between processing steps. Level 0 shows the main rejuvenation process, level 1 shows setting threshold values, and level 2 shows more detailed steps like checking aging factors and memory usage. The sequence diagram depicts the variable time and workload policy, with the system updating the rejuvenation time based on workload. Detailed modules are described for OS and VM cold/warm reboot processes.
This document provides an overview of supercomputers including their definition, the top supercomputers in the world by processing speed, India's fastest supercomputer SahasraT, proposed methodology for a prototype supercomputer using a 1-4 node cluster, common network topologies like fat tree and torus, how performance would be analyzed using benchmarking software, basic components of the prototype model, and potential applications of supercomputers in scientific research, data management, and multitasking.
This document contains the questions and answers from a computer architecture and organization exam. It includes questions about the differences between computer architecture and organization, instruction formats, bus definitions, cache memory advantages, and virtual memory. The responses provide detailed explanations of concepts like locality of reference, thrashing, address mapping, cache hits and misses, and hierarchical memory systems. Justification is given for using a hierarchical approach to improve performance across different memory types. The differences between paging and segmentation in virtual memory are also distinguished.
This document provides an overview of Lawrence Livermore National Laboratory's (LLNL) Massively Parallel Computing Initiative (MPCI) and its applications of parallel computing. The MPCI uses clusters of "killer microprocessors" to perform simulations and modeling faster than traditional supercomputers. The document discusses LLNL's implementation of molecular dynamics simulations using a geometric domain decomposition approach across multiple processors. It also briefly mentions applying this same approach to image processing and hydrodynamics simulations.
This document discusses the evolution of computer systems from early relay-based computers to modern parallel processing systems. It covers the progression from vacuum tubes to integrated circuits, increasing computer speeds and capabilities over generations. The key aspects covered are:
1. Computer components including the CPU, memory, and I/O have advanced significantly from early electromechanical to modern integrated systems.
2. Parallel processing has increased from basic multiprocessing to finer-grained instruction-level parallelism using pipelining and multiple functional units.
3. Uniprocessor computers exploit parallelism through techniques like overlapping I/O and CPU operations, hierarchical memory systems, and multiprogramming.
An Overview of Intel TFLOPS Super ComputerSerwer Alam
The document provides an overview of the Intel TFLOPS supercomputer, which was the first supercomputer built for the Accelerated Strategic Computing Initiative (ASCI) program. The ASCI program was created by the Department of Energy to accelerate the development of extremely powerful supercomputers capable of simulations needed to maintain the US nuclear stockpile without testing. The Intel TFLOPS supercomputer, known as the ASCI Option Red supercomputer, had over 9,000 Intel Pentium Pro processors and was capable of 1.34 trillion floating point operations per second, setting a new world record. It utilized a massively parallel distributed memory architecture across its nodes, which were connected via a high-speed interconnect network.
The document describes a multiprogramming system with a hierarchical structure implemented on a Dutch computer. The system divides all activities across sequential processes at different hierarchical levels, with independent abstractions at each level. This hierarchical structure proved vital for verifying the system's logical soundness and implementation correctness. The primary goal of the system is to smoothly process a continuous flow of user programs as a service to the university.
1. A computer is an electronic device that performs tasks by executing instructions from users or programs. It processes data, performs calculations, stores information, and communicates with other devices.
2. A computer's basic architecture consists of input devices, a central processing unit (CPU), memory, output devices, and storage devices interconnected via a motherboard and bus system. The CPU executes instructions and performs calculations using an arithmetic logic unit, while the control unit coordinates activities.
3. Computers have progressed through five generations from vacuum tubes to integrated circuits and microprocessors. Programming languages have also evolved from machine language to high-level languages like C++ and Python.
Parallelization of Graceful Labeling Using Open MPIJSRED
This document summarizes research on parallelizing the graceful graph labeling problem using OpenMP on multi-core processors. It introduces the concepts of parallelization, multi-core architecture, and OpenMP. An algorithm is designed to parallelize graceful labeling by distributing graph vertices across processor cores. Execution time and speedup are measured for graphs of increasing size, showing improved speedup and reduced time with parallelization. Results show consistent performance gains as graph size increases due to better utilization of the multi-core architecture.
Bedtime Stories on Operating Systems.pdfAyushBaiswar1
The document provides an overview of processes and process scheduling in operating systems. Some key points:
- A process is a program in execution that is represented by a process control block containing its state, scheduling information, and other data.
- There are three main scheduling queues: job queue, ready queue, and device queues. Scheduling algorithms select processes from the ready queue for CPU execution.
- The main scheduling algorithms discussed are first-come, first-served; shortest job first; and priority scheduling. Shortest job first can increase throughput but requires predicting process lengths.
- Context switching involves saving the state of the current process and loading the next process. The goal of scheduling is to maximize CPU and
(Im2col)accelerating deep neural networks on low power heterogeneous architec...Bomm Kim
This document discusses accelerating deep neural networks on low power heterogeneous architectures. Specifically, it focuses on accelerating the inference time of the VGG-16 neural network on the ODROID-XU4 board, which contains an ARM CPU and Mali GPU. The authors develop parallel versions of VGG-16 using OpenMP for the CPU and OpenCL for the GPU. Several optimizations are explored in OpenCL, including work groups, vector data types, and the CLBlast library. The best OpenCL implementation achieves a 9.4x speedup over the original serial version.
The document describes a microcontroller-based emulator that can mimic the functionality of various logic gates and structured logic devices in real-time. The emulator uses a read-only memory (ROM) device to store the logic patterns of different devices. Address lines of the ROM are used as inputs to select the desired device and its corresponding logic pattern. This allows the emulator to function like the selected logic device through its input/output pins. The emulator provides a low-cost solution for students to perform digital design experiments and engineers to prototype systems without requiring the actual logic components.
Possible Worlds Explorer: Datalog & Answer Set Programming for the Rest of UsBertram Ludäscher
PWE: Datalog & ASP for the Rest of Us discusses using Possible Worlds Explorer (PWE) to make Datalog and Answer Set Programming (ASP) more accessible to non-experts. It covers topics like using provenance to explain query results, capturing rule firings to track provenance, representing provenance as a graph, using states to track derivation rounds, and declarative profiling of Datalog programs. The presentation advocates for tools like PWE that wrap Datalog/ASP engines to combine them with Python ecosystems and allow interactive use in Jupyter notebooks. This makes the languages more approachable and helps users build on existing work by experimenting further.
This paper describes an integrated performance monitoring environment for parallel systems. It consists of:
1) A distributed monitoring system that collects performance data from instrumented applications and sends it to analysis tools.
2) Graphical and command-line profiling and visualization tools that analyze the performance data to identify bottlenecks.
3) A common graphical interface that provides a consistent way to instrument applications, start tool runs, and view performance results across different tools.
The environment aims to handle large amounts of performance data from massively parallel applications and provide insights at both the application and system level. It is initially targeted for the Intel Paragon but is designed to support different programming models.
The document summarizes benchmarking results for four magnetic fusion simulation codes: GTS, TGYRO, BOUT++, and VORPAL. It was performed on the Cray XE6 "Hopper" supercomputer at NERSC to evaluate performance, scalability, memory usage, and communication overhead at large scales. For GTS, weak scaling tests showed computation time remained constant while communication time increased slightly with up to 49,152 cores. Testing also examined the codes' sensitivity to reduced memory bandwidth by increasing core count per node. Overall results provide insight to improve fusion code design and inform exascale co-design efforts.
Parallel computing is computing architecture paradigm ., in which processing required to solve a problem is done in more than one processor parallel way.
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A research center for augmenting human intellect
1. APR 5 1974
3954
A research center for augmenting human intellect*”
by DOUGLAS C. EN.GELBART
and WILLIAM K. ENGLISH
Stanford RmeamhZmtiiule
Menlo Park, California
AFIPS - Conference Proceedings, Volume 33
51CopyrIght @ 1968 by Thompson Book Company
I SUMMARY
la This paper describes a multisponsor re-
search center at Stanford Research Institute in
man-computer interaction.
actions and computer feedback involved in
controlling the application of these service
functions) .
la1 For its laboratory facility, the Center
has a time-sharing computer (65K, 24-bit
core) with a 4.5 megabyte swapping drum
and a 96 megabyte file-storage disk. This
serves twelve CRT work stations simultane-
ously.
l&a Special hardware completely removes
from the CPU the burden of display re-
freshing and input sampling, even though
these are done directly out of and into core,
lalb The display in a user’s office appears
on a high-resolution (875-line) commercial
television monitor, and provides both char-
acter and vector portrayals. A relatively
standard typewriter keyboard is supple-
mented by a five-key handset used (option-
ally) for entry of control codes and brief
literals. An SRI cursor device called the
“mouse” is used for screen pointing and
selection.
1b User files are organized as hierarchical
structures of data entities, each composed of
arbitrary combinations of text and figures. A
repertoire of coordinated service features en-
ables a skilled user to compose, study, and mod-
ify these files with great speed and flexibility,
and to have searches, analyses data manipula-
tion, etc. executed. In particular, special sets of
conventions, functions, and working methods
have been developed to air programming, logi-
cal design, documentation, retrieval, project
management, team interaction, and hard-copy
production.
B INTRODUCTION
lalbl The “mouse” is a hand-held X-Y
transducer usable on any flat surface ; it
is described in greater detail further on.
lag Special-purpose high-level languages and
associated compilers provide rapid, flexible
development and modification of the reper-
toire of service functions and of their control
procedures (the latter being the detailed user
aa In the Augmented Human Intellect (AHI)
Research Center at Stanford Research Institute
a group of researchers is developing an experi-
mental laboratory around an interactive, multi-
console computer-display system, and is work-
ing to learn the principles by which interactive
computer aids can augment their intellectual
capability.
2b The research objective is to develop prin-
ciples and techniques for designing an “aug-
mentation system.”
*Principal ~KWIOIS~IF: Advanced Research Projects Agency
and National Aeronautics and Spaca Agency (NASl-7897), and
Rome Air Dev&pment Center F306V.
2bl This includes concern not only for the
technology of providing interactive computer
service, but also for changes both in ways of
conceptualizing, visualizing, and organizing
working material, and in procedures and
methods for working individually and coop-
eratively.
2. 396 Fall Joint Computer Conference, 1968
2c The research approach is strongly empirical.
At the workplace of each member of the subject
group we aim to provide nearly full-time avail-
ability of a CRT work station, and then to work
continuously to improve both the service avail-
able at the stations and the aggregate value de-
rived therefrom by the group over the entire
range of its roles and activities.
2d Thus the research group is also the subject
group in the experiment.
2d1 Among the special activities of the group
are the evolutionary development of a com-
plex hardware-software system, the design of
new task procedures for the system’s users,
and careful documentation of the evolving
system designs and user procedures.
2d2 The group also has the usual activities
of managing its activities, keeping up with
outside developments, publishing reports, etc.
2&S Hence, the particulars of the augmenta-
tion system evolving here will reflect the na-
ture of these tasks-i.e., the system is aimed
at augmenting a system-development project
team. Though the primary research goal is
to develop principles of analysis and design
so as to understand how to augment human
capability, choosing the researchers them-
selves as subjects yields as valuable secondary
benefit a system tailored to help develop com-
plex computer-based systems.
2e This “bootstrap” group has the interesting
(recursive) assignment of developing tools and
techniques to make it more effective at carrying
out its assignment.
2el Its tangible product is a developing aug-
mentation system to provide increased capa-
bility for developing and studying augmenta-
tion systems.
2e2 This system can hopefully be transferred,
as a whole or by pieces of concept, principle
and technique, to help others develop augmen-
tation systems for aiding many other dis-
ciplines and activities.
2f In other words we are concentrating fully
upon reaching the point where we can do all
of our work on line-placing in computer store
all of our specifications, plans, designs, pro-
grams, documentation, reports, memos, bibliog-
raphy and reference notes, etc., and doing all
of our scratch work, planning, designing, de-
bugging, etc., and a good deal of our intercom-
munication, via the consoles.
2fl We are trying to maximize the coverage
of our documentation, using it as a dynamic
and plastic structure that we continually de-
velop and alter to represent the current state
of our evolving goals, plans, progress, knowl-
edge, designs, procedures, and data.
2g The display-computer system to support this
experiment is just (at this writing) becoming
operational. Its functional features serve a
basic display-oriented user system that we have
evolved over five years and through three other
computers. Below are described the principal
features of these systems.
9 THE USER SYSTEM
3u Basic Facility
3~1 As “seen” by the user, the basic facility
has the following characteristics :
3ulu 12 CRT consoles, of which 10 are
normally located in offices of AH1 research
St&.
3~1 b The consoles are served by an SDS
940 time-sharing computer dedicated to
full-time service for this staff, and each
console may operate entirely independently
of the others.
Salt Each individual has private file space,
and the group has community space, on a
high-speed disc with a capacity of 96 mil-
lion characters.
3~2 The system is not intended to serve a
general community of time-sharing users, but
is being shaped in its entire design toward
the special needs of the “bootstrapping” ex-
periment.
3b Work Stations
Sbl As noted above, each work station is
equipped with a display, an alphanumeric
keyboard, a mouse, and a five-key handset.
3bZ The display at each of the work stations
(see Figure 1) is provided on a high-resolu-
tion, closed-circuit television monitor.
3. --
Research Center for Augmenting Human Intellect 397
FIGURE I-Typical work station., with TV display, typewriter
keyboard, mouse, and chord handset
3b3 The alphanumeric keyboard is similar to
a Teletype keyboard. It has 96 normal char-
acters in two cases. A third-case shift key
provides for future expansion, and two spe-
cial keys are used for system control,
8b4 The mouse produces two analog voltages
ast het wo wheels (see Figure 2) rotate, each
changing in proportion to the X or Y move-
ment over the table top.
Sb4u These voltages control-via an A/D
converter, the computer’s memory, and the
display generator-the coordinates of a
tracking spot with which the user may
“noint” to positions on the screen.
3b4b Three buttons on top of the mouse
are used for special control.
3b4c A set of experiments, comparing
(within our techniques of interaction) the
FIGURE 2-Underside of mouee
relative speed and accuracy obtained with
this and other selection devices showed the
mouse to be better than a light pen or a joy-
stick (see Refs. English 1 and English 2).
3b4cl Compared to a light pen, it is gen-
erally less awkward and fatiguing to use,
and it has a decided advantage for use
with raster-scan, write-through storage
tube, projection, or multiviewer display
systems.
3b5 The five-key handset has 31 chords or
unique key-stroke combinations, in five
“cases.”
3b5a The first four cases contain lower-
and upper-case letters and punctuation,
digits, and special characters. (The chords
for the letters correspond to the binary
numbers from 1 to 26.)
3b5b The fifth case is “control case.” A
particular chord (the same chord in each
case) will always transfer subsequent in-
put-chord interpretations to control case.
3b5c In control case, one can “backspace”
through recent input, specify underlining
for subsequent input, transfer to another
case, visit another case for one character
or one word, etc.
3b5d One-handed typing with the handset
is slower than two-handed typing with the
standard keyboard. However, when the
user works with one hand on the handset
and one on the mouse, the coordinated in-
4. 398 Fall Joint Computer Conference, 1968
terspersion of control characters and short
literal strings from one hand with mouse-
control actions from the other yields con-
siderable advantage in speed and smooth-
ness of operation.
3b5dl For literal strings longer than
about ten characters, one tends to trans-
fer from the handset to the normal key-
board.
Jb5d2 Both from general experience and
from specific experiment, it seems that
enough handset skill to make its use
worthwhile can generally be achieved
with about five hours of practice. Be-
yond this, skill grows with usage.
3c Structure of Files
3~1 Our working information is organized
into files, with flexible means for users to set
up indices and directories, and to hop from
file to file by display-selection or by typed-in
file-name designations. Each file is highly
structured in its internal organization.
&la The specific structure of a given file
is determined by the user, and is an im-
portant part of his conceptual and “study-
manipulate” treatment of the file.
3~2 The introduction of explicit “structur-
ing” to ‘our working information stems from
a very basic feature of our conceptual frame-
work (see Refs. Engelbartl and Engelbart2)
regarding means for augmenting human in-
tellect.
Sc2a With the view that the symbols one
works with are supposed to represent a
mapping of one’s associated concepts, and
further that one’s concepts exist in a “net-
work” of relationships as opposed to the
essentially linear form of actual printed
records, it was decided that the concept-
manipulation aids derivable from real-time
computer support could be appreciably en-
hanced by structuring conventions that
would make explicit (for both the user and
the computer) the various types of network
relationships among concepts.
3c2b As an experiment with this concept,
we adopted some years ago the convention
of organizing all information into explicit
hierarchical structures, with provisions for
arbitrary cross-referencing among the ele-
ments of a hierarchy.
3c2bl The principal manifestation of
this hierarchical structure is the break-
ing up of text into arbitrary segments
called “statements,” each of which bears
a number showing its serial location in
the text and its “level” in an “outline” of
the text. This paper is an example of
hierarchical text structure.
3c2c To set up a reference link from State-
ment A to Statement B, one may refer in
Statement A either to the location number
of B or to the “name” of B. The difference
is that the number is vulnerable to subse-
quent structural change, whereas the name
stays with the statement through changes
in the structure around it.
3~2~1 By convention, the first word of
a statement is treated as the name of the
statement, if it is enclosed in paren-
theses. For instance, Statement 0 on the
screen of Figure 1 is named “FJCC.”
3~2~2 References to these names may be
embedded anywhere in other statements,
for instance as “see (AFI) ,” where ape-
cial format informs the viewer explicitly
that this refers to a statement named
“AFI,” or merely as a string of char-
acters in a context such that the viewer
can infer the referencing.
SC%.??This naminga nd linking, when
added to the basic hierarchical form,
yields a highly flexible general structur-
ing capability. These structuring con-
ventions are expected to evolve relatively
rapidly as our research progresses.
Sc3 For some material, the structured-
statement form may be undesirable. In
these cases, there are means for suppress-
ing the special formatting in the final print-
out of the structured text.
3~4 The basic validity of the structured-
text approach has been well established by
our subsequent experience.
SC&Z We have found that in both off-line
and on-line computer aids, the concep-
5. Research Center for Augmenting Human Intellect 399
tion, stipulation, and execution of sig-
nificant manipulations are made much
easier by the structuring conventions.
SC& Also, in working on line at a CRT
console, not only is manipulation made
much easier and more powerful by the
structure, but a user’s ability to get
about very quickly within his data, and
to have special “views” of it generated
to suit his need, are significantly aided
by the structure.
3c4c We have come to write all of our
documentation, notes, reports, and pro-
posals according to these conventions,
because of the resulting increase in our
ability to study and manipulate them
during composition, modification, and
usage. Our programming systems also
incorporate the conventions. We have
found it to be fairly universal that after
an initial period of negative reaction in
reading explicitly structured material,
one comes to prefer it to material printed
in the normal form.
Sd File Studying
8dl The computer aids are used for two prin-
cipal “studying” operations, both concerned
with construction of the user’s “views,” i.e.,
the portion of his working text that he sees
on the screen at a given moment.
3dla Display Start
3dZal The first operation is finding a
particular statement in the file (called
the “display start”) ; the view will then
begin with that statement. This is equiva-
lent to finding the beginning of a par-
ticular passage in a hard-copy document.
3dlb Form of View
Sdlbl The second operation is the speci-
fication of a “form” of view-it may
simply consist of a screenful of text
which sequentially follows the point spec-
ified as the display start, or it may be
constructed in other ways, frequently so
as to give the effect of an outline.
8dlc In normal, off-line document study-
ing, one often does the first type of opera-
tion, but the second is like a sissors-and-
staple job and is rarely done just to aid
one’s studying.
3dld (A third type of service operation
that will undoubtedly be of significant aid
to studying is question answering. We do
not have this type of service.)
3d2 Specification of Display Start
3d2a The display start may be specified in
several ways :
3d2al By direct selection of a statement
which is on the display-the user simply
points to any character in the statement,
using the mouse.
3d2u2 If the desired display start is not
on the display, it may be selected in-
directly if it bears a “marker.”
3d2u2a Markers are normally invisi-
ble. A marker has a name of up to five
characters, and is attached to a char-
acter of the text. Referring to the
marker by name (while holding down
a special button) is exactly equivalent
to pointing to the character with the
mouse.
3d2a2b The control procedures make it
extremely quick and easy to fix and
call markers.
8d2a8 By furnishing either the name or
the location number of the statement,
which can be done in either of two basic
ways :
3d2u3a Typing from the keyboard
8d2u8b Selecting an occurrence of the
name or number in the text. This may
be done either directly or via an in-
direct marker selection.
3d2b After identifying a statement by one
of the above means, the user may request
to be taken directly there for his next view.
Alternately, he may request instead that
he be taken to some statement bearing a
specified structure relationship to the one
specifically identified. For instance, when
the user identifies Statement 3E4 by one
of the above means (assume it to be a
member of the list 3El through 3E’7), he
may ask to be taken to
6. 400 Fall Joint Computer Conference, 1968
SdXbl Its successor, i.e., Statement 3E5
Sd2b2 Its predecessor, i.e., Statement
3E3
Sd2bS Its list tail, i.e., Statement 3E7
Sd2b4 Its list head, i.e., Statement 3El
Sd2b5 Its list source, i.e., Statement 3E
Sd2b6 Its subhead, i.e., Statement 3E4A
Sd2c Besides being taken to an explicitly
identified statement, a user may ask to go
to the first statement in the file (or the
next after the current location) that con-
tains a specified word or string of char-
acters.
Sd2cl He may specify the search string
by typing it in, by direct (mouse) selec-
tion, or by indirect (marker) selection.
3d3 Specification of Form of View
SdSa The “normal” view beginning at a
given location is like a frame cut out from
a long scroll upon which the hierarchical
set of statements is printed in sequential
order. Such a view is displayed in Figure 1.
SdSb Otherwise, three independently vari-
able view-specification conditions may be
applied to the construction of the displayed
view: level clipping, line truncation, and
content filtering. The view is simultaneous-
ly affected by all three of these.
3dSbl Level : Given a specified level
parameter, L (L = 1, 2, . . . , ALL), the
view generator will display only those
statements whose “depth” is less than
or equal to L. (For example, Statement
3E4 is third level, 3E second, 4B2Cl fifth,
etc.) Thus it is possible to see only first-
level statements, or only first-, second-,
and third level statements, for example.
Sd3b2 Truncation : Given a specified
truncation parameter, T (T = 1, 2, . . .,
AIL) , the view generator will show only
the first T lines of each statement being
displayed.
3d3bS Content: Given a specification for
desired content (written in a special
high-level content-analysis language) the
view generator optionally can be directed
to display only those statements that
have the specified content.
Sd3bSa One can specify simple strings,
or logical combinations thereof, or such
things as having the word “memory”
within four words of the word “alloca-
tion.”
Sd3bSb Content specifications are writ-
ten as text, anywhere in the file. Thus
the full power of the system may be
used for composing and modifying them.
3dSbSc Any one content specification can
then be chosen for application (by select-
ing it directly or indirectly). It is com-
piled immediately to produce a machine-
code content-analysis routine, which is
then ready to “filter” statements for the
view generator.
Sd,Sc In addition, the following format fea-
tures of the display may be independently
varied : indentation of statements accord-
ing to level, suppression of location num-
bers and/or names of statements, and sepa-
ration of statements by blank lines.
S&d .The user controls these view speci-
fications by means of brief, mnemonic char-
acter codes. A skilled user will readjust
his view to suit immediate needs very
quickly and frequently ; for example, he
may change level and truncation settings
several times in as many seconds.
sd4 “Freezing” Statements
3d4a One may also preempt an arbitrary
amount of the upper portion of the screen
for holding a collection of “frozen” state-
ments. The remaining lower portion is
treated as a reduced-size scanning frame,
and the view generator follows the same
rules for filling it as described above.
3d4b The frozen statements may be inde-
pendently chosen or dismissed, each may
have line truncation independent of the
rest, and the order in which they are dis-
played is arbitrary and readily changed.
Any screen-select operand for any com-
mand may be selected from any portion of
the display (including the frozen state-
merits).
7. Research Center for Augmenting Human Intellect 401
Sd5 Examples
ScZ5aFigures 3 and 4 show views generated
from the same starting point with different
level-clipping parameters. This example hap-
pens to be of a program written in our Ma-
chine-oriented language (MOL, see below).
3d5b Figure 5, demonstrates the freezing
feature with a view of a program (the same
one shown in Figure 8) written in our Con-
trol Metalanguage (CML, see below). State-
ments 3C, 3C2, 2B, 2B1, 2B2, 2B3, and 2B4
are frozen, and statements from 25 on are
shown normally with L = 3, T = 1.
3d5bl The freezing here was used to hold
for sil’nultaneous view four different func-
tionally related process descriptions.
The subroutines (+ BUGlSPEC) and
FIGURE 3-View of BP MOL pmgram, with level paramet,er
set to X and truncation to 1
FIGURE 4-Same program as Figure 3, but with level parameter
changed to 6 (several levels still remain hidden from view)
(+ WAIT were located by use of the
hop-to-name feature described above.
Se File Modification
Se1 Here we use a standard set of editing
operations, specifying with each operation a
particular type of text entity.
Se1 a Operations : Delete, Insert, Replace,
Move, Copy.
3elb Entities (within text of statements) :
Character, Text (arbitrary strings), Word,
Visible (print string), Invisible (gap
string) .
delc Entities (for structure manipula-
tion) : Statement, Branch (statement plus
all substructure), Group (sublist of branch-
es), Plex (complete list of branches).
Se2 Structure may also be modified by join-
ing statements, or breaking a statement into
two at a specified point.
Se3 Generally, an operation and an entity
make up a command, such as “Delete Word.”
To specify the command, the user types the
first letter of each word in the command:
thus “DW” specifies “Delete Word.” There
are occasional cases where a third word is
used or where the first letter cannot be used
because of ambiguities.
.?f File Output
3fl Files may be sent to any of a number of
different output devices to produce hard
copy-an upper/lower-case line printer, an
8. 402 Fall Joint Computer Conference, 1968
on-line highquality typewriter, or paper tape
to drive various typewriters.
Jfra In future it will be possible to send
files via magnetic tape to an off-line CRT-
to-film system from which we can produce
Xerox prints, Multilith masters, or micro-
form records.
8fg Flexible format control may he exercised
in this process by means of specially coded
directives embedded in the files-running
headers, page numbering, line lengths, line
centering, suppression of location numbers?
indenting, right justification (hyphenless),
etc., are controllable features.
3gl ,Source-wde files written in any of our
compiler languagex~ (age below), or in the
SDS 940 assembly language (ARPAS, in
which our compiler output is produced) may
be compiled under on-line control, For de-
bugging, we .have made a trivial addition to
the SDS 940’s DDT loaderdebugger so as to
operate it from the CRT displays. Though it
was designed to operate from a Teletype
terminal, this system gains a great deal in
speed and power by merely showing with a
display the Iast 26 lines of what would have
been on the Teletype output.
ah Calculating
Jhl The same small innovation as mentioned
above for DDT enables us to use the CAL
system from a display tzrminal.
3i Conferencing
8i1 We have set up a room specially equipped
for on-line conferencing. Six displays are
arranged in the center of a square table (see
Figure 6) so that each of twenty participants
has good visibility. One participant controls
the system, and all displays show the same
view. The other participants have mice that
control a large arrow .on the screen, for use
as a pointer (with no control function).
8U As a quick means of Anding and display-
ing (with appropriate forms of view) any
desired material from a very large collection,
this system is a powerful aid to presentation
and review conferences.
FIGURE 6on-line conferenw arrangement
Sti We are also experimenting with it in
project meetings, using it not only to keep
track of agenda items and changes but also
to log progress notes, action notes, etc. The
review aid is of course highly useful here
also.
3ti We are anxious to see what special con-
ventions and procedures will evolve to allow
us to harness a number of independent con-
soles within a conference group. This obvi-
ously has considerable potential.
4 SERVICE-SYSTEM SCFTWARF
4a The U&s Control Iduguage
.&cl Consider the service a user gets from
the computer tc be in the form of discrete
operations-i. e., the execution of individual
“service functions” from a repertoire com-
prising a “service system.”
4ala Examples of service functions are
deleting a word, replacing a character,
hopping to a name, etc.
4~8 Associated with each function of this
repertoire is a “control-dialogue procedure.”
This procedure involves selecting a service
function from the repertoire, setting up the
nw parameter designations for a par-
ticular ,application, recovering from user
errors, and calling for the execution of the
function.
4&a The procedure is made up of the
sequence of keystrokes, select actions, etc.
9. Research Center for Augmenting Human Intellect 403
made by the user, together with the inter-
spersed feedback messages from the com-
puter.
4~8 The repertoire of service functions, to-
gether with their control-dialogue procedures,
constitutes the user’s “control language.”
This is a language for a “master-slave” dia-
logue, enabling the user to control applica-
tion of the computer’s capabilities to his own
service.
4~8~ It seems clear that significant aug-
mentation of one’s intellectual effectiveness
from the harnessing of computer services
will require development of a broad and
sophisticated control-language vocabulary.
4a& It follows that the evolution of such
a control language is a very important part
of augmentation-system research.
4~4 For the designer of user systems, it is
important to have good means for specifying
the nature of the functions and their respec-
tive controldialogue procedures, so that a
design specification will be
4u4a Concise, so that its essential features
are easily seen
4u4b Unambiguous, so that questions about
the design may be answered clearly
4u4c Canonical, so that information is
easily located
4u4d Natural, so that the form of the de-
scription fits the conceptual frame of the
design
4a4e Easy to compose, study, and modify,
so that the process of evolutionary design
can be facilitated.
4~5 It is also important for the user to have
a description of the service functions and
their controldialogue procedures.
da52 The description must again be con-
cise, unambiguous, canonical, and natural ;
furthermore, it must be accurate, in that
everything relevant to the user about the
service functions and their control-dialogue
procedures is described, and everything de-
scribed actually works as indicated.
FIGURE 7-Statschart portrayal of part of the text-manipule-
tion control languages
4b State-Chmt Repreaedation of Cmtrol-Lfm-
imwe De&m
4bl Figure 7 shows a charting method that
was used in earlier stages of our work for
designing and specifying the control-pro-
cedure portions of the control language.
Even though limited to describing only the
control-dialogue procedures, this representa-
tion nonetheless served very well and led us
to develop the successive techniques described
below.
4b2 Figure 7 shows actual control procedures
for four service functions from the repertoire
of an interactive system: Delete Word, De-
lete Text, Place Up Statement, and Forward
Statement.
4b2a The boxes contain abbreviated de-
scriptions of relevant display-feedback
conditions, representing the intermediate
states between successive user actions.
Both to illustrate how the charting con-
ventions are used and to give some feeling
for the dynamics of our user-system con-
trol procedures, we describe briefly below
both the chart symbols and the associated
display-feedback conventions that we have
developed.
-&b&l The writing at the top of each
box indicates what is to be shown a.p
“command feedback” at the top of the
display (see Figures 3, 4 and 6).
4b2ala An uparrow sometimes ap-
10. 404 Fall Joint Computer Conference, 1968
pears under the first character of one
of the words of Command Feedback.
4b2alal This indicates to the user
that the next character he types will
be interpreted as designating a new
term to replace that being pointed
to-no uparrow under Command
Feedback signifies that keyboard ac-
tion will not affect the command
designation.
4bZal b “Entity” represents the entity
word (i.e., “character,” “word, “state-
ment,” etc.) that was last used as part
of a fully specified command.
4b2albl The computer often “of-
fers” the user an entity option.
4b2n2 The circle in the box indicates the
character to be used for the “bug” (the
tracking spot), which alternates between
the characters uparrow and plus.
4bda2a The uparrow indicates that a
select action is appropriate, and the
plus indicates that a select action is
inappropriate.
4b2a3 The string of X’s, with under-
lines, indicates that the selected char-
acters are to be underlined as a means
of showing the user what the computer
thinks he has selected.
4b2b There is frequently an X on the out-
put line from a box on the chart. This indi-
cates that the computer is to wait until the
user has made another action.
4b2bl After this next action, the com-
puter follows a branching path, depend-
ing upon what the action was (as indi-
cated on the chart) to reach another
state-description box or one of the func-
tion-execution processes.
4c The Control Metalanguage
4cl In search for an improvement over the
state chart, we looked for the following spe-
cial features, as weli as the general features
listed above :
4cla A representational form using struc-
tural text so as to harness the power of
our on-line text-manipulation techniques
for composing, studying, and modifying
our designs.
4clb A form that would allow us to specify
the service functions as well as the control-
dialogue procedures.
4clc A form such that a designdescrip-
tion file could be translated by a computer
program into the actual implementation of
the control language.
4~2 Using our Tree Meta compiler-compiler
(described below), we have developed a next
step forward in our means of designing,
specifying, implementing and documenting
our on-line control languages. The result is
called “Control Metalanguage” (CML) .
4c2a Figure 8 shows a portion of the de-
scription for the current control language,
written in Control Metalanguage.
4c2al This language is the means for
describing both the service functions and
their control-dialogue procedures.
4c2b The Control Metalanguage Trans-
lator (CMLT) can process a file contain-
ing such a description, to produce a corre-
sponding version of an interactive system
which responds to user actions exactly as
described in the file.
4~3 There is a strong correspondence be-
tween the conventions for representing the
control procedures in Control Metalanguage
and in the state chart, as a comparison of
Figures 8 and 7 will reveal.
4c3a The particular example printed out
for Figure 8 was chosen because it specifies
some of the same procedures as in Figure 7.
4c3b For instance, the steps of display-
feedback states, leading to execution of the
“Delete Word” function, can readily be fol-
lowed in the state chart.
,4c3bl The steps are produced by the
user typing “D,” then “W,” then select-
ing a character in a given word, and then
hitting “command accept” (the CA key).
4cJb2 The corresponding steps are out-
lined below for the Control Metalanguage
description of Figure 8, progressing
from Statement 3, to Statement 3c, to
11. Research Center for Augmenting Human Intellect 405
Statement 3~2, to Subroutine + BUG-
SPEC, etc.
.&3b3 The points or regions in Figure ‘7
corresponding to these statements and
subroutines are marked by (3)) (3C),
(3C2), and (+ BUGlSPEC), to help
compare the two representations.
4&c These same steps are indicated in
Figure 8, starting from Statement 3:
4~3~1 ‘9” sets up the state described in
Statement 3C
4.~3~2 “W” sets up the state described
in Statement 3C2
FIGTJRE S-Metslanguage description of part of control language
3 (WC:) zap case
3A (b) [edit] dsp(backward tes*) . case
.
.
.
3B Cc) [edit] dsp(copy *es*) :s true => <am>adjl: . case
381 (c) s*-cc dsp(tcopy character) e*-c,character +bug2spec
+cdlim(bl ,pl ,p2 ,p3,p4) +cdlim(b2 ,pS,p6 ,p7,p8)
+cpchtx(bl ,P~,P~,PS,P~) ;
382 (w) s*-cw dsp(tcopy word) e*-w,word +bug2spec
+wdr2(bl,pl,p2,p3,p4) +wdrZ(bZ,pS,p6,p7,p8)
+cpwdvs (bl ,p$p4 ,p5 ,p6) ;
3B3 (1) s*-cl dsp(tcopy line) e*=l,line +bug2spec
+ldlim(bl ,pl ,pZ,p3,p4) +ldlim(b2,pS,p6,p7,p8) :c st bl+sf(bl) p2,
rif :p p2>pl cr: then (cr) else (null) , pS p6, p4 se(b1): goto
14
3B4 (v) s*-cv dsp(tcopy visible) e*=v,visible +bug2spec
+vdr2(bl ,pl ,p2,p3,p4) +vdr2(bZ,p5,p6,p7,p8)
l cpwdvs(bl ,p2 ,p4,p5 ,pfd ;
.
.
:blO endcase +caqm ;
3C (d) [edit] dsp(delete tes*) . case
3C1 (c) s*-dc dspttdelete character) e*-c,character +buglspec
+cdlim(bl ,pl ,p2 ,p3,p4) +del;
3C2 (w) s*=dw dsp(+delete word) e*=w,word +buglspec +wdr
W ,pl ,p2 ,p%p4) +deI ;
3c3 (1) s*-dl dsp(tdelete line) e*-1,line +buglspec...
.
.
.
12. 4Q6 Fall Joint Computer Conference, 1968
4~3~3 The subroutine +BUGlSPEC
waits for the select-word (1) and CA
(2) actions leading to the execution of
the delete-word function.
4c3c3a Then the TWDR subroutine
takes the bug-position parameter and
sets pointers Pl through P4 to delimit
the word in the text data.
4c3c3b Finally, the + DEL subroutine
deletes what the pointers delimit, and
then returns to the last-defined state
(i.e., to where S* = DW).
4d Basic Organization of the On-Line System
(NLS)
4dl Figure 9 shows the relationships among
the major components of NLS.
4d2 The Tree Meta Translator is a processor
specially designed to produce new translators.
4d2a There is a special language-the Tree
Meta Language-for use in describing the
translator to be produced.
4d2b A special Tree Meta library of sub-
routines must be used, along with the out-
put of the Tree Meta Translator, to pro-
duce a functioning new translator. The
same library serves for every translator it
produces.
E’IGURE; O-Basic organization of XLS showing UEWof compilers
and compiler-compiler to implement it
4d3 For programming the various subrou-
tines used in our 940 systems, we have de-
veloped a special Machine-Oriented Language
(MOL) , together with an MOL Translator to
convert MOL program descriptions into ma-
chine code (see Ref. Hay1 for a complete
description).
4d3a The MOL is designed to facilitate
system programming, by providing a high-
level language for iterative, conditional,
and arithmetic operations, etc., along with
a block structure and conventions for label-
ing that fit our structured-statement on-
line manipulation aids.
4dSal These permit sophisticated com-
puter aid where suitable, and also allow
the programmer to switch to machine-
level coding (with full access to varia-
bles, labels, etc.) where core space, speed,
timing, core-mapping arrangements, etc.,
are critical.
4d4 The NLS is organized as follows (letters
refer to Figure 9) :
4dbu The Control Processor (E) receives
and processes successive user actions, and
calls upon subroutines in the library (H)
to provide it such services as the following:
4d4aZ Putting display feedback on the
screen
4d4a2 Locating certain data in the file
4d4a3 Manipulating certain working data
4d4a4 Constructing a display view of
specified data according to given view-
ing parameters, etc.
4d4b The NLS library subroutines (H)
are produced from MOL programs (F) ,
as translated by the MOL Translator (G) .
4d4c The Control Processor is produced
from the control-language description (D) ,
written in Control Metalanguage, as trans-
lated by the CMLT (C) .
4d4d The CMLT, in turn, is produced from
a description (A) written in Tree Meta, as
translated by the Tree Meta Translator
(B).
13. Research Center for Augmenting Human Intellect 407
@5 Advantages of Metalanguage Approach
to NLS Implementation
0~85~The metalanguage approach gives us
improved means for control-language spec-
ification, in terms of being unambiguous,
concise, canonical, natural and easy to com-
pose, study and modify.
&Z5b Moreover, the Control Metalanguage
specification promises to provide in itself a
users’ documentation that is completely
accurate, and also has the above desirable
characteristics to facilitate study and refer-
ence.
.$d5c Modifying the control-dialogue pro-
cedures for existing functions, or making
a reasonable range of changes or additions
to these functions, can often be accom-
plished solely by additions or changes to
the control-language record (in CML) .
&&cl With our on-line studying, ma-
nipulating and compiling techniques,
system additions or changes at this level
can be thought out and implemented
(and automatically documented) very
quickly.
.4d5d New functions that require basic
operations not available through existing
subroutines in the NLS library will need
to have new subroutines specified and pro-
grammed (in MOL), and then will need
new terms in CML to permit these new
functions to be called upon. This latter
requires a change in the record (A), and
a new compilation of CMLT by means of
the Tree Meta Translator.
&dl On-line techniques for writing
and modifying the MOL source code (F) ,
for executing the compilations, and for
debugging the routines, greatly reduce
the effort involved in this process.
5 SERVICE-SYSTEM HARDWARE (OTHER
THAN SDS 940)
5a In addition to the SDS 940, the facility in-
cludes peripheral equipment made by other
manufacturers and. equipment designed and
constructed at SRI.
521 All of the non-SDS equipment is interfaced
through the special devices channel which con-
nects to the second memory buss through the
SDS memory interface connection (MIC) .
5211 This equipment, together with the RAD,
is a significant load on the second memory
buss. Not including the proposed “special
operations” equipment, the maximum ex-
pected data rate is approximately 264,000
words per second or one out of every 2.1
memory cycles. However, with the 940 varia-
ble priority scheme for memory access (see
Pirtle’), we expect less than 1 percent de-
gradation in CPU efficiency due to this load.
5b2 This channel and the controllers (with
the exception of the disc controller) were de-
signed and constructed at SRI.
5b2a In the design of the hardware serv-
ing the work stations, we have attempted
to minimize the CPU burden by making
the system as automatic as possible in its
access to memory and by formatting the
data in memory so as to minimize the
executive time necessary to process it for
the users.
5c Figure 10 is a block diagram of the special-
devices channel and associated equipment. The
major components are as follows:
5cl Executive Control
5cla This is essentially a sophisticated
multiplexer that allows independent, asyn-
chronous access to core from any of the
6 controllers connected to it. Its functions
are the following:
5clal Decoding instructions from the
computer and passing them along as
signals to the controllers.
5~1~2 Accepting addresses and requests
for memory access (input or output)
from the controllers, determining rela-
tive priority among the controllers, syn-
chronizing to the computer clock, and
passing the requests along to memory via
the MIC.
5clb The executive control includes a com-
prehensive debugging panel that allows
any of the 6 controllers to be operated off-
line without interfering with the operation
of .other controllers.
14. 408 Fall Joint Computer Conference, 1968
5~2 Disc File
5c2a This is a Model 4061 Bryant disc,
selected for compatibility with the con-
tinued 940-system development by Berke-
ley’s Project GENIE, where extensive file-
handling software was developed.
5c2b As formatted for our use, the disc
will have a storage capacity of approxi-
mately 32 million words, with a data-trans-
fer rate of roughly 40,000 words per second
and average access time of 85 milliseconds.
5c2c The disc controller was designed by
Bryant in close cooperation with SRI and
Project GENIE.
5~3 Display System
5c3a The display systems consists of two
identical subsystems, each with display con-
troller, display generator, G CRT’s, and 6
closed-circuit television systems.
5cSb The display controllers process dis-
play-command tables and display lists that
are resident in core, and pass along dis-
play-buffer contents to the display genera-
tors.
5cSc The display generators and CRT’s
were developed by Tasker Industries to our
specifications. Each has general character-
vector plotting capability. They will accept
display buffers consisting of instructions
(beam motion, character writing, etc. 1
from the controller. Each will drive six
5-inch high-resolution CRT’s on which the
display pictures are produced.
5cScl Character writing time is approxi-
mately 8 microseconds, allowing an aver-
FIGURE lO--Speciel devices channel
- -
L
C.R.T.
DISPLAY DISPLAY
I
- CONTROL - GENERATOR - !
1 1
- I
- I
I
’ MONITOR
-CONTROL -GENERATOR I
MOUSE
KEYSET
KEYBOARD
MOUSE
KEYSET
KEYBOARD
15. Research Center for Augmenting Human Intellect 409
age of 1000 characters on each of the six
monitors when regenerating at 20 cps.
5cSd A high-resolution (8754ine) closed-
circuit television system transmits display
pictures from each CRT to a television
monitor at the corresponding work-station
console.
5cSe This system was developed as a “best
solution” to our experimental-laboratory
needs, but it turned out to have properties
which seem valuable for more widespread
use :
5c3el Since only all-black or all-white
signal levels are being treated, the scan-
beam current on the cameras can be re-
duced to achieve a short-term image-
storage effect that yields flicker-free TV
output even when the display refresh
rate is as low as 15 cps. This allows a
display generator to sustain about four
times more displayed material than if
the users were viewing direct-view re-
freshed tubes.
5cSe2 The total cost of small CRT, TV
camera, amplifier-controller, and monitor
came to about $5500 per work station-
where a random-deflection, display-qual-
ity CRT of similar size would cost con-
siderably more and would be harder to
drive remotely.
5c3e3 Another cost feature which is
very important in some system environ-
ments favors this TV approach: The ex-
pensive part is centrally located; each
outlying monitor costs only about $600,
so terminals can be set up even where
usage will be low, with some video
switching in the central establishment to
take one terminal down and put another
up.
5cbe.4 An interesting feature of the video
system is that with the flick of a switch
the video signal can be inverted, so that
the image picked up as bright lines on
dim background may be viewed as black
lines on a light background. There is a
definite user preference for this inverted
form of display.
5cSf In addition to the advantages noted
above, the television display also invites
the use of such commercially available de-
vices as extra cameras, scan converters,
video switches, and video mixers to enrich
system service.
5cSfl For example, the video image of a
user’s computer-generated display could
be mixed with the image from a camera
focused on a collaborator at another ter-
minal; the two users could communicate
through both the computer and a voice
intercom. Each user would then see the
other’s face superimposed on the display
of date under discussion.
5cSf2 Superimposed views from cameras
focused on film images or drawings, or
on the computer hardware, might also
be useful.
5c3f3 We have experimented with these
techniques (see Figure 11) and found
them to be very effective. They promise
to add a great deal to the value of re-
mote display terminals.
5~4. Input-Device Controller
5~442In addition to the television monitor,
each work-station console has a keyboard,
binary keyset, and mouse.
5&b The controller reads the state of these
FIGURE II-Television display obtained by mixing the video
signal from a remote camera with that from the compmer-
generated display
16. 410 Fall Joint Computer Conference, 1968
devices at a preset interval (about 30 milli-
seconds) and writes it into a fixed location
table in core.
5c4bl Bits are added to information
from the keyboards, keysets and mouse
switches to indicate when a new char-
acter has been received or a switch has
changed state since the last sample. If
there is a new character or switch
change, an interrupt is issued after the
sample period.
5clb2 The mouse coordinates are for-
matted as a beam-positioning instruction
to the display generator. Provisions are
made in the display controller for in-
cluding an entry in the mouse-position
table as a display buffer. This allows
the mouse position to be continuously
displayed without any attention from the
CPU.
5c5 Special Operations
5c5a The box with this label in Figure 10 is
at this time only a provision in the execu-
tive control for the addition of a high-speed
device. We have tentative plans for add-
ing special hardware here to provide opera-
tions not available in the 940 instruction
set, such as character-string moves and
string-pattern matching.
5~6 Low-Priority Devices
5&a This controller accommodates three
devices with relatively low data-transfer
6
6a
6h
6C
6d
6e
6f
rates. At this time only the line printer is
implemented, with provisions for adding
an on-line typewriter (Dura), a plotter,
and a terminal for the proposed ARPA
computer network.
5c6al The line printer is a Potter Model
HSP-3502 chain printer with 96 print-
ing characters and a speed of about 230
lines per minute.
REFERENCES
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