The 8259 programmable interrupt controller can handle up to 64 interrupts. It supports different operating modes like fully nested, rotating priority, and special mask modes. The 8259's priority structure, vector addresses, masking, and triggering can be programmed. It can generate interrupts in response to either edge or level signals and supports different end of interrupt modes.

2. Characteristics of 8259
• A single 8259 handles 8 interrupts, while a cascaded configuration of it in
which 1 master and 8 slaves can handle up to 64 interrupts.
• It can handle both edge-level triggering interrupts.
• Its priority structure can be easily altered.
• In 8259, interrupts can be masked individually.
• The vector address of the interrupts is easily programmed.
• It must be initialized by giving commands, to determine various properties
like vector numbers, priority, masking, triggering etc.

3. Operating Modes of 8259
• The different modes of operation of 8259 can be programmed by altering
the bits of ICW or OCW commands of 8259.
• Types
 Fully nested mode
 Special fully nested mode (SFNM)
 Rotating priority modes
 Special mask mode (SMM)
 Poll mode
 EOI Modes
 Edge and level-triggered mode
 Buffered Mode

4. Fully Nested Mode
• It is the default mode of operation of 8259.
• Here, IR0 has the highest priority and IR7 has the lowest priority. When any
interrupt requests occurs then the highest priority interrupt request is
serviced first and its vector address is placed on data bus and its
corresponding bit in ISR register is set until the processor executes the EOI
command before returning the interrupt service routine or AEOI(Automatic
end of interrupt bit is set) until the falling of the last INTA’.
• When the ISR bit is set for an interrupt, then all the equal and lower
priority interrupts are masked, but a higher level interrupt request can
occur and which will be acknowledged only if the microprocessor interrupt
enables flag IF= 1.
• It is suitable for a single 8259 configuration.
• The priority mechanism can be easily programmed.

5. Special Fully Nested Mode (SFNM)
• This mode is used by master 8259 in a cascaded mode. Its priority
structure is fixed and is the same as fully nested mode (i.e. IR0 has the
highest priority and IR7 has the lowest priority).
• In a special fully nested mode, the master will only serve higher priority
interrupt from a slave, whose another interrupt is currently in service.

6. Rotating Priority Modes
• There are two rotating priority modes
 Automatic Rotation Mode: It is used when various interrupt sources
are of the same priority. In this mode, after a device is serviced, it gets
the lowest priority. All other priorities rotate according to it.
Example: If IR4 has just been serviced, it will get the lowest priority.
 Specific Rotation Mode: The programmer can alter priorities by
programming the lowest priority and thus fixing all other priorities.
Example: If IR6 is programmed as the lowest priority, then IR7 will have
the highest priority.

7. Special Mask Mode (SMM)
• In SMM, 8259 enables interrupts of all levels (lower or higher) except the
one that is currently in service.
• Because it is especially masking the request of the priority level of
interrupt, which is the same as the current interrupt priority level, therefore
it is called special mask mode.

8. Poll Mode
• The INT pin of 8259 is not used, so, 8259 cannot interrupt the µp. Instead,
the µP will provide a poll command to 8259 using OCW3. In response,
8259 provides a poll word to the µP.
• The poll word indicates the highest priority interrupt which needs service
from µP. Thereafter, the µP services the interrupt.

9. EOI Modes
• Normal EOI Mode: An EOI command is compulsory. The EOI command is
written by the programmer at the end of the ISR. It makes 8259 to reset
the bit from ISR. EOI command is of two types :
 Non Specific EOI Command: The programmer doesn’t specify the bit
number to be reset in the ISR. 8259 itself resets the highest priority bit
from ISR.
 Specific EOI Command: The programmer determines the bit number
to be reset from ISR.
• Automatic EOI mode (AEOI): In this mode, the EOI command is not
required. Instead, 8259 will itself clear the corresponding bit from ISR at
the end of the 2nd INTA pulse.

10. Edge and level-triggered mode
• If the LTIM bit of ICW1 =0 then the edge-triggered interrupt mode is set,
otherwise the interrupts are level triggered.
Buffered Mode
• 8259 sends a buffer enabled signal on the SP’/ EN’ pin when data is placed
on the data bus.