The document discusses the 8086 microprocessor. It has a 16-bit data bus (8086) or 8-bit data bus (8088). The 8086 has a 40-pin design while the 8088 has a pin that is either SSO or a regular pin. The document describes the pinouts, bus cycles, memory organization, and differences between minimum and maximum mode systems for both chips.

1. Microprocessors & its
Applications

2. Signals of 8086
• The 8086 is a 16-bit microprocessor with a 16-bit data bus, and the 8088 is a 16-bit microprocessor
with an 8-bit data bus. (As the pin-outs show, the 8086 has pin connections AD0-AD15, and the
8088 has pin connections AD0-AD7.)
• Data bus width is therefore the only major difference between these microprocessors.
• There is, however, a minor difference in one of the control signals.
• The 8086 has an 40 pins.
• The only other hardware difference appears on Pin 34 of both chips: on the 8088, it is an SSO pin,
while on the 8086, it is a pin.

3. Pin Diagram of 8086

4. Common Pins of 8086
AD7-AD0 The 8088 address/data bus lines compose the multiplexed address data bus of
the 8088
A15-A8 The 8088 address bus provides the upper-half memory address.
AD15-AD8 The 8086 address/data bus lines compose the upper multiplexed address/data
bus on the 8086.
A19/S6-
A16/S3
The address/status bus bits are multiplexed to provide address signals A19-A16
and also status bits S6-S3.
RD Whenever the read signal is a logic 0, the data bus is receptive to data from the
memory or I/O devices connected to the system.
INTR Interrupt request is used to request a hardware interrupt.
NMI The non-maskable interrupt.
RESET The reset input causes the microprocessor to reset.
CLK The clock pin provides the basic timing signal to the microprocessor.
MN / MX The minimum/maximum mode pin selects either minimum mode or maximum
mode operation for the microprocessor.
BHE/S7 The bus high enable pin is used in the 8086 to enable the most-significant data
bus bits (D15-D8) during a read or a write operation. The state of S7 is always
a logic 1.

5. Function of status bits S3 and S4.
S4 S3 Function
0 0 Extra segment
0 0 Stack segment
1 0 Code or no segment
1 1 Data segment

6. Minimum Mode Pins

7. Maximum Mode Pins

8. Status Pins
S2 S1 S0 Function
0 0 0 Interrupt acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
The status bits indicate the function of the current bus cycle.

9. Queue status

10. Physical Organization of memory
• To demultiplex the bus, 8086 provides the ALE signals to capture the address in either in 8282 or 8283 8- bit
bistable latches.
• Latches propagate the address through to the outputs while ALE is HIGH and latch the address in the falling edge
of ALE
• In 8086, address space is a sequence of one million byts in which any byte may contain an 8 – bit data element
and any two consecutive bytes contains 16 bit data element.
• The address space is physically implemented on a 16- bit data bus by dividing the address space in to 2 banks of
up to 512 k bytes.
• These banks can be selected by BHE and A0
BHE A0 Byte transferred
0 0 both bytes
0 1 upper byte to/from odd addr.
1 0 lower byte to/ from even addr.
1 1 None
• One bank is connected to D7 – D0 & even addressed byets (A0 =0)
• Other bank is connected to D15 – D8 & contains odd addr bytes (A0=1)
• Particular bytes in each bank is address by A19 – A1
• Even addressed bank is enabled by low on A0 & data bytes transferred over D0 - D7
• Odd addressed bank is enabled by low on BHE & data bytes transferred over D15 – D8
• High on BHE disables odd bank.
• High On A0 disables even bank.

11. Multiplexed address bus

12. 8086 Bus Cycle
A bus cycle is broken into four states or T periods :
During T 1 :
The address is placed on the Address/Data bus.
Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the
address onto the address bus and set the direction of data transfer on
data bus.
During T 2 :
8086 issues the RD or WR signal, DEN , and, for a write, the data.
DEN enables the memory or I/O device to receive the data for writes and the 8086
to receive the data for reads.
During T 3 :
This cycle is provided to allow memory to access data.
READY is sampled at the end of T 2 .
If low, T 3 becomes a wait state.
Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
All bus signals are deactivated, in preparation for next bus cycle.
Data is sampled for reads, writes occur for writes.

13. READY and the WAIT STATE
• READY input causes wait states for slower
memory and I/O components.
• A wait state (Tw) is an extra clocking period,
inserted between T3 & T4 that lengthens the bus
cycle.
• If one wait state is inserted, then the memory
access time is lengthened by one clocking period
(200 ns) to 660 ns, normally 460 ns with a 5 MHz
clock.
– The READY input
READY is sampled at the end T2 & during Tw

14. General Timing Diagram

15. Minimum mode 8086 system
• In a minimum mode 8086 system, the microprocessor
8086 is operated in minimum mode by strapping its
MN/MX pin to logic 1.
• In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the
minimum mode system.
• The remaining components in the system are latches, transreceivers,
clock generator, memory and I/O devices.
• The clock generator also synchronizes some external signal with
the system clock.
• It has 20 address lines and 16 data lines, the 8086 CPU requires
three octal address latches and two octal data buffers for the
complete address and data separation.

16. Minimum mode 8086 system contd.
• Latches are generally buffered output D-type flip-flops like 74LS373 or 8282.
They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by 8086.
• Transreceivers are the bidirectional buffers and some times they are called as
data amplifiers. They are required to separate the valid data from the time
multiplexed address/data signals.
• They are controlled by two signals namely, DEN and DT/R.
• The DEN signal indicates the availability of valid data over the address/data
lines. The DT/R signal indicates direction of data, i.e. from or to the processor.
• Usually, EPROM are used for monitor storage, while RAM for users program
storage. A system may contain I/O devices.

17. 8086- Minima Mode

18. Minimum mode - READ
• Hence the timing diagram can be categorized in two parts,
• the timing diagram for read cycle
• the timing diagram for write cycle.
• The read cycle begins in T1 with the assertion of address
latch enable (ALE) signal and also M / IO signal. During
the negative going edge of this signal, the valid address is
latched on the local bus.

19. Minimum mode Read Cycle
• The BHE and A0 signals address low, high or both bytes.
From T1 to T4 , the M/IO signal indicates a memory or I/O
operation.
• At T2, the address is removed from the local bus and is
sent to the output. The bus is then tristated. The read (RD)
control signal is also activated in T2.
• The read (RD) signal causes the address device to enable
its data bus drivers. After RD goes low, the valid data is
available on the data bus.
• The addressed device will drive the READY line high.
When the processor returns the read signal to high level,
the addressed device will again tristate its bus drivers.

21. Write Cycle
• A write cycle also begins with the assertion of ALE and
the emission of the address. The M/IO signal is again
asserted to indicate a memory or I/O operation. In T2, after
sending the address in T1, the processor sends the data to
be written to the addressed location.
• The data remains on the bus until middle of T4 state. The
WR becomes active at the beginning of T2 (unlike RD is
somewhat delayed in T2 to provide time for floating).
• The BHE and A0 signals are used to select the proper byte
or bytes of memory or I/O word to be read or write.
• The M/IO, RD and WR signals indicate the type of data
transfer as specified in table below.

23. Minimum mode - Write Cycle

24. Hold Response sequence
• The HOLD pin is checked at leading
edge of each clock pulse.
• If it is received active by the
processor before T4 of the previous
cycle or during T1 state of the
current cycle, the CPU activates
HLDA in the next clock cycle and
for succeeding bus cycles, the bus
will be given to another requesting
master.
• The control of the bus is not regained
by the processor until the requesting
master does not drop the HOLD pin
low.
• When the request is dropped by the
requesting master, the HLDA is
dropped by the processor at the
trailing edge of the next clock.

25. Maximum mode 8086 system
• In the maximum mode, the 8086 is operated by strapping
the MN/MX pin to ground.
• In this mode, the processor derives the status signal S2,
S1, S0. Another chip called bus controller derives the
control signal using this status information .
• In the maximum mode, there may be more than one
microprocessor in the system configuration.
• The components in the system are same as in the
minimum mode system.

26. Maximum mode Design
• The basic function of the bus controller chip IC8288,
is to derive control signals like RD and WR ( for
memory and I/O devices), DEN, DT/R, ALE etc.
using the information by the processor on the status
lines.
• The bus controller chip has input lines S2, S1, S0 and
CLK. These inputs to 8288 are driven by CPU.
• It derives the outputs ALE, DEN, DT/R, MRDC,
MWTC, AMWC, IORC, IOWC and AIOWC. The
AEN, IOB and CEN pins are specially useful for
multiprocessor systems.

27. Maximum mode contd’
AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The
significance of the MCE/PDEN output depends upon the status of the IOB pin.
• If IOB is grounded, it acts as master cascade enable to control cascade 8259A,
else it acts as peripheral data enable used in the multiple bus configurations.
• INTA pin used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device. IORC, IOWC are I/O read command and
I/O write command signals respectively . These signals enable an IO interface
to read or write the data from or to the address port.
• The MRDC, MWTC are memory read command and memory write command
signals respectively and may be used as memory read or write signals.
• All these command signals instructs the memory to accept or send data from or to
the bus.
• For both of these write command signals, the advanced signals namely AIOWC
and AMWTC are available.

29. Read Cycle

30. Write Cycle

31. RQ/GT Timings in Maximum Mode
•The request/grant response sequence
contains a series of three pulses. The
request/grant pins are checked at each
rising pulse of clock input.
• When a request is detected and if the
condition for HOLD request are satisfied,
the processor issues a grant pulse over
the RQ/GT pin immediately during T4
(current) or T1 (next) state.
• When the requesting master receives this
pulse, it accepts the control of the bus, it
sends a release pulse to the processor
using RQ/GT pin.