This document discusses different cache mapping techniques including direct mapping, associative mapping, and set-associative mapping. It provides examples of direct mapping where the main memory is divided into pages that map to cache frames. Direct mapping allows only one main memory page to map to each cache frame based on the page number. Associative mapping allows any main memory page to map to any cache frame by using a content addressable memory. Set-associative mapping groups cache frames into sets, and each main memory page can map to one of the frames within a set. The document also gives an example of how cache hit rates can be different between direct mapping, 2-way set associative mapping, and fully associative mapping.

1. UNIT IV
CACHE MEMORY
Mr. C.KARTHIKEYAN,
ASSISTANT PROFESSOR,
ECE , RMKCET

2. CACHE MAPPING TECHNIQUES
1. Direct Mapping
2. Associative Mapping
3. Set - Associative Mapping

3. DIRECT MAPPING
0
1
2
3
.
.
.
4094
4095
Main Memory
Main Memory is fragmented into pages
of equal size
Every page contains equal no of
memory location
P = 4096
16 locations
4096 x 16
212 x 24 = 216 Bit address
Page Number Page Offset
12 bits 4 bits
MAR

4. DIRECT MAPPING
0
1
2
.
.
.
127
Cache Memory
Cache Memory is fragmented into
frames of equal size
F = 128
Every frames contains equal no of
memory location
16 locations
27 x 24 = 211 Bit address
128 x 16
Frame Number Frame Offset
7 bits 4 bits

5. DIRECT MAPPING
0
1
2
3
.
.
.
4094
4095
Main Memory
0
1
2
.
.
.
127
Cache Memory

6. DIRECT MAPPING
3
1
0
31
384
129
2
4095
0 128 256 384 ..
..
..
…
3098
1 129 257 385 3099
2 130 258 386 3100
.. .. .. .. ..
127 255 383 411 4095
Main Memory
Cache
Tag
0
1
2
127
0 1 2 31
4096/128 = 32
3

7. ASSOCIATIVE /FULLY
ASSOCIATIVE MAPPING
Any Main Memory page can be loaded to any Cache Memory Frame
Tag (Page Address) W
MAR
Tag Field Cache Frame No (C)
CAM word
C W
CAM is costly (19 bits)
Multiple pages with same tag no cannot be loaded to Cache Memory

8. SET ASSOCIATIVE MAPPING
1. 2 way
2. 4 way

9. 2 WAY SET ASSOCIATIVE
MAPPING
0 64 128
…
4032
1 65 129 4033
2 66 130 4034
.. .. ..
63 127 191 4095
Main Memory
Cache
Tag
0
1
2
127
0 1 2 63
128/2 = 64
0
1
63
4096/64 = 64

10. MISSES AND ASSOCIATIVITY IN
CACHE
Assume there are three small caches, each consisting of four one-word blocks. One cache is
fully associative, a second is two-way set-associative, and the third is direct-mapped. Find the
number of misses for each cache organization given the following sequence of block
addresses: 0, 8, 0, 6, and 8.
EXAMPLE

11. DIRECT MAPPED CACHE
sequence of block addresses: 0, 8, 0, 6, and 8.
MISS Memory [0]
MISS Memory [8]
MISS Memory [0]
MISS Memory [0] Memory [6]
MISS Memory [8]

12. 2 way Set Associative Mapped Cache
sequence of block addresses: 0, 8, 0, 6, and 8.
MISS Memory [0]
MISS Memory [0] Memory [8]
HIT Memory [0] Memory [8]
MISS Memory [0] Memory [6]
MISS Memory [8] Memory [6]

13. Fully Associative Mapped Cache
sequence of block addresses: 0, 8, 0, 6, and 8.
MISS Memory [0]
MISS Memory [0] Memory [8]
HIT Memory [0] Memory [8]
MISS Memory [0] Memory [8] Memory [6]
HIT Memory [0] Memory [8] Memory [6]

14. CACHE READ & WRITE POLICIES

15. HIT RATIO & EFFECTIVE ACCESS
TIME