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1996-CUG-presentation_nonblocking_assigns.pdf

This document summarizes a presentation on understanding blocking and non-blocking assignments in Verilog. The key points are: - Blocking assignments evaluate and assign in a single step, blocking further execution until complete. Non-blocking assignments evaluate immediately but assign later. - Procedural assignments can be modeled as sequential (determinate order) or concurrent (indeterminate order). - Simulation time is divided into queues for evaluating different statement types. Blocking assigns in Q1, non-blocking assigns in Q2. - Timing controls like # delays can postpone when an assignment is evaluated or assigned, allowing non-blocking assignments even in sequential blocks.

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Understanding Verilog Blocking Understanding Verilog Blocking and Non and Non- -blocking Assignments blocking Assignments International Cadence International Cadence User Group Conference User Group Conference September 11, 1996 September 11, 1996 presented by presented by Stuart Sutherland Stuart Sutherland Sutherland HDL Consulting Sutherland HDL Consulting
About the Presenter About the Presenter Stuart Sutherland has over 8 years of experience using Verilog w Stuart Sutherland has over 8 years of experience using Verilog with a variety of software tools. He ith a variety of software tools. He holds a BS degree in Computer Science, with an emphasis on Elect holds a BS degree in Computer Science, with an emphasis on Electronic Engineering, and has ronic Engineering, and has worked as a design engineer in the defense industry, and as an A worked as a design engineer in the defense industry, and as an Applications Engineer for Gateway pplications Engineer for Gateway Design Automation (the originator of Verilog) and Cadence Design Design Automation (the originator of Verilog) and Cadence Design Systems. Mr. Sutherland has Systems. Mr. Sutherland has been providing Verilog HDL consulting services since 1991. As a been providing Verilog HDL consulting services since 1991. As a consultant, he has been actively consultant, he has been actively involved in using the Verilog involved in using the Verilog langiage langiage with a many different of software tools for the design of with a many different of software tools for the design of ASICs ASICs and systems. He is a member of the IEEE 1364 standards committ and systems. He is a member of the IEEE 1364 standards committee and has been involved ee and has been involved in the specification and testing of Verilog simulation products in the specification and testing of Verilog simulation products from several EDA vendors, including from several EDA vendors, including the Intergraph the Intergraph- -VeriBest VeriBest VeriBest VeriBest simulator, the Mentor simulator, the Mentor QuickHDL QuickHDL simulator, and the Frontline simulator, and the Frontline CycleDrive CycleDrive cycle based simulator. In addition to Verilog design cycle based simulator. In addition to Verilog design consutlting consutlting, Mr. Sutherland , Mr. Sutherland provides expert on provides expert on- -site Verilog training on the Verilog HDL language and site Verilog training on the Verilog HDL language and Programing Programing Language Language Interface. Mr. Sutherland is the author and publisher of the po Interface. Mr. Sutherland is the author and publisher of the popular pular “Verilog IEEE 1364 Quick “Verilog IEEE 1364 Quick Reference Guide” Reference Guide” and the and the “Verilog IEEE 1364 PLI Quick Reference Guide” “Verilog IEEE 1364 PLI Quick Reference Guide”. . Please Please conact conact Mr. Sutherland with any questions about this material! Mr. Sutherland with any questions about this material! phone: (503) 692 phone: (503) 692- -0898 0898 fax: (503) 692 fax: (503) 692- -1512 1512 e e- -mail: mail: stuart stuart@ @sutherland sutherland.com .com Sutherland HDL Consulting Sutherland HDL Consulting Verilog Consulting and Training Services Verilog Consulting and Training Services 22805 SW 92 22805 SW 92nd nd Place Place Tualatin, OR 97062 USA Tualatin, OR 97062 USA
The material in this presentation is copyrighted by Sutherland H The material in this presentation is copyrighted by Sutherland HDL Consulting, DL Consulting, Tualatin, Oregon. The presentation is printed with permission a Tualatin, Oregon. The presentation is printed with permission as part of the s part of the proceedings of the 1996 International Cadence User Group Confere proceedings of the 1996 International Cadence User Group Conference. All rights nce. All rights are reserved. No material from this presentation may be duplica are reserved. No material from this presentation may be duplicated or transmitted by ted or transmitted by any means or in any form without the express written permission any means or in any form without the express written permission of Sutherland HDL of Sutherland HDL Consulting. Consulting. copyright notice copyright notice Sutherland HDL Consulting Sutherland HDL Consulting 22805 SW 92 22805 SW 92 nd nd Place Place Tualatin, OR 97062 USA Tualatin, OR 97062 USA phone: (503) 692 phone: (503) 692- -0898 0898 fax: (503) 692 fax: (503) 692- -1512 1512 e e- -mail: info@ mail: info@sutherland sutherland.com .com © ©1996 1996
4 4 Sutherland Sutherland Sutherland H H H D D D L L L Objectives Objectives Objectives ➤ ➤ The primary objective is to understand: The primary objective is to understand: What type of hardware is represented What type of hardware is represented by blocking and non by blocking and non- -blocking blocking assignments? assignments? ➤ ➤ The material presented is a subset of an advanced Verilog The material presented is a subset of an advanced Verilog HDL training course HDL training course
5 5 Sutherland Sutherland Sutherland H H H D D D L L L Procedural Assignments Procedural Assignments Procedural Assignments ➤ ➤ Procedural assignment evaluation can be modeled as: Procedural assignment evaluation can be modeled as: ➤ ➤ Blocking Blocking ➤ ➤ Non Non- -blocking blocking ➤ ➤ Procedural assignment execution can be modeled as: Procedural assignment execution can be modeled as: ➤ ➤ Sequential Sequential ➤ ➤ Concurrent Concurrent ➤ ➤ Procedural assignment timing controls can be modeled as: Procedural assignment timing controls can be modeled as: ➤ ➤ Delayed evaluations Delayed evaluations ➤ ➤ Delayed assignments Delayed assignments
6 6 Sutherland Sutherland Sutherland H H H D D D L L L Blocking Procedural Assignments Blocking Blocking Procedural Assignments Procedural Assignments ➤ ➤ The The = = token represents a token represents a blocking blocking procedural assignment procedural assignment ➤ ➤ Evaluated and assigned in a single step Evaluated and assigned in a single step ➤ ➤ Execution flow within the procedure is blocked until the Execution flow within the procedure is blocked until the assignment is completed assignment is completed ➤ ➤ Evaluations of concurrent statements in the same time step Evaluations of concurrent statements in the same time step are blocked until the assignment is completed are blocked until the assignment is completed These examples will These examples will not not work work   Why not? Why not? //swap bytes in word always @(posedge clk) begin word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; end //swap bytes in word always @(posedge clk) begin word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; end //swap bytes in word always @(posedge clk) fork word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; join //swap bytes in word always @(posedge clk) fork word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; join
7 7 Sutherland Sutherland Sutherland H H H D D D L L L Non-Blocking Procedural Assignments Non Non- -Blocking Blocking Procedural Assignments Procedural Assignments ➤ ➤ The The <= <= token represents a token represents a non non- -blocking blocking assignment assignment ➤ ➤ Evaluated and assigned in two steps: Evaluated and assigned in two steps: ① ① The right The right- -hand side is evaluated immediately hand side is evaluated immediately ② ② The assignment to the left The assignment to the left- -hand side is postponed until hand side is postponed until other evaluations in the current time step are completed other evaluations in the current time step are completed ➤ ➤ Execution flow within the procedure continues until a Execution flow within the procedure continues until a timing control is encountered (flow is not blocked) timing control is encountered (flow is not blocked) These examples will work These examples will work   Why? Why? //swap bytes in word always @(posedge clk) begin word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; end //swap bytes in word always @(posedge clk) begin word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; end //swap bytes in word always @(posedge clk) fork word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; join //swap bytes in word always @(posedge clk) fork word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; join
8 8 Sutherland Sutherland Sutherland H H H D D D L L L Representing Simulation Time as Queues Representing Representing Simulation Time as Queues Simulation Time as Queues ➤ ➤ Each Verilog simulation time step is divided into 4 queues Each Verilog simulation time step is divided into 4 queues Note: this is an abstract view, not how simulation algorithms ar Note: this is an abstract view, not how simulation algorithms are implemented e implemented Time 0: ➤ Q1 — (in any order) : ➤ Evaluate RHS of all non-blocking assignments ➤ Evaluate RHS and change LHS of all blocking assignments ➤ Evaluate RHS and change LHS of all continuous assignments ➤ Evaluate inputs and change outputs of all primitives ➤ Evaluate and print output from $display and $write ➤ Q2 — (in any order) : ➤ Change LHS of all non-blocking assignments ➤ Q3 — (in any order) : ➤ Evaluate and print output from $monitor and $strobe ➤ Call PLI with reason_synchronize ➤ Q4 : ➤ Call PLI with reason_rosynchronize Time 1: ... Time 0: ➤ Q1 — (in any order) : ➤ Evaluate RHS of all non-blocking assignments ➤ Evaluate RHS and change LHS of all blocking assignments ➤ Evaluate RHS and change LHS of all continuous assignments ➤ Evaluate inputs and change outputs of all primitives ➤ Evaluate and print output from $display and $write ➤ Q2 — (in any order) : ➤ Change LHS of all non-blocking assignments ➤ Q3 — (in any order) : ➤ Evaluate and print output from $monitor and $strobe ➤ Call PLI with reason_synchronize ➤ Q4 : ➤ Call PLI with reason_rosynchronize Time 1: ...
9 9 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Procedural Assignments Sequential Sequential Procedural Assignments Procedural Assignments ➤ ➤ The order of evaluation is The order of evaluation is determinate determinate ➤ ➤ A A sequential blocking assignment sequential blocking assignment evaluates and assigns evaluates and assigns before continuing on in the procedure before continuing on in the procedure always @( always @(posedge clk posedge clk) ) begin begin A A = = 1; 1; #5 B #5 B = = A + 1; A + 1; end end evaluate and assign A immediately evaluate and assign A immediately delay 5 time units, then evaluate and assign delay 5 time units, then evaluate and assign ➤ ➤ A A sequential non sequential non- -blocking assignment blocking assignment evaluates, then evaluates, then continues on to the next timing control before assigning continues on to the next timing control before assigning always @( always @(posedge clk posedge clk) ) begin begin A A <= <= 1; 1; #5 B #5 B <= <= A + 1; A + 1; end end evaluate A immediately; assign at end of time step evaluate A immediately; assign at end of time step delay 5 time units, then evaluate; then assign at delay 5 time units, then evaluate; then assign at end of time step (clock + 5) end of time step (clock + 5)
10 10 Sutherland Sutherland Sutherland H H H D D D L L L Concurrent Procedural Assignments Concurrent Concurrent Procedural Assignments Procedural Assignments The order of concurrent evaluation is The order of concurrent evaluation is indeterminate indeterminate ➤ ➤ Concurrent Concurrent blocking assignments blocking assignments have have unpredictable results unpredictable results always @( always @(posedge clk posedge clk) ) #5 A #5 A = = A + 1; A + 1; always @( always @(posedge clk posedge clk) ) #5 B #5 B = = A + 1; A + 1; Unpredictable Result: Unpredictable Result: (new value of (new value of B B could be evaluated before could be evaluated before or after or after A A changes) changes) ➤ ➤ Concurrent Concurrent non non- -blocking assignments blocking assignments have have predictable results predictable results always @( always @(posedge clk posedge clk) ) #5 A #5 A <= <= A + 1; A + 1; always @( always @(posedge clk posedge clk) ) #5 B #5 B <= <= A + 1; A + 1; Predictable Result: Predictable Result: (new value of (new value of B B will always be evaluated will always be evaluated before before A A changes) changes)
11 11 Sutherland Sutherland Sutherland H H H D D D L L L Delayed Evaluation Procedural Assignments Delayed Evaluation Delayed Evaluation Procedural Assignments Procedural Assignments ➤ ➤ A timing control before an assignment statement will postpone A timing control before an assignment statement will postpone when the next assignment is evaluated when the next assignment is evaluated ➤ ➤ Evaluation is delayed for the amount of time specified Evaluation is delayed for the amount of time specified begin begin #5 #5 A A = = 1; 1; #5 #5 A A = = A + 1; A + 1; B B = = A + 1; A + 1; end end delay for 5, then evaluate and assign delay for 5, then evaluate and assign delay 5 more, then evaluate and assign delay 5 more, then evaluate and assign no delay; evaluate and assign no delay; evaluate and assign What values do A and B contain after 10 time units? What values do A and B contain after 10 time units?
12 12 Sutherland Sutherland Sutherland H H H D D D L L L Delayed Assignment Procedural Assignments Delayed Assignment Delayed Assignment Procedural Assignments Procedural Assignments ➤ ➤ An An intra intra- -assignment delay assignment delay places the timing control places the timing control after after the the assignment token assignment token ➤ ➤ The right The right- -hand side is evaluated before the delay hand side is evaluated before the delay ➤ ➤ The left The left- -hand side is assigned after the delay hand side is assigned after the delay always @(A) always @(A) B B = = #5 #5 A; A; A A is evaluated at the time it changes, but is evaluated at the time it changes, but is not assigned to is not assigned to B B until after 5 time units until after 5 time units always @( always @(negedge clk negedge clk) ) Q Q <= <= @( @(posedge clk posedge clk) ) D; D; D D is evaluated at the negative edge of is evaluated at the negative edge of CLK CLK, , Q Q is changed on the positive edge of is changed on the positive edge of CLK CLK always @(instructor_input) if (morning) understand = instructor_input; else if (afternoon) understand = #5 instructor_input; else if (lunch_time) understand = wait (!lunch_time) instructor_input; always @(instructor_input) if (morning) understand = instructor_input; else if (afternoon) understand = #5 instructor_input; else if (lunch_time) understand = wait (!lunch_time) instructor_input;
13 13 Sutherland Sutherland Sutherland H H H D D D L L L Intra-Assignment Delays With Repeat Loops Intra Intra- -Assignment Delays Assignment Delays With Repeat Loops With Repeat Loops ➤ ➤ An edge An edge- -sensitive intra sensitive intra- -assignment timing control permits a assignment timing control permits a special use of the repeat loop special use of the repeat loop ➤ ➤ The edge sensitive time control may be repeated several The edge sensitive time control may be repeated several times before the delay is completed times before the delay is completed ➤ ➤ Either the blocking or the non Either the blocking or the non- -blocking assignment may be blocking assignment may be used used always @(IN) OUT <= repeat (8) @(posedge clk) IN; always @(IN) OUT <= repeat (8) @(posedge clk) IN; The value of IN is evaluated when it changes, but is not assigned to OUT until after 8 clock cycles
14 14 Sutherland Sutherland Sutherland H H H D D D L L L Choosing the Correct Procedural Assignment Choosing the Choosing the Correct Procedural Assignment Correct Procedural Assignment ➤ ➤ Which procedural assignment should be used to model a Which procedural assignment should be used to model a combinatorial logic buffer? combinatorial logic buffer? ➤ ➤ Which procedural assignment should be used to model a Which procedural assignment should be used to model a sequential logic flip sequential logic flip- -flop? flop? ➤ ➤ The following pages will answer these questions The following pages will answer these questions always @(in) #5 out = in; always @(in) #5 out <= in; always @(in) out = #5 in; always @(in) out <= #5 in; always @(posedge clk) #5 q = d; always @(posedge clk) #5 q <= d; always @(posedge clk) q = #5 d; always @(posedge clk) q <= #5 d;
15 15 Sutherland Sutherland Sutherland H H H D D D L L L Transition Propagation Methods Transition Transition Propagation Methods Propagation Methods ➤ ➤ Hardware has two primary propagation delay methods: Hardware has two primary propagation delay methods: ➤ ➤ Inertial delay Inertial delay models devices with finite switching speeds; models devices with finite switching speeds; input glitches do not propagate to the output input glitches do not propagate to the output ➤ ➤ Transport delay Transport delay models devices with near infinite models devices with near infinite switching speeds; input glitches propagate to the output switching speeds; input glitches propagate to the output 20 60 50 40 30 10 20 60 50 40 30 10 Buffer with a 10 nanosecond propagation delay 20 60 50 40 30 10 20 60 50 40 30 10 Buffer with a 10 nanosecond propagation delay
16 16 Sutherland Sutherland Sutherland H H H D D D L L L Combinational Logic Procedural Assignments Combinational Logic Combinational Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? 20 60 50 40 30 10 in in 33 33 36 36 45 45 always @(in) always @(in) o1 o1 = = in; in; Blocking, Blocking, No delay No delay always @(in) always @(in) o2 o2 <= <= in; in; Non Non- -blocking, blocking, No delay No delay always @(in) always @(in) #5 #5 o3 o3 = = in; in; Blocking, Blocking, Delayed evaluation Delayed evaluation o1 o1 o2 o2 o3 o3 o4 o4 o5 o5 o6 o6 always @(in) always @(in) #5 #5 o4 o4 <= <= in; in; Non Non- -blocking, blocking, Delayed evaluation Delayed evaluation always @(in) always @(in) o5 o5 = #5 = #5 in; in; Blocking, Blocking, Delayed assignment Delayed assignment always @(in) always @(in) o6 o6 <= #5 <= #5 in; in; Non Non- -blocking, blocking, Delayed assignment Delayed assignment zero delay zero delay inertial inertial transport transport
17 17 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic Procedural Assignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Sequential assignments Sequential assignments ➤ ➤ No delays No delays 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) begin begin y1 y1 = = in; in; y2 y2 = = y1; y1; end end always @( always @(posedge clk posedge clk) ) begin begin y1 y1 <= <= in; in; y2 y2 <= <= y1; y1; end end in 35 53 y2 y1 y1 y2 y2 y1 parallel flip parallel flip- -flops flops y1 y2 shift shift- -register with zero delays register with zero delays
18 18 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic Procedural Assignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Sequential assignments Sequential assignments ➤ ➤ Delayed evaluation Delayed evaluation 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) begin begin #5 #5 y1 y1 = = in; in; #5 #5 y2 y2 = = y1; y1; end end always @( always @(posedge clk posedge clk) ) begin begin #5 #5 y1 y1 <= <= in; in; #5 #5 y2 y2 <= <= y1; y1; end end in 35 53 y2 y1 y1 y2 ? ? ? ? ? ? y1 y2 #5 #5 shift register with delayed clocks shift register with delayed clocks ? ? ? ? ? ? y1 y2 #5 #5 shift register with delayed clocks shift register with delayed clocks
19 19 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic Procedural Assignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Sequential assignments Sequential assignments ➤ ➤ Delayed assignment Delayed assignment 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) begin begin y1 y1 = #5 = #5 in; in; y2 y2 = #5 = #5 y1; y1; end end always @( always @(posedge clk posedge clk) ) begin begin y1 y1 <= #5 <= #5 in; in; y2 y2 <= #5 <= #5 y1; y1; end end y1 y2 y1 y2 in 35 53 shift register delayed clock on second stage shift register delayed clock on second stage y1 y2 #5 #5 #5 y1 y2 #5 #5 shift register with delays shift register with delays
20 20 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic Procedural Assignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Concurrent assignments Concurrent assignments ➤ ➤ No delays No delays y1 y2 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) y1 y1 = = in; in; always @( always @(posedge clk posedge clk) ) y2 y2 = = y1; y1; y1 y2 always @( always @(posedge clk posedge clk) ) y1 y1 <= <= in; in; always @( always @(posedge clk posedge clk) ) y2 y2 <= <= y1; y1; in 35 53 ? ? ? ? ? ? ? ? y1 y2 ? shift register with race condition shift register with race condition y1 y2 shift shift- -register with zero delays register with zero delays
21 21 Sutherland Sutherland Sutherland H H H D D D L L L y2 y1 Sequential Logic Procedural Assignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Concurrent assignments Concurrent assignments ➤ ➤ Delayed evaluation Delayed evaluation 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) #5 #5 y1 y1 = = in; in; always @( always @(posedge clk posedge clk) ) #5 #5 y2 y2 = = y1; y1; always @( always @(posedge clk posedge clk) ) #5 #5 y1 y1 <= <= in; in; always @( always @(posedge clk posedge clk) ) #5 #5 y2 y2 <= <= y1; y1; in 35 53 y1 y2 ? ? ? ? ? ? ? ? ? ? shift register with race condition shift register with race condition y1 y2 ? #5 #5 ? ? ? ? y1 y2 #5 shift register with race condition shift register with race condition
22 22 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic Procedural Assignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Concurrent assignments Concurrent assignments ➤ ➤ Delayed assignment Delayed assignment 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) y1 y1 = #5 = #5 in; in; always @( always @(posedge clk posedge clk) ) y2 y2 = #5 = #5 y1; y1; always @( always @(posedge clk posedge clk) ) y1 y1 <= #5 <= #5 in; in; always @( always @(posedge clk posedge clk) ) y2 y2 <= #5 <= #5 y1; y1; in 35 53 y1 y2 y1 y2 y1 y2 #5 #5 shift register, delay must be < clock period shift register, delay must be < clock period y1 y2 #5 #5 shift register with delays shift register with delays
23 23 Sutherland Sutherland Sutherland H H H D D D L L L Rules of Thumb for Procedural Assignments Rules of Thumb for Rules of Thumb for Procedural Assignments Procedural Assignments ➤ ➤ Combinational Logic: Combinational Logic: ➤ ➤ No delays: No delays: Use blocking assignments ( Use blocking assignments ( a = b; a = b; ) ) ➤ ➤ Inertial delays: Inertial delays: Use delayed evaluation blocking Use delayed evaluation blocking assignments ( assignments ( #5 a = b; #5 a = b; ) ) ➤ ➤ Transport delays: Transport delays: Use delayed assignment non Use delayed assignment non- -blocking blocking assignments ( assignments ( a <= #5 b; a <= #5 b; ) ) ➤ ➤ Sequential Logic: Sequential Logic: ➤ ➤ No delays: No delays: Use non Use non- -blocking assignments ( blocking assignments ( q <= d; q <= d; ) ) ➤ ➤ With delays: With delays: Use delayed assignment non Use delayed assignment non- -blocking blocking assignments ( assignments ( q <= #5 d; q <= #5 d; ) )
24 24 Sutherland Sutherland Sutherland H H H D D D L L L An Exception to Non-blocking Assignments in Sequential Logic An Exception to Non An Exception to Non- -blocking blocking Assignments in Sequential Logic Assignments in Sequential Logic ➤ ➤ Do Do not not use a non use a non- -blocking assignment if another statement in blocking assignment if another statement in the procedure requires the new value in the same time step the procedure requires the new value in the same time step begin #5 A <= 1; #5 A <= A + 1; B <= A + 1; end What values do A and B contain after 10 time units? What values do A and B contain after 10 time units? always @(posedge clk) begin case (state) `STOP: next_state <= `GO; `GO: next_state <= `STOP; endcase state <= next_state; end Assume state and next_state are `STOP at the first clock, what is state: - At the 2nd clock? - At the 3rd clock? - At the 4th clock? - At the 5th clock? Assume state and next_state are `STOP at the first clock, what is state: - At the 2nd clock? - At the 3rd clock? - At the 4th clock? - At the 5th clock? A is 2 A is 2 B is 2 B is 2 `STOP `STOP `GO `GO `GO `GO `STOP `STOP
25 25 Sutherland Sutherland Sutherland H H H D D D L L L Exercise 3: Procedural Assignments Exercise 3: Exercise 3: Procedural Assignments Procedural Assignments ➤ ➤ Write a procedure for an adder (combinational logic) that Write a procedure for an adder (combinational logic) that assigns C the sum of A plus B with a 7ns propagation delay. assigns C the sum of A plus B with a 7ns propagation delay. ➤ ➤ Write the procedure(s) for a 4 Write the procedure(s) for a 4- -bit wide shift register (positive bit wide shift register (positive edge triggered) of clock and has a 4ns propagation delay. edge triggered) of clock and has a 4ns propagation delay. always @(A or B) #7 C = A + B; always @(A or B) #7 C = A + B; always @(posedge clk) begin y1 <= #4 in; y2 <= #4 y1; y3 <= #4 y2; out <= #4 y3; end always @(posedge clk) begin y1 <= #4 in; y2 <= #4 y1; y3 <= #4 y2; out <= #4 y3; end always @(posedge clk) y1 <= #4 in; always @(posedge clk) y2 <= #4 y1; always @(posedge clk) y3 <= #4 y2; always @(posedge clk) out <= #4 y3; always @(posedge clk) y1 <= #4 in; always @(posedge clk) y2 <= #4 y1; always @(posedge clk) y3 <= #4 y2; always @(posedge clk) out <= #4 y3;
26 26 Sutherland Sutherland Sutherland H H H D D D L L L Exercise 3 (continued): Procedural Assignments Exercise 3 (continued): Exercise 3 (continued): Procedural Assignments Procedural Assignments ➤ ➤ Write a Verilog procedure for a “black box” ALU pipeline that Write a Verilog procedure for a “black box” ALU pipeline that takes 8 clock cycles to execute an instruction. The pipeline takes 8 clock cycles to execute an instruction. The pipeline triggers on the positive edge of clock. The “black box” is triggers on the positive edge of clock. The “black box” is represented as call to a function named ALU with inputs A, B represented as call to a function named ALU with inputs A, B and OPCODE. and OPCODE. always @(posedge clk) alu_out <= repeat(7) @(posedge clk) ALU(A,B,OPCODE); always @(posedge clk) alu_out <= repeat(7) @(posedge clk) ALU(A,B,OPCODE); How many Verilog statements does it take to model an eight stage pipeline?

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1996-CUG-presentation_nonblocking_assigns.pdf

  • 1.
    Understanding Verilog Blocking UnderstandingVerilog Blocking and Non and Non- -blocking Assignments blocking Assignments International Cadence International Cadence User Group Conference User Group Conference September 11, 1996 September 11, 1996 presented by presented by Stuart Sutherland Stuart Sutherland Sutherland HDL Consulting Sutherland HDL Consulting
  • 2.
    About the Presenter Aboutthe Presenter Stuart Sutherland has over 8 years of experience using Verilog w Stuart Sutherland has over 8 years of experience using Verilog with a variety of software tools. He ith a variety of software tools. He holds a BS degree in Computer Science, with an emphasis on Elect holds a BS degree in Computer Science, with an emphasis on Electronic Engineering, and has ronic Engineering, and has worked as a design engineer in the defense industry, and as an A worked as a design engineer in the defense industry, and as an Applications Engineer for Gateway pplications Engineer for Gateway Design Automation (the originator of Verilog) and Cadence Design Design Automation (the originator of Verilog) and Cadence Design Systems. Mr. Sutherland has Systems. Mr. Sutherland has been providing Verilog HDL consulting services since 1991. As a been providing Verilog HDL consulting services since 1991. As a consultant, he has been actively consultant, he has been actively involved in using the Verilog involved in using the Verilog langiage langiage with a many different of software tools for the design of with a many different of software tools for the design of ASICs ASICs and systems. He is a member of the IEEE 1364 standards committ and systems. He is a member of the IEEE 1364 standards committee and has been involved ee and has been involved in the specification and testing of Verilog simulation products in the specification and testing of Verilog simulation products from several EDA vendors, including from several EDA vendors, including the Intergraph the Intergraph- -VeriBest VeriBest VeriBest VeriBest simulator, the Mentor simulator, the Mentor QuickHDL QuickHDL simulator, and the Frontline simulator, and the Frontline CycleDrive CycleDrive cycle based simulator. In addition to Verilog design cycle based simulator. In addition to Verilog design consutlting consutlting, Mr. Sutherland , Mr. Sutherland provides expert on provides expert on- -site Verilog training on the Verilog HDL language and site Verilog training on the Verilog HDL language and Programing Programing Language Language Interface. Mr. Sutherland is the author and publisher of the po Interface. Mr. Sutherland is the author and publisher of the popular pular “Verilog IEEE 1364 Quick “Verilog IEEE 1364 Quick Reference Guide” Reference Guide” and the and the “Verilog IEEE 1364 PLI Quick Reference Guide” “Verilog IEEE 1364 PLI Quick Reference Guide”. . Please Please conact conact Mr. Sutherland with any questions about this material! Mr. Sutherland with any questions about this material! phone: (503) 692 phone: (503) 692- -0898 0898 fax: (503) 692 fax: (503) 692- -1512 1512 e e- -mail: mail: stuart stuart@ @sutherland sutherland.com .com Sutherland HDL Consulting Sutherland HDL Consulting Verilog Consulting and Training Services Verilog Consulting and Training Services 22805 SW 92 22805 SW 92nd nd Place Place Tualatin, OR 97062 USA Tualatin, OR 97062 USA
  • 3.
    The material inthis presentation is copyrighted by Sutherland H The material in this presentation is copyrighted by Sutherland HDL Consulting, DL Consulting, Tualatin, Oregon. The presentation is printed with permission a Tualatin, Oregon. The presentation is printed with permission as part of the s part of the proceedings of the 1996 International Cadence User Group Confere proceedings of the 1996 International Cadence User Group Conference. All rights nce. All rights are reserved. No material from this presentation may be duplica are reserved. No material from this presentation may be duplicated or transmitted by ted or transmitted by any means or in any form without the express written permission any means or in any form without the express written permission of Sutherland HDL of Sutherland HDL Consulting. Consulting. copyright notice copyright notice Sutherland HDL Consulting Sutherland HDL Consulting 22805 SW 92 22805 SW 92 nd nd Place Place Tualatin, OR 97062 USA Tualatin, OR 97062 USA phone: (503) 692 phone: (503) 692- -0898 0898 fax: (503) 692 fax: (503) 692- -1512 1512 e e- -mail: info@ mail: info@sutherland sutherland.com .com © ©1996 1996
  • 4.
    4 4 Sutherland Sutherland Sutherland H H H D D D L L L Objectives Objectives Objectives ➤ ➤ Theprimary objective is to understand: The primary objective is to understand: What type of hardware is represented What type of hardware is represented by blocking and non by blocking and non- -blocking blocking assignments? assignments? ➤ ➤ The material presented is a subset of an advanced Verilog The material presented is a subset of an advanced Verilog HDL training course HDL training course
  • 5.
    5 5 Sutherland Sutherland Sutherland H H H D D D L L L Procedural Assignments ProceduralAssignments Procedural Assignments ➤ ➤ Procedural assignment evaluation can be modeled as: Procedural assignment evaluation can be modeled as: ➤ ➤ Blocking Blocking ➤ ➤ Non Non- -blocking blocking ➤ ➤ Procedural assignment execution can be modeled as: Procedural assignment execution can be modeled as: ➤ ➤ Sequential Sequential ➤ ➤ Concurrent Concurrent ➤ ➤ Procedural assignment timing controls can be modeled as: Procedural assignment timing controls can be modeled as: ➤ ➤ Delayed evaluations Delayed evaluations ➤ ➤ Delayed assignments Delayed assignments
  • 6.
    6 6 Sutherland Sutherland Sutherland H H H D D D L L L Blocking Procedural Assignments Blocking Blocking ProceduralAssignments Procedural Assignments ➤ ➤ The The = = token represents a token represents a blocking blocking procedural assignment procedural assignment ➤ ➤ Evaluated and assigned in a single step Evaluated and assigned in a single step ➤ ➤ Execution flow within the procedure is blocked until the Execution flow within the procedure is blocked until the assignment is completed assignment is completed ➤ ➤ Evaluations of concurrent statements in the same time step Evaluations of concurrent statements in the same time step are blocked until the assignment is completed are blocked until the assignment is completed These examples will These examples will not not work work   Why not? Why not? //swap bytes in word always @(posedge clk) begin word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; end //swap bytes in word always @(posedge clk) begin word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; end //swap bytes in word always @(posedge clk) fork word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; join //swap bytes in word always @(posedge clk) fork word[15:8] = word[ 7:0]; word[ 7:0] = word[15:8]; join
  • 7.
    7 7 Sutherland Sutherland Sutherland H H H D D D L L L Non-Blocking Procedural Assignments Non Non- -Blocking Blocking ProceduralAssignments Procedural Assignments ➤ ➤ The The <= <= token represents a token represents a non non- -blocking blocking assignment assignment ➤ ➤ Evaluated and assigned in two steps: Evaluated and assigned in two steps: ① ① The right The right- -hand side is evaluated immediately hand side is evaluated immediately ② ② The assignment to the left The assignment to the left- -hand side is postponed until hand side is postponed until other evaluations in the current time step are completed other evaluations in the current time step are completed ➤ ➤ Execution flow within the procedure continues until a Execution flow within the procedure continues until a timing control is encountered (flow is not blocked) timing control is encountered (flow is not blocked) These examples will work These examples will work   Why? Why? //swap bytes in word always @(posedge clk) begin word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; end //swap bytes in word always @(posedge clk) begin word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; end //swap bytes in word always @(posedge clk) fork word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; join //swap bytes in word always @(posedge clk) fork word[15:8] <= word[ 7:0]; word[ 7:0] <= word[15:8]; join
  • 8.
    8 8 Sutherland Sutherland Sutherland H H H D D D L L L Representing Simulation Timeas Queues Representing Representing Simulation Time as Queues Simulation Time as Queues ➤ ➤ Each Verilog simulation time step is divided into 4 queues Each Verilog simulation time step is divided into 4 queues Note: this is an abstract view, not how simulation algorithms ar Note: this is an abstract view, not how simulation algorithms are implemented e implemented Time 0: ➤ Q1 — (in any order) : ➤ Evaluate RHS of all non-blocking assignments ➤ Evaluate RHS and change LHS of all blocking assignments ➤ Evaluate RHS and change LHS of all continuous assignments ➤ Evaluate inputs and change outputs of all primitives ➤ Evaluate and print output from $display and $write ➤ Q2 — (in any order) : ➤ Change LHS of all non-blocking assignments ➤ Q3 — (in any order) : ➤ Evaluate and print output from $monitor and $strobe ➤ Call PLI with reason_synchronize ➤ Q4 : ➤ Call PLI with reason_rosynchronize Time 1: ... Time 0: ➤ Q1 — (in any order) : ➤ Evaluate RHS of all non-blocking assignments ➤ Evaluate RHS and change LHS of all blocking assignments ➤ Evaluate RHS and change LHS of all continuous assignments ➤ Evaluate inputs and change outputs of all primitives ➤ Evaluate and print output from $display and $write ➤ Q2 — (in any order) : ➤ Change LHS of all non-blocking assignments ➤ Q3 — (in any order) : ➤ Evaluate and print output from $monitor and $strobe ➤ Call PLI with reason_synchronize ➤ Q4 : ➤ Call PLI with reason_rosynchronize Time 1: ...
  • 9.
    9 9 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Procedural Assignments Sequential Sequential ProceduralAssignments Procedural Assignments ➤ ➤ The order of evaluation is The order of evaluation is determinate determinate ➤ ➤ A A sequential blocking assignment sequential blocking assignment evaluates and assigns evaluates and assigns before continuing on in the procedure before continuing on in the procedure always @( always @(posedge clk posedge clk) ) begin begin A A = = 1; 1; #5 B #5 B = = A + 1; A + 1; end end evaluate and assign A immediately evaluate and assign A immediately delay 5 time units, then evaluate and assign delay 5 time units, then evaluate and assign ➤ ➤ A A sequential non sequential non- -blocking assignment blocking assignment evaluates, then evaluates, then continues on to the next timing control before assigning continues on to the next timing control before assigning always @( always @(posedge clk posedge clk) ) begin begin A A <= <= 1; 1; #5 B #5 B <= <= A + 1; A + 1; end end evaluate A immediately; assign at end of time step evaluate A immediately; assign at end of time step delay 5 time units, then evaluate; then assign at delay 5 time units, then evaluate; then assign at end of time step (clock + 5) end of time step (clock + 5)
  • 10.
    10 10 Sutherland Sutherland Sutherland H H H D D D L L L Concurrent Procedural Assignments Concurrent Concurrent ProceduralAssignments Procedural Assignments The order of concurrent evaluation is The order of concurrent evaluation is indeterminate indeterminate ➤ ➤ Concurrent Concurrent blocking assignments blocking assignments have have unpredictable results unpredictable results always @( always @(posedge clk posedge clk) ) #5 A #5 A = = A + 1; A + 1; always @( always @(posedge clk posedge clk) ) #5 B #5 B = = A + 1; A + 1; Unpredictable Result: Unpredictable Result: (new value of (new value of B B could be evaluated before could be evaluated before or after or after A A changes) changes) ➤ ➤ Concurrent Concurrent non non- -blocking assignments blocking assignments have have predictable results predictable results always @( always @(posedge clk posedge clk) ) #5 A #5 A <= <= A + 1; A + 1; always @( always @(posedge clk posedge clk) ) #5 B #5 B <= <= A + 1; A + 1; Predictable Result: Predictable Result: (new value of (new value of B B will always be evaluated will always be evaluated before before A A changes) changes)
  • 11.
    11 11 Sutherland Sutherland Sutherland H H H D D D L L L Delayed Evaluation ProceduralAssignments Delayed Evaluation Delayed Evaluation Procedural Assignments Procedural Assignments ➤ ➤ A timing control before an assignment statement will postpone A timing control before an assignment statement will postpone when the next assignment is evaluated when the next assignment is evaluated ➤ ➤ Evaluation is delayed for the amount of time specified Evaluation is delayed for the amount of time specified begin begin #5 #5 A A = = 1; 1; #5 #5 A A = = A + 1; A + 1; B B = = A + 1; A + 1; end end delay for 5, then evaluate and assign delay for 5, then evaluate and assign delay 5 more, then evaluate and assign delay 5 more, then evaluate and assign no delay; evaluate and assign no delay; evaluate and assign What values do A and B contain after 10 time units? What values do A and B contain after 10 time units?
  • 12.
    12 12 Sutherland Sutherland Sutherland H H H D D D L L L Delayed Assignment ProceduralAssignments Delayed Assignment Delayed Assignment Procedural Assignments Procedural Assignments ➤ ➤ An An intra intra- -assignment delay assignment delay places the timing control places the timing control after after the the assignment token assignment token ➤ ➤ The right The right- -hand side is evaluated before the delay hand side is evaluated before the delay ➤ ➤ The left The left- -hand side is assigned after the delay hand side is assigned after the delay always @(A) always @(A) B B = = #5 #5 A; A; A A is evaluated at the time it changes, but is evaluated at the time it changes, but is not assigned to is not assigned to B B until after 5 time units until after 5 time units always @( always @(negedge clk negedge clk) ) Q Q <= <= @( @(posedge clk posedge clk) ) D; D; D D is evaluated at the negative edge of is evaluated at the negative edge of CLK CLK, , Q Q is changed on the positive edge of is changed on the positive edge of CLK CLK always @(instructor_input) if (morning) understand = instructor_input; else if (afternoon) understand = #5 instructor_input; else if (lunch_time) understand = wait (!lunch_time) instructor_input; always @(instructor_input) if (morning) understand = instructor_input; else if (afternoon) understand = #5 instructor_input; else if (lunch_time) understand = wait (!lunch_time) instructor_input;
  • 13.
    13 13 Sutherland Sutherland Sutherland H H H D D D L L L Intra-Assignment Delays WithRepeat Loops Intra Intra- -Assignment Delays Assignment Delays With Repeat Loops With Repeat Loops ➤ ➤ An edge An edge- -sensitive intra sensitive intra- -assignment timing control permits a assignment timing control permits a special use of the repeat loop special use of the repeat loop ➤ ➤ The edge sensitive time control may be repeated several The edge sensitive time control may be repeated several times before the delay is completed times before the delay is completed ➤ ➤ Either the blocking or the non Either the blocking or the non- -blocking assignment may be blocking assignment may be used used always @(IN) OUT <= repeat (8) @(posedge clk) IN; always @(IN) OUT <= repeat (8) @(posedge clk) IN; The value of IN is evaluated when it changes, but is not assigned to OUT until after 8 clock cycles
  • 14.
    14 14 Sutherland Sutherland Sutherland H H H D D D L L L Choosing the CorrectProcedural Assignment Choosing the Choosing the Correct Procedural Assignment Correct Procedural Assignment ➤ ➤ Which procedural assignment should be used to model a Which procedural assignment should be used to model a combinatorial logic buffer? combinatorial logic buffer? ➤ ➤ Which procedural assignment should be used to model a Which procedural assignment should be used to model a sequential logic flip sequential logic flip- -flop? flop? ➤ ➤ The following pages will answer these questions The following pages will answer these questions always @(in) #5 out = in; always @(in) #5 out <= in; always @(in) out = #5 in; always @(in) out <= #5 in; always @(posedge clk) #5 q = d; always @(posedge clk) #5 q <= d; always @(posedge clk) q = #5 d; always @(posedge clk) q <= #5 d;
  • 15.
    15 15 Sutherland Sutherland Sutherland H H H D D D L L L Transition Propagation Methods Transition Transition PropagationMethods Propagation Methods ➤ ➤ Hardware has two primary propagation delay methods: Hardware has two primary propagation delay methods: ➤ ➤ Inertial delay Inertial delay models devices with finite switching speeds; models devices with finite switching speeds; input glitches do not propagate to the output input glitches do not propagate to the output ➤ ➤ Transport delay Transport delay models devices with near infinite models devices with near infinite switching speeds; input glitches propagate to the output switching speeds; input glitches propagate to the output 20 60 50 40 30 10 20 60 50 40 30 10 Buffer with a 10 nanosecond propagation delay 20 60 50 40 30 10 20 60 50 40 30 10 Buffer with a 10 nanosecond propagation delay
  • 16.
    16 16 Sutherland Sutherland Sutherland H H H D D D L L L Combinational Logic ProceduralAssignments Combinational Logic Combinational Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? 20 60 50 40 30 10 in in 33 33 36 36 45 45 always @(in) always @(in) o1 o1 = = in; in; Blocking, Blocking, No delay No delay always @(in) always @(in) o2 o2 <= <= in; in; Non Non- -blocking, blocking, No delay No delay always @(in) always @(in) #5 #5 o3 o3 = = in; in; Blocking, Blocking, Delayed evaluation Delayed evaluation o1 o1 o2 o2 o3 o3 o4 o4 o5 o5 o6 o6 always @(in) always @(in) #5 #5 o4 o4 <= <= in; in; Non Non- -blocking, blocking, Delayed evaluation Delayed evaluation always @(in) always @(in) o5 o5 = #5 = #5 in; in; Blocking, Blocking, Delayed assignment Delayed assignment always @(in) always @(in) o6 o6 <= #5 <= #5 in; in; Non Non- -blocking, blocking, Delayed assignment Delayed assignment zero delay zero delay inertial inertial transport transport
  • 17.
    17 17 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic ProceduralAssignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Sequential assignments Sequential assignments ➤ ➤ No delays No delays 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) begin begin y1 y1 = = in; in; y2 y2 = = y1; y1; end end always @( always @(posedge clk posedge clk) ) begin begin y1 y1 <= <= in; in; y2 y2 <= <= y1; y1; end end in 35 53 y2 y1 y1 y2 y2 y1 parallel flip parallel flip- -flops flops y1 y2 shift shift- -register with zero delays register with zero delays
  • 18.
    18 18 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic ProceduralAssignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Sequential assignments Sequential assignments ➤ ➤ Delayed evaluation Delayed evaluation 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) begin begin #5 #5 y1 y1 = = in; in; #5 #5 y2 y2 = = y1; y1; end end always @( always @(posedge clk posedge clk) ) begin begin #5 #5 y1 y1 <= <= in; in; #5 #5 y2 y2 <= <= y1; y1; end end in 35 53 y2 y1 y1 y2 ? ? ? ? ? ? y1 y2 #5 #5 shift register with delayed clocks shift register with delayed clocks ? ? ? ? ? ? y1 y2 #5 #5 shift register with delayed clocks shift register with delayed clocks
  • 19.
    19 19 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic ProceduralAssignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Sequential assignments Sequential assignments ➤ ➤ Delayed assignment Delayed assignment 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) begin begin y1 y1 = #5 = #5 in; in; y2 y2 = #5 = #5 y1; y1; end end always @( always @(posedge clk posedge clk) ) begin begin y1 y1 <= #5 <= #5 in; in; y2 y2 <= #5 <= #5 y1; y1; end end y1 y2 y1 y2 in 35 53 shift register delayed clock on second stage shift register delayed clock on second stage y1 y2 #5 #5 #5 y1 y2 #5 #5 shift register with delays shift register with delays
  • 20.
    20 20 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic ProceduralAssignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Concurrent assignments Concurrent assignments ➤ ➤ No delays No delays y1 y2 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) y1 y1 = = in; in; always @( always @(posedge clk posedge clk) ) y2 y2 = = y1; y1; y1 y2 always @( always @(posedge clk posedge clk) ) y1 y1 <= <= in; in; always @( always @(posedge clk posedge clk) ) y2 y2 <= <= y1; y1; in 35 53 ? ? ? ? ? ? ? ? y1 y2 ? shift register with race condition shift register with race condition y1 y2 shift shift- -register with zero delays register with zero delays
  • 21.
    21 21 Sutherland Sutherland Sutherland H H H D D D L L L y2 y1 Sequential Logic ProceduralAssignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Concurrent assignments Concurrent assignments ➤ ➤ Delayed evaluation Delayed evaluation 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) #5 #5 y1 y1 = = in; in; always @( always @(posedge clk posedge clk) ) #5 #5 y2 y2 = = y1; y1; always @( always @(posedge clk posedge clk) ) #5 #5 y1 y1 <= <= in; in; always @( always @(posedge clk posedge clk) ) #5 #5 y2 y2 <= <= y1; y1; in 35 53 y1 y2 ? ? ? ? ? ? ? ? ? ? shift register with race condition shift register with race condition y1 y2 ? #5 #5 ? ? ? ? y1 y2 #5 shift register with race condition shift register with race condition
  • 22.
    22 22 Sutherland Sutherland Sutherland H H H D D D L L L Sequential Logic ProceduralAssignments Sequential Logic Sequential Logic Procedural Assignments Procedural Assignments ➤ ➤ How will these procedural assignments behave? How will these procedural assignments behave? ➤ ➤ Concurrent assignments Concurrent assignments ➤ ➤ Delayed assignment Delayed assignment 20 60 50 40 30 10 clk always @( always @(posedge clk posedge clk) ) y1 y1 = #5 = #5 in; in; always @( always @(posedge clk posedge clk) ) y2 y2 = #5 = #5 y1; y1; always @( always @(posedge clk posedge clk) ) y1 y1 <= #5 <= #5 in; in; always @( always @(posedge clk posedge clk) ) y2 y2 <= #5 <= #5 y1; y1; in 35 53 y1 y2 y1 y2 y1 y2 #5 #5 shift register, delay must be < clock period shift register, delay must be < clock period y1 y2 #5 #5 shift register with delays shift register with delays
  • 23.
    23 23 Sutherland Sutherland Sutherland H H H D D D L L L Rules ofThumb for Procedural Assignments Rules of Thumb for Rules of Thumb for Procedural Assignments Procedural Assignments ➤ ➤ Combinational Logic: Combinational Logic: ➤ ➤ No delays: No delays: Use blocking assignments ( Use blocking assignments ( a = b; a = b; ) ) ➤ ➤ Inertial delays: Inertial delays: Use delayed evaluation blocking Use delayed evaluation blocking assignments ( assignments ( #5 a = b; #5 a = b; ) ) ➤ ➤ Transport delays: Transport delays: Use delayed assignment non Use delayed assignment non- -blocking blocking assignments ( assignments ( a <= #5 b; a <= #5 b; ) ) ➤ ➤ Sequential Logic: Sequential Logic: ➤ ➤ No delays: No delays: Use non Use non- -blocking assignments ( blocking assignments ( q <= d; q <= d; ) ) ➤ ➤ With delays: With delays: Use delayed assignment non Use delayed assignment non- -blocking blocking assignments ( assignments ( q <= #5 d; q <= #5 d; ) )
  • 24.
    24 24 Sutherland Sutherland Sutherland H H H D D D L L L An Exceptionto Non-blocking Assignments in Sequential Logic An Exception to Non An Exception to Non- -blocking blocking Assignments in Sequential Logic Assignments in Sequential Logic ➤ ➤ Do Do not not use a non use a non- -blocking assignment if another statement in blocking assignment if another statement in the procedure requires the new value in the same time step the procedure requires the new value in the same time step begin #5 A <= 1; #5 A <= A + 1; B <= A + 1; end What values do A and B contain after 10 time units? What values do A and B contain after 10 time units? always @(posedge clk) begin case (state) `STOP: next_state <= `GO; `GO: next_state <= `STOP; endcase state <= next_state; end Assume state and next_state are `STOP at the first clock, what is state: - At the 2nd clock? - At the 3rd clock? - At the 4th clock? - At the 5th clock? Assume state and next_state are `STOP at the first clock, what is state: - At the 2nd clock? - At the 3rd clock? - At the 4th clock? - At the 5th clock? A is 2 A is 2 B is 2 B is 2 `STOP `STOP `GO `GO `GO `GO `STOP `STOP
  • 25.
    25 25 Sutherland Sutherland Sutherland H H H D D D L L L Exercise 3: ProceduralAssignments Exercise 3: Exercise 3: Procedural Assignments Procedural Assignments ➤ ➤ Write a procedure for an adder (combinational logic) that Write a procedure for an adder (combinational logic) that assigns C the sum of A plus B with a 7ns propagation delay. assigns C the sum of A plus B with a 7ns propagation delay. ➤ ➤ Write the procedure(s) for a 4 Write the procedure(s) for a 4- -bit wide shift register (positive bit wide shift register (positive edge triggered) of clock and has a 4ns propagation delay. edge triggered) of clock and has a 4ns propagation delay. always @(A or B) #7 C = A + B; always @(A or B) #7 C = A + B; always @(posedge clk) begin y1 <= #4 in; y2 <= #4 y1; y3 <= #4 y2; out <= #4 y3; end always @(posedge clk) begin y1 <= #4 in; y2 <= #4 y1; y3 <= #4 y2; out <= #4 y3; end always @(posedge clk) y1 <= #4 in; always @(posedge clk) y2 <= #4 y1; always @(posedge clk) y3 <= #4 y2; always @(posedge clk) out <= #4 y3; always @(posedge clk) y1 <= #4 in; always @(posedge clk) y2 <= #4 y1; always @(posedge clk) y3 <= #4 y2; always @(posedge clk) out <= #4 y3;
  • 26.
    26 26 Sutherland Sutherland Sutherland H H H D D D L L L Exercise 3(continued): Procedural Assignments Exercise 3 (continued): Exercise 3 (continued): Procedural Assignments Procedural Assignments ➤ ➤ Write a Verilog procedure for a “black box” ALU pipeline that Write a Verilog procedure for a “black box” ALU pipeline that takes 8 clock cycles to execute an instruction. The pipeline takes 8 clock cycles to execute an instruction. The pipeline triggers on the positive edge of clock. The “black box” is triggers on the positive edge of clock. The “black box” is represented as call to a function named ALU with inputs A, B represented as call to a function named ALU with inputs A, B and OPCODE. and OPCODE. always @(posedge clk) alu_out <= repeat(7) @(posedge clk) ALU(A,B,OPCODE); always @(posedge clk) alu_out <= repeat(7) @(posedge clk) ALU(A,B,OPCODE); How many Verilog statements does it take to model an eight stage pipeline?