Virtual memory allows a program to access more memory than is physically installed on the system by storing seldom-used data on disk. The CPU uses virtual addresses while physical addresses identify the actual memory location. The memory management unit (MMU) translates virtual to physical addresses using page tables stored in memory. If a page is not in memory, a page fault occurs and the OS loads the required page from disk before resuming execution. Virtual memory provides the illusion of a larger memory to programs through demand paged paging and address translation mechanisms.

1. VIRTUAL MEMORY
BY
TAMIZHARASI A
ASST PROFESSOR – CSE
RMD ENGINEERING COLLEGE

2. Virtual and Physical Memory
�Physical Memory: memory actually
available in the computer
�Virtual Memory: memory that the OS
allows a program to believe it has
�Physical Address: real location in
physical memory; identifies actual storage
�Virtual Address: conventional
addressing used by a program which the
OS must translate into a physical address

3. CPUCPU
regsregs
C
a
c
h
e
MemoryMemory diskdisk
size:
speed:
$/Mbyte:
line size:
32 B
1 ns
8 B
Register Cache Memory Disk Memory
32 KB-4MB
2 ns
$125/MB
32 B
1024 MB
30 ns
$0.20/MB
4 KB
100 GB
8 ms
$0.001/MB
larger, slower, cheaper
8 B 32 B 4 KB
cache virtual memory

4. if no enough space in main memory then secondary
storage devices is used.
the program is brought into the main memory while
needed.
the OS moves programs and data automatically
between the main memory and secondary storage referred
as virtual-memory techniques.
the addresses that the processor issues for either
instructions or data are called virtual or logical
addresses.

6. Memory management unit (MMU), translates virtual
addresses into physical addresses.
when the desired data (or instructions) are in the main
memory, these data are fetched.
if the data are not in the main memory, the MMU
causes the operating system to bring the data into the
memory from the disk.
transfer of data between the disk and the main memory
is performed using the DMA scheme.

7. Processor
Hardware
Addr Trans
Mechanism
Main
Memorya
a'
physical addressvirtual address part of the
on-chip
memory mgmt unit (MMU)

8. ADDRESS TRANSLATION
Pages:(basic unit of information)
Virtual and physical address spaces divided into equal-
sized blocks are called “pages” (both virtual and physical)
occupies contiguous main memory locations
ranges from 2K to 16K bytes in length.
should not be too small, bcoz the access time of a
magnetic disk is much longer than main memory.
if too large it is possible that a substantial portion of a
page may not be used.

9. Cache techniques and virtual -memory techniques are
very similar.
Each virtual address has
- virtual page number (high-order bits)
- offset (low-order bits) specifies the location of a
particular byte within a page.
Page table:
 has Information about the main memory location of
each page
like address where the page is stored and the current
status of the page.

10. An area in the main memory that can hold one page is
called a page frame.
 The starting address of the page table is kept in a
page table base register.
 By adding the virtual page number to the contents of
this register, the address of the corresponding entry in
the page table is obtained.

11. Computing Physical Address
Page Table Entry (PTE) provides information about page
if (valid bit = 1) then the page is in memory.
Use physical page number (PPN) to construct address
if (valid bit = 0) then the page is on disk
Page fault

12. control bits that describe the status of the page
one bit indicates the validity of the page, that is, whether
the page is actually loaded in the main memory.
Another bit indicates whether the page has been modified
during its residency in the memory.
Other control bits indicate various restrictions that may be
imposed on accessing the page.

13. Translation Lookaside Buffer (TLB):
 due large size of page table it is impossible to include in
MMU of processor. Hence, page table is kept in main
memory.
a copy of small portion of page can be a accommodated
within MMU using TLB
 A small cache consists of most recently accessed page
entries
 TLB must also include the virtual address of the entry.

15. Address translation of TLB:
If the page table entry is found in the TLB, the
physical address is obtained immediately.
else the required entry is obtained from the page table
in the main memory and the TLB is updated.
Page Fault:
if the requested page is not in the main memory, a
page fault is said to have occurred.
The whole page must be brought from the disk into
the memory before access can proceed.
MMU asks the OS to intervene by raising an
exception (interrupt).

16. active task is interrupted, and OS then copies the
requested page from the disk into the main memory and
returns control to the interrupted task, a long delay may
occur.
when the task resumes, either the execution of the
interrupted instruction must continue from the point of
interruption or the instruction must be restarted.
If a new page is brought from the disk when the main
memory is full, it must replace one of the resident pages.
 Least Recently Used is removed normally.
 A control bit that is set to 1 whenever the corresponding
page is referenced (accessed).

17. The average translation time can be reduced by including
one or more special registers that retain the virtual page
number and the physical page frame of the most recently
performed translations.
MEMORY MANAGEMENT REQUIREMENTS
 system space - OS routines
 user space -user application programs reside.

18. MMU uses a page table base register to determine the
address of the table to be used in the translation process.
by changing the contents of this regis-ter, OS can switch
from one space to another.
The physical main mem-ory is thus shared by the active
pages of the system space and several user spaces.
 can access only the pages that belong to one of these
spaces at any given time.

19. No program should be allowed to destroy either the
data or instructions of other programs in the memory.
The processor has two states:
Supervisor state
The processor is usually placed in the supervisor state
when OS routines are being executed and in the user
state to execute user programs.
User State
In the user state, some machine instructions cannot be
executed.

20. These privileged instructions, which include such
operations as modifying the page table base register, can
only be executed while the processor is in the supervisor
state.
Hence, a user program is prevented from accessing the
page tables of other user spaces or of the system space.
some application program have access to certain pages
belonging to another program.

21. OS can arrange this by causing these pages to appear
in both spaces.
The shared pages will therefore have entries in two
different page tables.
The control bits in each table entry can be sent to
control the access privileges granted to each program.

22. THANK YOU