This paper presents an area, delay and power efficient design of SR flip flop. As the chip manufacturing technology is on the threshold of evaluation, which shrinks a chip in size and enhances its performance, here the flip flop is implemented in a layout level which develops an optimized design using recent CMOS layout tools. The proposed SR flip flop has been designed and simulated using 45nm technology. After that, parametric analysis has been done. In this paper, flip flop has been developed using full automatic design flow and semi-custom design flow. The performance of SR flip flop layouts using different design flows has been analyzed and compared in terms of area, delay and power consumption. The simulation results show that the design of SR flip flop using semi-custom design flow improved the area occupied by 46.9% and power consumption is reduced by 38.4%.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 52
Layout Design Analysis of SR Flip Flop using
CMOS Technology
Avneet Kaur
Department of ECE, National Institute of Technical Teachers’ Training & Research, Chandigarh, India
avneetkaur.ak92@gmail.com
Abstract:- This paper presents an area, delay and power
efficient design of SR flip flop. As the chip manufacturing
technology is on the threshold of evaluation, which shrinks a
chip in size and enhances its performance, here the flip flop is
implemented in a layout level which develops an optimized
design using recent CMOS layout tools. The proposed SR flip
flop has been designed and simulated using 45nm technology.
After that, parametric analysis has been done. In this paper,
flip flop has been developed using full automatic design flow
and semi-custom design flow. The performance of SR flip flop
layouts using different design flows has been analyzed and
compared in terms of area, delay and power consumption.
The simulation results show that the design of SR flip flop
using semi-custom design flow improved the area occupied by
46.9% and power consumption is reduced by 38.4%.
Keywords: Bistable circuits, Latches, Flip flops, CMOS
integrated circuits, Design methodology
1. INTRODUCTION
A flip flop is an electronic circuit that has two stable states
and can be used to store information. The circuit can be
made to change its state by applying signals to one or more
control inputs and will have one or two outputs. Flip flops
are often used in computational circuits to operate in
selected sequences during recurring clock intervals to
receive and maintain data for a limited period of time
sufficient for other circuits within a system to further
process data [1]. Thus, flip flops are the basic storage
elements in a sequential logic circuit. Memory elements
play a vital role in digital world and the basic memory
elements are latches and flip flops. These bistable circuits
are the basic building blocks of a data path structure. They
allow for the storage of data processed by combinational
circuits and synchronization of operation at a given clock
frequency [2]. For high performance chip design in VLSI,
the choice of the back-end methodology has a significant
impact on the design time and the design cost. Latches and
flip flops directly impact the power consumption and speed
of VLSI systems [3]. The main improvement in terms of
feature size reduction for CMOS integrated circuits is
increased number of metal interconnects to link MOS
devices together within the chip [4]. Also, in synchronous
systems, any violation of the timing constraints of the flip
flops can cause the overall system to malfunction.
Moreover, the process variations can create a large
variability in flip flop delays impacting the timing yield
[5]. Flip flops have a wide area of applications such as
counters, shift registers and level shifters. A binary
synchronous counter is one of the essential building blocks
in very large scale integration design. Its operation is
usually based on a synchronous timing principle in which
the data signal is evaluated at each clock cycle and
assigned to its associated flip flop [6]. A counter is
designed by using a number of D registers. The D latch is a
simple gated SR latch with an inverter connected between
its S and R inputs [7]. Steady miniaturization of transistors
with each new generation of bulk CMOS technology has
yielded continual improvement in the performance of
digital circuits. Thus, power efficiency if of increased
importance, to meet the performance requirements of VLSI
design [8]. Also, the leakage power increases as
technology is scaled down [9]. A tradeoff between speed
and power is always possible. In high-performance and
low-power applications, both features are equally
important. The point of minimum power-delay product is
the point of optimal energy utilization at a given clock
frequency [10]. In this paper, area, delay and power
consumption for an SR flip flop have been compared using
DSCH and Microwind tools. Basically, two types of design
methodologies have been compared, full automatic and
semi-custom. Both the designs are created using 45nm
CMOS technology. The SR flip flop or the gated SR latch
having a second level of AND gates along with a level of
direct SR latch using NOR gates has been discussed in the
paper.
2. SR LATCH
A latch is a circuit that has two stable states. Thus, it is a
bistable multivibrator. It can be used to store state
information. It is made up of several transistors and is used
in the design of static memories and hardware registers.
When using static gates as building blocks, the most
commonly used fundamental latch is the SR latch, where S
stands for set and R stands for reset. It can be constructed
from a pair of cross-coupled NOR logic gates. The stored
bit is represented on the output marked Q.
Figure 1. SR Latch
The truth table for a simple SR latch is shown in Table 1.
Table 1. SR latch operation
R S Q Comment
0 0 NC No change. Latch remains in
present state.
0 1 1 Set
1 0 0 Reset
1 1 0 Invalid condition

2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
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3. GATED SR LATCH
A gated SR latch (clocked SR flip-flop) can be made by
adding a level of AND gates to the SR latch.
Figure 2. Gated SR Latch
With E high (enable true), the signals can pass through the
input gates to the encapsulated latch, i.e. the latch
is transparent. With E low (enable false) the latch is closed
(opaque) and remains in the state it was left in when the
last time E was high. The enable input may be a clock
signal, but more often it is a read or write strobe.
Table 2. Gated SR latch operation
E/C Action
0 No action (keep state)
1 The same as non-clocked SR latch
The circuit shown in Figure 2 is now implemented using
DSCH. Figure 3 shows the schematic of SR flip flop at
transistor level.
Figure 3. CMOS SR flip flop
4. LAYOUT DESIGN SIMULATIONS
In complex VLSI design, manual layout designing for a
very complex circuit becomes very difficult. So, as
compared to the manual layout design, an automatic layout
generation approach is preferred. According to the full
automatic design flow, the schematic implemented using
DSCH shown in Figure 3 is now compiled using
Microwind. Compilation is done in 45nm technology.
Figure 4 shows the automatically generated layout.
Figure 4. Full Automatic SR Flip Flop Layout
Figure 5 depicts the simulation result of the automatically
generated CMOS layout of SR flip flop.
Figure 5. Full Automatic Design Simulation
Here, the first type of design flow i.e. full automatic has
been completed. Now proceeding to the second type of
design flow i.e. semi-custom in which NMOS and PMOS
devices are generated using MOS generator option from
the palette. In this, the layout is directly created using
Microwind. The advantage of this approach is that design
rule errors can be avoided. Figure 6 shows the semi-custom
design layout of SR flip flop. The proposed semi-custom
layout of SR flip flop is also designed in 45nm technology
in Microwind. In the following layout, the design is
optimized by bringing the inverters and gates closer, in
order to minimize the length of the polysilicon gates.
Figure 6. Semi-Custom SR Flip Flop Layout
Now, Figure 7 shows that the simulation result of semi-
custom generated layout design is similar to that of
automatically generated design.
Figure 7. Semi-Custom Design Simulation
5. RESULT ANALYSIS
In this paper, the SR flip flop has been implemented using
two different design methodologies. So, performance
comparison is as depicted by Table 3. The aspects on
which the comparison is done are area, delay and power
consumption.

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Table 3. Performance Comparison for SR Flip Flop
Aspect Full
Automatic
Design
Semi-
Custom
Design
Area (µm2
) 82.2 43.6
Delay (ps) 540 527
Power (µW) 2.440 1.501
The analysis of above comparison shows that the SR flip
flop designed using semi-custom design flow has better
performance. Area reduces by 46.9% and power
consumption gets reduced to 38.4%. The same results can
be observed graphically from Figure 8.
Figure 8. Comparison Analysis
6. CONCLUSION
In this paper, an exhaustive analysis of two design
methodologies for SR flip flop in 45nm CMOS technology
has been carried out. The comparison has been performed
for area, delay and power consumption. According to the
presented results, the SR flip flop in semi-custom design is
compact with less delay and low power consumption.
Thus, it has better performance when used in memories.
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