Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 88
Layout Design Analysis of CMOS Comparator
using 180nm Technology
1
Jyoti , 2
Rajesh Mehra
1
ME Scholar , 2
Associate Professor,
1, 2
Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training and
Research, Chandigarh, India
Jyoti13july@gmail.com
ABSTRACT- Comparator is a very useful and basic arithmetic
component of digital system. In the world of technology the
demand of portable devices are increasing day by day. This
paper presents CMOS design of 1-bit comparator on 180nm
technology. The layout of 1-bit comparator has been developed
using Automatic and semi-custom techniques. Both the layouts
are compared and analyzed in terms of their Power and Area
consumption. Automatic layout is generated from its equivalent
schematic whereas semi-custom layout is developed manually.
The result shows that semi-custom consumes less power as
compared to Automatic.
Key Words: CMOS technology, Power dissipation, Layout, Performance
analysis, combinational circuit
INTRODUCTION
Comparator is one of the fundamental building blocks in
most analog-to-digital converters (ADCs) [1]. Comparator
are the most important design element for various application
such as in embedded processor, general purpose processor,
DSP core, image/signal processing and built in self test
circuits [2]. Minimizing the power dissipation for the digital
circuits requires optimization at all level of the design. So,
this optimization depends on circuit style, topologies and in
fact includes the technology which is used to implement the
digital circuits [3]. In VLSI design Comparator is a basic
component which compares two binary number and then
determine whether the number is greater than, less than or
equal to the other input. The n-bit Comparator is shown in
figure 1
A A > B
A=B
B
A > B
Fig.1 Block diagram of n-bit Comparator
The outcome of comparison is specified by three binary
variables that show whether A>B, A=B, or A<B. In the truth
table, the circuit for comparing two n-bit numbers, has 2n
inputs & 22n
entries. So, 4 inputs & 16-rows in the truth table
for 2-bit numbers and similarly, for 3-bit numbers 6-inputs &
64-rows in the truth table [4]. The logic style used in logic
gates basically influences the size, speed, power dissipation
and the wiring complexity of a circuit [5]. Circuit size
depends on the number of transistors and their sizes and on
the wiring complexity [6]. The wiring complexity is determined
by the number of connections and their lengths. All mentioned
characteristics may vary considerably from one logic style to
another and thus proper choice of logic style is very important for
circuit performance [7, 8]. The speed, power consumption and
chip area are the important factors while designing comparators.
The continually-growing application of portable devices makes
the power consumption a very critical constraint for circuit
designers [9].The CMOS technology produce degraded output in
the circuit. As NMOS transistor pass strong logic 0 and weak 1
pass but PMOS transistor is strong 1 pass and weak 1 pass. It is
possible to combine NMOS and PMOS transistor into a single
switch that is capable of driving its output terminal either to a low
or high voltage equally well [10].
Here we use Microwind3.1 to draw the layout of the CMOS
circuit. In order to differentiate designs, simulations are carried
out for Power and Area. Simulations are performed at 180nm
technology. CMOS can be designed by using PMOS and NMOS
transistor and CMOS consumes no steady state power.
1-BIT MAGNITUDE COMPARATOR
Digital Comparator also called “Magnitude Comparator” is a
combinational circuit that compares two numbers in which A and
B are two inputs and three outputs A> , = , < and only
one of the three outputs would be high accordingly if A is greater
than or equal to or less than B. The truth table of 1-bit comparator
is shown in Table 1
Table 1. Truth table of 1-bit comparator
Input Output
A B A> A=B A<
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Karnaugh -Map is used to minimize Boolean function obtained
from truth table and shown in figure 2
Equation for (A > B) = ′
n- Bit Magnitude
Comparator

2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
89 NITTTR, Chandigarh EDIT-2015
Equation for (A < B)= ′
Equation for ( A = B) = ′ ′
+
= A ʘ B
Fig.2 Equations from Karnaugh -Map
SCHEMATIC DESIGN SIMULATIONS
A Comparator has two inputs and three outputs which are
A > B , A< B and A=B. The logic circuit of this comparator
can be implemented with the help of XNOR gate, AND gates
and NOT gates. The logic for A=B requires XNOR gate
while the logic for A >B and A< B requires AND and NOT
gates. The basic logic diagram for Comparator with basic
gates can be represented as shown below figure 3
Fig.3 Logic Level comparator
The Switch level Comparator consist of NMOS and PMOS
transistors as shown in figure 4 and showing 1-bit
Comparator. Also the timing diagram is shown in fig. 5
Fig.4 Switch Level Comparator
Fig.5 Timing diagram of Switch Level Comparator
LAYOUT DISCUSSIONS
The schematic of 1-bit Comparator is designed. Using Microwind
software, the auto generated layout of 1-bit Comparator is created
with 180nm foundary. The figure 6 represents the autogenerated
layout. Layout is the general concept that describes the
geometrical representation of the circuits by the means of layers.
Different logical layers is used by designers to generate the
layout.
Fig.6 Auto generated layout of the comparator
The Output waveform for Automatic generated layout is shown in
figure 7
Fig.7 Output waveform for automatic generated layout

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The representation of Semi-Custom Layout of the 1-bit
Comparator using nMOS, pMOS and its output waveform is
shown in figure 8 and figure 9 respectively.
Fig.8 Semi-custom layout of the comparator
Fig.9 Output waveform for semi-custom layout
The performance of proposed 1-bit Comparator layout is
compared with semicustom approach. The performance in
terms of Area and Power is compared. Comparative analysis
is shown in Table 2
Table 2: Comparative Analysis For Area And Power
Approach Area
(μm2)
Power
(mWatt)
Width(μm) Height(μm)
Automatic
Generated
1446.5 0.176 73.8 19.6
Semi-
Custom
855.4 0.163 31.8 26.9
In terms of area and power the Semi-Custom layout has
better performance among two design approaches. Area and
Power graph representation of these design approach is
shown below in figure 10 and Figure 11 respectively
Fig.10 Area shown between Automatic Generated and Semi-Custom layout
Fig11 Power shown between Automatic Generated and Semi-Custom layout
From the above graph we observed that there is a reduction in
power and Area for semi custom approach as compared to
Automatic generated layout.
CONCLUSION
Above analysis conclude that this technique is very useful to
reduce the effective area on a chip and power dissipation. In this
paper, we presented the analysis for layout of 1-bit comparator
using auto generated and semi-custom technique and also
expressions were derived using karnaugh -map. Finally from the
comparative analysis it is clear that the Semi-Custom layout is
more efficient than auto generated in terms of power and area. So
this design approach can be implemented where area and power
reduction is the main consideration.
REFERENCES
[1] Samaneh Babayan-Mashhadi and Reza Lotfi, “ Analysis & Design of a Low
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[2] Saleh Abdel- Hafeez, “Scalable digital CMOS comparator using a parallel
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[3] Geetanjali Sharma, Uma Nirmal, Yogesh Misra, “ A low power8- bit
magnitude comparator with small transistor count hybrid PTL/CMOS logic,”
International Journal of Computational Engineering & Management, Vol. 12,pp.
110-115, April 2011.
0
200
400
600
800
1000
1200
1400
1600
Area
Automatic
Generated
Semi-Custom
Automatic
Generated
52%
Semi-
Custom
48%
Power(mw)

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91 NITTTR, Chandigarh EDIT-2015
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