1. COMPUTER SCIENCE
UNIT I, MODULE 1
THE FETCH EXECUTE CYCLE II
FETCH
This is the "Fetch" part of the cycle.
1. The CPU examines the program counter (PC) register. This gives the address of the
instruction to be brought in from memory. This address is copied to the memory address
register (MAR) as the MAR is the register which holds the addresses to be placed on the
address bus.
2. The processor then sets 2 signals on the address bus: the Read/Write line to 1 to indicate that
the memory value is to be read into the CPU; then it sets the Address Bus Enable line to
indicate that the address bus holds a valid address.
3. The memory fetches the byte from the specified address and places it on the data bus.
4. The memory then sets the Data Bus Enable line to indicate to the processor that the data bus
contains a valid byte.
5. The CPU reads the word in from the data bus to the instruction register (IR).
6. The CPU increments the value in the PC so that it will proceed to the following instruction
on the next machine code fetch.
EXECUTE
The processor then executes the instruction, which, in this case, means two more steps:
Decode
7. The instruction is next decoded by the decoder (in the control unit)
Execute
8. The processor performs the required action. This may vary from a data manipulation
operation, to a control operation, to an input/output operation.
1. This usually involves the use of other registers such as the accumulator
E.g. if the operand in the machine instruction is the data to be operated on it is moved to
the memory data register (MDR).
E.g. if the data is in memory, another fetch operation is required and the data is stored in
the MDR.
An ADD operation would then see the ALU adding the contents of the MDR to the
accumulator and storing the result back into the accumulator
