chapter-12memory.pptx

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Semiconductor
Memories
December 20, 2002
© Digital Integrated Circuits2nd Memories

Chapter Overview
 Memory Classification
 Memory Architectures
 The Memory Core
 Periphery
 Reliability
 Case Studies

Semiconductor Memory Classification
Read-Write Memory
Non-Volatile
Read-Write
Memory
Read-Only Memory
Random
Access
Non-Random
Access
EPROM
E2
PROM
Mask-Programmed
Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CAM

Memory Timing: Definitions

Memory Architecture: Decoders
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
Decoder reduces the number of select signals
K = log2N
Word 0
Word 1
Word 2
Word N2 2
Word N2 1
Storage
cell
M bits M bits
words
S0
S1
S2
S
N N2 2
SN2 1
Input-Output
(M bits)
A
A
0
1
AK2 1
K 5 log2N
Storage
cell
S0
Input-Output
(M bits)
Deco
Word 0
Word 1
Word 2
dW
er
ord N2 2
Word N2 1

Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word

Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings

Block Diagram of 4 Mbit SRAM
ubglobalGro
l
o
w
b
a
d
l
e
r
c
o
o
w
d
S
e
d
u
r
e
bc
go
lo
db
ea
rl row decoder
BBlolockck33
S
10
128 K Array Block
Block 1
Clock
generator
CS, WE
buffer
I/O
buffer
Y-address
buffer
X-address
buffer
x1/x4
controller
Z-address
buffer
X-address
buffer
Predecoder and block selector
Bit line load
Transfer gate
Column decoder
Sense amplifier and write driver
Local row dec
[Hirose90]

Contents-Addressable Memory
I/O B
Iu
/O
ffe
B
ru
sffers
ComCmoamnmdsands
Address Deco9der
Address Decoder
Validity
Bits
Address
Decoder
Data (64 bits)
I/O
Buffers
Comparand
CAM Array
9
2 words 3 64 bits
Mask
Control Logic R/W Address (9 bits)
Commands
2
9
Validity
Bits
Priority
Encoder

Memory Timing: Approaches
DRAM Timing
Multiplexed Adressing
SRAM Timing
Self-timed

Read-Only Memory Cells
WL
BL
WL
BL
1
WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM
MOS ROM 1 MOS ROM 2

MOS OR ROM
WL[0]
VDD
BL[0]
WL[1]
WL[2]
WL[3]
Vbias
BL[1]
Pull-down loads
BL[2] BL[3]
VDD

MOS NOR ROM
WL[0]
GND
BL[0]
WL[1]
WL[2]
WL[3]
VDD
Pull-up devices
BL[1] BL[2]
BL[3]
GND

MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5 x 7)
Programmming using the
Active Layer Only

MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11 x 7)
Programmming using
the Contact Layer Only

MOS NAND ROM
All word lines high by default with exception of selected row
WL[0]
WL[1]
WL[2]
WL[3]
VDD
Pull-up devices
BL[3]
BL[2]
BL[1]
BL[0]

MOS NAND ROM Layout
No contact to VDD or GND necessary;
drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8 x 7)
Programmming using
the Metal-1 Layer Only

NAND ROM Layout
Cell (5 x 6)
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
Programmming using
Implants Only

Equivalent Transient Model for MOS NOR ROM
 Word line parasitics
 Wire capacitance and gate capacitance
 Wire resistance (polysilicon)
 Bit line parasitics
 Resistance not dominant (metal)
 Drain and Gate-Drain capacitance
Model for NOR ROM VDD
Cbit
rword
cword
WL
BL

Equivalent Transient Model for MOS NAND ROM
 Word line parasitics
 Similar to NOR ROM
 Bit line parasitics
 Resistance of cascaded transistors dominates
 Drain/Source and complete gate capacitance
Model for NAND ROM
VDD
CL
rword
cword
cbit
rbit
WL
BL

Decreasing Word Line Delay
Polysilicon word line
WL K cells
Driver
WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides
Metal bypass
(b) Using a metal bypass
(c) Use silicides

Precharged MOS NOR ROM
BL[0] BL[1] BL[2] BL[3]
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
WL[0]
GND
WL[1]
WL[2]
WL[3]
VDD
Precharge devices
GND
f pre

Non-Volatile Memories
The Floating-gate transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n+ n+_
p
tox
tox
Device cross-section
Schematic symbol
D
G
S

Floating-Gate Transistor Programming
0 V
2 5 V 0 V
D
S
Removing programming
voltage leaves charge trapped
5 V
2 2.5 V 5 V
D
S
Programming results in
higher VT.
20 V
10 V 5 V 20 V
D
S
Avalanche injection

A “Programmable-Threshold” Transistor

FLOTOX EEPROM
Floating gate
Source
Substrate
p
Gate
Drain
n1 n1
FLOTOX transistor
Fowler-Nordheim
I-V characteristic
20–30 nm
10 nm
-10 V
10 V
I
VGD

EEPROM Cell
BL
WL
VDD
Absolute threshold control
is hard
Unprogrammed transistor
might be depletion
 2 transistor cell

Flash EEPROM
erasure
Control gate
Floating gate
Thin tunneling oxide
n1 source n1 drain
programming
p-substrate
Many other options …

Cross-sections of NVM cells
EPROM
Memories
Flash
© Digital Integrated Circuits2nd Courtesy Intel

Basic Operations in a NOR Flash Memory―
Erase

Write

Read

NAND Flash Memory
Unit Cell
Word line(poly)
Source line
(Diff. Layer)
Gate
ONO
FG
Gate
Oxide
Courtesy Toshiba

NAND Flash Memory
Word lines
Select transistor
Bit line contact Source line contact
Active area
STI
Courtesy Toshiba

Characteristics of State-of-the-art NVM

Read-Write Memories (RAM)
 STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
 DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

6-transistor CMOS SRAM Cell
BL
WL
VDD
M5
M6
M4
M1
M2
M3
BL
Q
Q

CMOS SRAM Analysis (Read)
WL
BL
VDD
M5
M6
M4
M1
VDD
VDD VDD
BL
Q = 1
Q = 0
Cbit
Cbit

CMOS SRAM Analysis (Read)
ge rise [V]
1.2
1
0.8
0.6
0.4
V
o0l.
2ta
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)
Voltage
Rise
(V)

CMOS SRAM Analysis (Write)
BL = 1 BL = 0
Q = 0
Q = 1
M5
M6
M1
VDD
WL
VDD
M4

CMOS SRAM Analysis (Write)

6T-SRAM — Layout
VDD
Q
Q
GND
WL
BL
BL
M1
M3
M4
M2
M5 M6

Resistance-load SRAM Cell
Static power dissipation -- Want R L large
Bit lines precharged to VDD to address tp problem
M3
RL RL
WL
VDD
Q Q
M1 M2
M4
BL BL

SRAM Characteristics

3-Transistor DRAM Cell
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTn
WWL
BL1
M1 X
M3
M2
CS
BL2
RWL
VDD
VDD 2 VT
DV
VDD 2 VT
BL 2
BL 1
X
RWL
WWL

3T-DRAM — Layout
BL2
BL1 GND
RWL
M3
M2
WWL
M1

1-Transistor DRAM Cell
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
CS
------------
CS + CBL
=
V = VBL – VPRE VBIT – VPRE

DRAM Cell Observations
 1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.
 DRAM memory cells are single ended in contrast to
SRAM cells.
The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
 Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage
is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD

Sense Amp Operation
DV(1)
V(1)
V(0)
t
VPRE
VBL
Sense amp activated
Word line activated

1-T DRAM Cell
Uses Polysilicon-Diffusion Capacitance
Expensive in Area
M1 word
line
Diffused
bit line
Polysilicon
gate
Polysilicon
plate
Capacitor
Cross-section Layout
Metal word line
Poly
SiO2
Field Oxide
n+ n+
Inversion layer
induced by
plate bias
Poly

SEM of poly-diffusion capacitor 1T-DRAM

Advanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell Stacked-capacitor Cell
Capacitor dielectric layer
Cell plate
Word line
Insulating Layer
Transfer gate Isolation
Storage electrode

Static CAM Memory Cell
••• •••
CAM
Word
••• CAM
Bit Bit Bit Bit
CAM
Word
Wired-NOR Match Line
Match
M1
M2
M7
M6
M4 M5
M8 M9
M3
int
S
Word
••• CAM
Bit Bit
S

CAM in Cache Memory
A
d
Hit Logic
dress Decoder
CAM
ARRA
Y
Input Drivers
Tag Hit R/W
Address
SRAM
ARRA
Y
Sense Amps / Input Drivers
Data

Periphery
 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry

Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

Hierarchical Decoders
• • •
• • •
WL0
A2A3 A2A3 A2A3
A2A3
A3 A2 A2 A3
A0A1 A0A1 A0A1 A0A1
A1 A0 A0 A1
WL1
Multi-stage implementation improves performance
NAND decoder using
2-input pre-decoders

Dynamic Decoders
Precharge devices
VDD 
GND
WL3
WL2
WL1
WL0
A0
A0
GND
A1
A1

WL3
A0
A0 A1
A1
WL 2
WL1
WL 0
VDD
VDD
VDD
VDD
2-input NOR decoder
2-input NAND decoder

4-input pass-transistor based column
decoder
ut NOR decoder
A0
S0
BL 0 BL 1 BL 2 BL 3
A1
S1
S2
S3
2-inp
D
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count

4-to-1 tree based column decoder
BL 0 BL 1 BL 2 BL 3
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions:buffers
progressive sizing
combination of tree and pass transistor approaches
A0
A0
A1
A1

Decoder for circular shift-register
VDD
VDD
R
WL 0
VDD
f
f f
f
VDD
R
WL 1
VDD
f
f
f f
VDD
R
WL 2
VDD
f
f
f
f
• • •

Sense Amplifiers
C  V
Iav
tp =
make V as small
as possible
small
large
Idea: Use Sense Amplifer
output
input
s.a.
small
transition

Differential Sense Amplifier
Directly applicable to
SRAMs
M4
M1
M5
M3
M2
VDD
bit
bit
SE
Out
y

Differential Sensing ― SRAM
VDD VDD
VDD
VDD
BL
EQ
Diff.
Amp
(a) SRAM sensing scheme (b) two stage differential amplifier
SRAM cell i
WL i
Sense 2
x
x
VDD
Output
BL
PC
M3
1
M M2
M4
x
SE M5
SE
SE
Output
SE
2
x x 2
x
y
y
2
y

Latch-Based Sense Amplifier (DRAM)
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
EQ
BL BL
VDD
SE
SE

Charge-Redistribution Amplifier
Concept
M2 M3
VL VS
Vref
M1
Csmall
Clarge
Transient Response

Charge-Redistribution Amplifier―
EPROM
SE
VDD
WLC
Load
Cascode
device
Column
decoder
EPROM
array
BL
WL
Vcasc
Out
Cout
Ccol
CBL
M1
M2
M3
M4

Single-to-Differential Conversion
Diff.
S.A.
Cell
2
x
x
Output
How to make a good Vref?
WL
Vref
BL
1
2

Open bitline architecture with
dummy cells
CS
BLL
L L1 L0 R0 R1
CS
L
…
C C
S S
…
CS CS
BLR
VDD
SE
SE
EQ
Dummy cell Dummy cell

DRAM Read Process with Dummy Cell
3
2
1
0
0 3
V BL
BL
1 2
t (ns)
reading 0
3
2
1
0
0 3
V
SE
EQ WL
1 2
t (ns)
control signals
3
2
V 1
0
0 3
BL
BL
1 2
t (ns)
reading 1

Voltage Regulator
-
+
VDD
VREF
Vbias
Mdrive
Mdrive
VDL
VDL
VREF
Equivalent Model

Charge Pump

DRAM Timing

RDRAM Architecture
memory
array
ux/demux
m
network
Data
bus
Clocks
Column
Row
demux packet dec.
packet dec.
Bus
k
k3 l
demux

Address Transition Detection
DELAY
td
A0
DELAY
td
A1
DELAY
td
AN2 1
VDD
ATD ATD
…

Reliability and Yield

Sensing Parameters in DRAM
4K 64K 1M 16M 256M 4G 64G
Memory Capacity (bits /chip)
From [Itoh01]
10
100
1000
C
D
Q
,
,S
C
S
V
,
DD
V
,
smax
CD(1F)
CS(1F)
QS(1C)
Vsmax(mv)
VDD (V)
QS 5 CS VDD /2
Vsmax 5 QS /(CS 1 CD)

Noise Sources in 1T DRam
Ccross
electrode
a -particles
leakage
CS
WL
BL substrate Adjacent BL
CWBL

Open Bit-line Architecture —Cross Coupling
Sense
Amplifier
C
WL 1
BL
CBL
CWBL CWBL
C
C
WL 0
C
CBL
C C
WL D WL D WL 0 WL 1
BL
EQ

Folded-Bitline Architecture
Sense
Amplifier
C
WL1 WL1 WL0 CWBL
WL0
CWBL
C
WLD WLD
C
C C
C
BL CBL
BL CBL
EQ
x
x
y
y
…

SA
Transposed-Bitline Architecture
Ccross
BL99
(b) Transposed bit-line architecture
BL9
BL
BL
BL99
(a) Straightforward bit-line routing
SA
Ccross
BL9
BL
BL

Alpha-particles (or Neutrons)
1 Particle ~ 1 Million Carriers
WL
BL
n1
a -particle
VDD
SiO2
1
1
1
1
1
1
2
2
2
2
2
2

Yield
Yield curves at different stages of process maturity
(from [Veendrick92])

Redundancy
Redundant
columns
Memory
Array
Row Decoder
Column Decoder
Redundant
rows
Row
Address
Column
Address
: Fuse
Bank

Error-Correcting Codes
Example: Hamming Codes
e.g. B3 Wrong
with
1
1
0
= 3

Redundancy and Error Correction

PERIPHERY
ROW
DEC
selected
CHIP
COLUMN DEC
nCDE VINT f
mCDE VINT f
C f
PTVINT
IDCP
non-selected
ARRAY
m
n
m(n 2 1)ihld
miact
Sources of Power Dissipation in
Memories
VDD
VSS
S CiDVif1S
IDD 5 IDCP
From [Itoh00]

Data Retention in SRAM
(A3
)00n
100n
1.30u
1.10u
900n
700n
500n
0.00 .600 1.20 1.80
Factor 7
0.13mm CMOS
0.18mm CMOS
VDD
I
leakag
e
SRAM leakage increases with technology scaling

Suppressing Leakage in SRAM
SRAM
cell
SRAM
cell
SRAM
cell
VDD,int
VSS,int
sleep
SRAM
cell
SRAM
cell
SRAM
cell
VDD,int
sleep
VDD
low-threshold transistor VDD VDDL
sleep
Reducing the supply voltage
Inserting Extra Resistance

Data Retention in DRAM
From [Itoh00]

Case Studies
 Programmable Logic Array
 SRAM
 Flash Memory

PLA versus ROM
 Programmable Logic Array
structured approach to random logic
“two level logic implementation”
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
 Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLA’s has drastically reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
But …

Programmable Logic Array
GND GND GND GND
GND
GND
VDD
GND
VDD X 0 X 2
X 1 X 2
X 0 X 1
AND-plane
f0 f1
OR-plane
Pseudo-NMOS PLA

Dynamic PLA
GND
VDD
VDD
f0 f1 GND
X 2
f AND
X 0
f AND
f OR
f OR
X 0 X 1 X 1 X 2
AND-plane OR-plane

Clock Signal Generation
for self-timed dynamic PLA
f
tpre teval
f AND
f
f AND
f AND
f OR
f OR
(a) Clock signals (b) Timing generation circuitry
DummyAND row
DummyAND row

PLA Layout
VDD GND

And-Plane Or-Plane
x0 x0 x1 x1 x2 x2
Pull-up devices
f0 f1
Pull-up devices

4 Mbit SRAM
Hierarchical Word-line Architecture

Bit-line Circuitry
Bit-line
load
Block
select ATD
BEQ
Local WL
Memory cell
I/O line
B/T
CD I/O
Sense amplifier
CD CD
I/O
B/T

Sense Amplifier (and Waveforms)
BS
I/O I/O
DATA
Block
select ATD
SA BS SA
BS
SEQ
SEQ
SEQ
SEQ
SEQ
Dei
Address
ATD
BEQ
Vdd
I/O Lines
GND
SEQ
Vdd
SA, SA
GND
DATA
Data-cut

1 Gbit Flash Memory
From [Nakamura02]

Writing Flash Memory
Rea
100
0V 1V 2V 3V
Number o
Vf
t o
c
fe
m
ll
es
mory cells
4V
From [Nakamura02]
108
106
104
102
Evolution of thresholds Final Distribution

125mm2 1Gbit NAND Flash Memory
10.7mm
11.7mm
Charge
pump
2kB
Page
buffer
&
cache
16896 bit lines
From [Nakamura02]
32 word lines
x 1024 blocks

125mm2 1Gbit NAND Flash Memory
 Technology
 Cell size
 Chip size
 Organization
 Power supply
 Cycle time
 Read time
 Program time
 Erase time
From [Nakamura02]
0.13m p-sub CMOS triple-well
1poly, 1polycide, 1W, 2Al
0.077m2
125.2mm2
2112 x 8b x 64 page x 1k block
2.7V-3.6V
50ns
25s
200s / page
2ms / block

Semiconductor Memory Trends
(up to the 90’s)
Memory Size as a function of time: x 4 every three years

(updated)
From [Itoh01]

Trends in Memory Cell Area
From [Itoh01]

Technology feature size for different SRAM generations

chapter-12memory.pptx

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