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  1. 1. 1 Presented by :- SUSHANT MISHRA EC-2 Under the guidance of :- FinFETs: From Circuit to Architecture
  2. 2. Talk Outline <ul><li>Background </li></ul><ul><li>Low Power FinFET Circuits </li></ul><ul><ul><li>Unusual Logic Styles </li></ul></ul><ul><ul><li>Unusual Dual-V dd /Dual-V th Circuits </li></ul></ul><ul><li>Architectural Impact </li></ul><ul><li>Other Ongoing Work </li></ul><ul><li>Conclusions </li></ul>2
  3. 3. Why Double-gate Transistors ? <ul><li>DG-FETs can be used to fill this gap </li></ul><ul><li>DG-FETs are extensions of CMOS </li></ul><ul><ul><li>Manufacturing processes similar to CMOS </li></ul></ul><ul><li>Key limitations of CMOS scaling addressed through </li></ul><ul><ul><li>Better control of channel from transistor gates </li></ul></ul><ul><ul><li>Reduced short-channel effects </li></ul></ul><ul><ul><li>Better Ion/Ioff </li></ul></ul><ul><ul><li>Improved sub-threshold slope </li></ul></ul><ul><ul><li>No discrete dopant fluctuations </li></ul></ul>3 Non-Si nano devices Bulk CMOS Feature size 32 nm 10 nm DG-FETs Gap
  4. 4. What are FinFETs? <ul><li>Fin-type DG-FET </li></ul><ul><ul><li>A FinFET is like a FET, but the channel has been “turned on its edge” and made to stand up </li></ul></ul>4 Si Fin
  5. 5. Independent-gate FinFETs <ul><li>Both the gates of a FET can be independently controlled </li></ul><ul><li>Independent control </li></ul><ul><ul><li>Requires an extra process step </li></ul></ul><ul><ul><li>Leads to a number of interesting analog and digital circuit structures </li></ul></ul>5 Back Gate Oxide insulation
  6. 6. FinFET Width Quantization <ul><li>Electrical width of a FinFET with n fins: W = 2* n * h </li></ul><ul><li>Channel width in a FinFET is quantized </li></ul><ul><li>Width quantization is a design challenge if fine control of transistor drive strength is needed </li></ul><ul><ul><ul><li>E.g., in ensuring stability of memory cells </li></ul></ul></ul>6 FinFET structure Ananthan, ISQED’05
  7. 7. Talk Outline <ul><li>Background </li></ul><ul><li>Low Power FinFET Circuits </li></ul><ul><ul><li>Unusual Logic Styles </li></ul></ul><ul><ul><li>Unusual Dual-V dd /Dual-V th Circuits </li></ul></ul><ul><li>Architectural Impact </li></ul><ul><li>Other Ongoing Work </li></ul><ul><li>Conclusions </li></ul>
  8. 8. Motivation: Power Consumption <ul><li>Traditional view of CMOS power consumption </li></ul><ul><ul><li>Active mode: Dynamic power (switching + short circuit + glitching) </li></ul></ul><ul><ul><li>Standby mode: Leakage power </li></ul></ul><ul><li>Problem: rising active leakage </li></ul><ul><ul><li>40% of total active mode power consumption (70nm bulk CMOS) † </li></ul></ul>† J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction techniques,” in Proc. ICCAD, 2002.
  9. 9. Logic Styles: NAND Gates SG-mode NAND IG-mode NAND LP-mode NAND IG/LP-mode NAND pull up bias voltage pull down bias voltage IG-mode pull up LP-mode pull down
  10. 10. Comparing Logic Styles † Average leakage current for two-input NAND gate (V dd = 1.0V) Design Mode Advantages Disadvantages SG Fastest under all load conditions High leakage † (1 μ A) LP Very low leakage (85nA), low switched capacitance Slowest, especially under load. Area overhead (routing) IG Low area and switched capacitance Unmatched pull-up and pull-down delays. High leakage (772nA) IG/LP Low leakage (337nA), area and switched capacitance Almost as slow as LP mode
  11. 11. FinFET Circuit Power Optimization <ul><li>Construct FinFET-based Synopsys technology libraries </li></ul><ul><li>Extend linear programming based cell selection † for FinFETs </li></ul><ul><li>Use optimized netlists to compare logic styles at a range of delay constraints </li></ul>† D. Chinnery and K. Keutzer, “Linear programming for sizing, V dd and V t assignment,” in Proc. ISLPED , 2005. Benchmark Minimum-delay synthesis in Design Compiler SG-mode netlist Power-optimized mixed-mode netlists SG+ IG/LP SG+IG SG+LP Linear programming based cell selection 32 nm PTM FinFET models Delay/power characterization in SPICE LP IG/LP IG SG Synopsys libraries 32 nm PTM inFET models FinFET models (UFDG, PTM) Logic gate designs Logic gate designs
  12. 12. Power Consumption of Optimized Circuits <ul><li>Leakage power savings </li></ul><ul><li>110% a.t. (68.5%) </li></ul><ul><li>120% a.t. (80.3%) </li></ul><ul><li>Total power savings </li></ul><ul><li>110% arrival time (a.t.) (34%) </li></ul><ul><li>120% a.t. ( 47.5%) </li></ul>Estimated total power consumption for ISCAS’85 benchmarks V dd = 1.0V, α = 0.1, 32nm FinFETs Available modes
  13. 13. Talk Outline <ul><li>Background </li></ul><ul><li>Low Power FinFET Circuits </li></ul><ul><ul><li>Unusual Logic Styles </li></ul></ul><ul><ul><li>Unusual Dual-V dd /Dual-V th Circuits </li></ul></ul><ul><li>Architectural Impact </li></ul><ul><li>Other Ongoing Work </li></ul><ul><li>Conclusions </li></ul>
  14. 14. Dual-V dd FinFET Circuits <ul><li>Conventional low- </li></ul><ul><li>power principle: </li></ul><ul><ul><li>1.0V V dd for critical logic, 0.7V for off-critical paths </li></ul></ul><ul><li>Our proposal: overdriven gates </li></ul><ul><ul><li>Overdriven FinFET gates leak a lot less! </li></ul></ul>1.08V 1V Leakage current Vin Reverse bias V gs =+0.08V Overdriven inverter Higher V th
  15. 15. <ul><li>Using only two V dd ’s saves leakage only in P-type FinFETs, but not in N-type FinFETs </li></ul><ul><li>Solution </li></ul><ul><ul><li>Use a negative ground voltage (V H ss ) to symmetrically save leakage in N-type FinFETs </li></ul></ul>V th Control with Multiple V dd ’s (TCMS) V dd H V ss H V dd L V ss L TCMS buffer Symmetric threshold control for P and N V dd H 1.08V V dd L 1.0V V ss H -0.08V V ss L 0.0V
  16. 16. Exploratory Buffer Design <ul><li>Size of high-V dd inverters kept small to minimize leakage in them </li></ul><ul><li>Wire capacitances not driven by high-V dd inverters </li></ul><ul><li>Output inverter in each buffer overdriven and its size (and switched capacitance) can be reduced </li></ul>l opt S 1 S 2 V H dd V H ss V L ss V L dd S 1 S 2 V H dd V H ss V L ss V L dd i i’
  17. 17. Power Savings <ul><li>Benchmarks are nets extracted from real layouts and scaled to 32nm </li></ul><ul><ul><li> </li></ul></ul>Power component Savings Dynamic power -29.8% Leakage power 57.9% Total power 50.4%
  18. 18. Fin-count Savings <ul><li>Transistor area is measured as the total number of fins required by all buffers </li></ul><ul><li>TCMS can save 9% in transistor area </li></ul>
  19. 19. TCMS Extension Delay-minimized netlist Power : 283.6uW Area: 538 fins Power-optimized netlist Power : 149.9uW Area: 216 fins
  20. 20. Power Reduction (ISCAS’85 Benchmarks)
  21. 21. Power-minimized vs Delay-minimized Netlists at 130% ATC TCMS TCMS (Single-Vth Dual-Vdd % reduction in dynamic power 53.3 49.8 51.4 % reduction in leakage power 95.8 95.7 95.8 % reduction in total power 67.6 65.3 66.3 % reduction in Fin-count 65.2 59.5 61.6
  22. 22. Talk Outline <ul><li>Background </li></ul><ul><li>Low Power FinFET Circuits </li></ul><ul><ul><li>Unusual Logic Styles </li></ul></ul><ul><ul><li>Unusual Dual-V dd /Dual-V th Circuits </li></ul></ul><ul><li>Architectural Impact </li></ul><ul><li>Other Ongoing Work </li></ul><ul><li>Conclusions </li></ul>
  23. 23. Orion-FinFET <ul><li>Extends ORION for FinFET-based power simulation for interconnection networks </li></ul><ul><li>FinFET power libraries for various temperatures and technologies nodes </li></ul><ul><li>Power breakdown of interconnection networks for different FinFET modes </li></ul><ul><li>Power comparison for different FinFET modes under different traffic patterns </li></ul>
  24. 24. Router Microarchitecture & Pipeline Stages
  25. 25. Power Simulation Flow
  26. 26. Power Breakdown for SG/LP Modes <ul><li>4X4 mesh network: 5 ports/router, 48-flit buffer/port </li></ul><ul><li>Flit width = 128 bits </li></ul><ul><li>Clock frequency = 1GHz </li></ul>Router power breakdown Network power breakdown
  27. 27. Bulk CMOS vs. LP-mode FinFETs <ul><li>Bulk CMOS simulation: 32nm predictive technology model </li></ul><ul><li>Leakage power of bulk CMOS network 2.68X as compared to an LP-mode FinFET network </li></ul>
  28. 28. Router Leakage Power vs. Temp. <ul><li>Leakage power of SG-mode router grows much faster with temp. than for LP-mode </li></ul><ul><li>Leakage power ratio at 105 o C: 7:1 </li></ul>
  29. 29. Talk Outline <ul><li>Background </li></ul><ul><li>Low Power FinFET Circuits </li></ul><ul><ul><li>Unusual Logic Styles </li></ul></ul><ul><ul><li>Unusual Dual-V dd /Dual-V th Circuits </li></ul></ul><ul><li>Architectural Impact </li></ul><ul><li>Other ongoing work </li></ul><ul><li>Conclusions </li></ul>
  30. 30. FinFET SRAM and Embedded DRAM Design <ul><li>FinE: Two-tier FinFET simulation framework for FinFET circuit design space exploration: </li></ul><ul><ul><li>Sentaurus TCAD+UFDG SPICE model </li></ul></ul><ul><ul><li>Quasi Monte-Carlo simulation for process variation analysis </li></ul></ul><ul><ul><li>Thermal analysis using ThermalScope </li></ul></ul><ul><ul><li>Yield estimation </li></ul></ul><ul><li>Variation-tolerant ultra low-leakage FinFET SRAMs at lower technology nodes </li></ul><ul><li>Gated-diode FinFET embedded DRAMs </li></ul>
  31. 31. Extension of CACTI for FinFETs <ul><li>Selection of any of the FinFET SRAM and embedded DRAM cells </li></ul><ul><li>Use of any of the FinFET operating modes </li></ul><ul><li>Scaling of FinFET designs from 32nm to 22nm, 16nm and 10nm technology nodes </li></ul><ul><li>Accurately modeling the behavior of a wide range of cache configurations </li></ul>
  32. 32. FPGA vs. ASICs NATURE CMOS fabrication compatible Nano RAM on-chip storage Run-time reconfiguration Temporal logic folding Design flexibility Logic density <ul><li>Distributed non-volatile nano RAMs: main storage for reconfiguration bits </li></ul><ul><li>Fine-grain reconfiguration (even cycle-by-cycle) and logic folding </li></ul><ul><ul><li>More than an order of magnitude increase in logic density and area-delay product </li></ul></ul><ul><ul><li>Competitive performance and moderate power consumption </li></ul></ul><ul><ul><li>Non-volatility: useful in low power & secure processing </li></ul></ul><ul><li>NanoMap to map application to NATURE </li></ul><ul><ul><li>Significant area-delay trade-off flexibility </li></ul></ul>
  33. 33. Conclusions <ul><li>FinFETs a necessary semiconductor evolution step because of bulk CMOS scaling problems beyond 32nm </li></ul><ul><li>Use of the FinFET back gate leads to very interesting design opportunities </li></ul><ul><li>Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption </li></ul><ul><li>TCMS able to reduce both delay and subthreshold leakage current in a logic circuit simultaneously </li></ul><ul><li>Time has arrived to start exploring the architectural trade-offs made possible by switch to FinFETs </li></ul>