comparator used in mixed signal design----VLSI and advanced analog cmos design

1. – 1 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
CMOS Comparator

2. Comparator
– 2 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Transfer characteristic
(ideal)
Circuit symbol
Detects the polarity of the analog input signal and produces a digital output
(1 or 0) accordingly – threshold-crossing detector
Vi
Vo
“1”
“0”
Vth
Φ
Vi
Vo (“Digital”)
Vth

3. Applications
– 3 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Voltage/current level comparison (A/D conversion)
• Digital communication receivers (“slicer” or decision circuit)
• Sense amplifier in memory readout circuits
• Power electronics with digital control (dc-dc converter)

4. Design Considerations
– 4 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Accuracy (offset, noise, resolution)
• Settling time (tracking BW, regeneration speed)
• Sensitivity (gain)
• Metastability (any decision is better than no decision!)
• Overdrive recovery (memory)
• CMRR
• Power consumption

5. Comparator
– 5 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Amplification Clipping
• Precise gain and linearity are often unnecessary → simple, low-gain, open-
loop, wideband amplifiers + latch (positive feedback)
• More gain can be derived by cascading multiple gain stages
• Built-in sampling function with latched comparators
Vth
Vi
Vth
Vm
Vth
Vo
 

6. Multi-Stage Preamp
– 6 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
A(ω)
Vi
A(ω) A(ω)
… Vo
Vi
CL gmVi CL
RL gmVi+1
Vi+1
… …
  
 

0
0
0 L L
A
A ω
1 j ω / ω
ω 1/R C
 
 
 
 
 
   
 
   
 
  
 
   
N
N
0 0
N 2
0
0
1
N
0 N
N 3dB 3dB 0
A A
A ω
1 j ω / ω 1 ω / ω
A
A ω ω , ω ω 2 1
2
N stages:

7. Step Response
– 7 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
 
 
τ
τ τ

  
  
  
 
t/
1 in 0
in 0
in m L
L L
m
in
L
V V A 1 e
V A t / for t
t
V g R
R C
g
V t
C

 
     
 
 
 
   
 
 

L
2
t t
2
m m
1 m in in 2 m 1 in
L L L L
0 0
N
t N
m
N N m N 1 in
L L
0
Ignore R in all stages,
g g
1 1 1
V g V dt V t, V g V dt V t
C C C 2 C
g
1 t
For small V , V g V dt V
C N! C
Vin gmVin CL
RL gmV1
V1
…
V2

8. Optimum N
– 8 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
i
N
L
m
N
o
o
V
C
g
N!
t
V
,
V
small
For









1 2 3 4 5 6 7 8 9 10
10
0
10
1
10
2
N
t/(C
L
/g
m
)
V
o
/V
i
=10
Vo
/Vi
=100
V
o
/V
i
=1000
 
 
  
 
 
 
1
N
o
L
m i
V
C
t N!
g V
• Given A0 = Vo/Vi, Nopt can be determined with the above equation
• For A0 < 100, typical N value ranges between 2 and 4

9. Comparison
– 9 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• A higher A0 (= Vo/Vi) requires a larger N
• In comparison, latches regenerate faster than preamps
 
  
 
o
L
m i
V
C
latch: t ln
g V
 
 
  
 
 
 
1
N
o
L
m i
V
C
t N!
g V
10
0
10
1
10
2
10
3
0
2
4
6
8
10
V
o
/V
i
t/(C
L
/g
m
)
N=1
N=3
N=5
Latch

10. Multi-Stage PA Offset
– 10 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Total input-referred
Individual stage

A1
Vos1
A2
Vos2
A3
Vos3
A1
Vos
A2 A3
  
  

T 1 2 3
os2 os3
os os1
1 1 2
A A A A
V V
V V
A A A

11. Input Offset Cancellation
– 11 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
A
Vos
Φ1
Φ2
Φ2'
Vi
Vo
C
• AC coupling at input with input-referred offset stored in C
• Two-phase operation, one phase (Φ2) is used to store offset

12. Offset Storage – Φ2
– 12 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014

 
os
os
os
c
c
V
V
A
1
A
V
V
A
V







A
Vos
Φ2
Φ2'
Vo
Vc
Closed-loop stability (amplifier in unity-gain feedback)
Ref: J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital
conversion techniques. I,” JSSC, vol. 10, pp. 371-379, issue 6, 1975.

13. Amplifying Phase – Φ1
– 13 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014

 














A
1
V
V
A
V
V
V
A
V
os
in
os
c
in
o
• Offset cancellation is incomplete if A is finite
• Input AC coupling attenuates signal gain


os
os,in
Input -referred offset :
V
V
1 A
A
Vos
Φ1
Vi
Vo
Vc

14. CF and CI of Switches
– 14 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
A
Vos
Φ2
Φ2'
Vo
Vc
• What’s the optimum phase relationship between Φ2 and Φ2'?
• Bottom-plate sampling → Φ2' switches off slightly before Φ2 (note the
operation in this phase is signal independent anyway)
Φ2'
Φ1
Φ2

15. Output Offset Cancellation
– 15 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• AC coupling at output with offset stored in C
• A must be small and well controlled (independent of Vo)
• Does not work for high-gain op-amps
A
Vos
Φ1
Φ2
Vi
Vo
C Φ1
Φ2'

16. Offset Storage – Φ2
– 16 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
   os
os
c AV
V
A
V 



• Closed-loop stability is not required
• CF and CI of Φ2' gets divided by A when referred to input
Ref: R. Poujois and J. Borel, “A low drift fully integrated MOSFET operational
amplifier,” JSSC, vol. 13, pp. 499-503, issue 4, 1978.
Vos
Φ2
Vc
Φ2'
A

17. Amplifying Phase – Φ1
– 17 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014

 
in
os
os
i
o
AV
AV
V
V
A
V




• Cancellation is complete if A is constant (independent of Vo)
• AC coupling at output attenuates signal gain
Vos
Φ1
Vi
Vo
Vc Φ1
A
os,in
Input -referred offset :
V = 0

18. Offset Cancellation w/ Auxiliary Input
– 18 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Gm1 and Gm2 are the preamp and latch, respectively
• A form of output offset cancellation technique
Ref: B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution
comparators,” JSSC, vol. 27, pp. 1916-1926, issue 12, 1992.
Vos1
S1
S4
Vi
+
Vo
+
Gm2
Vos2
C1
S3
S2
Vi
-
C2
S5
S6
RL
RL
Vo
-
Gm1

19. Offset Sampling
– 19 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Gm1 and Gm2 are grounded and the PFB of Gm2 is disabled
• Vos1 and Vos2 are amplified by Gm1 and Gm2 to appear at Vo
• When S5 & S6 open (slightly before S3 & S4), offset voltage is sampled
and stored in C1 and C2
• CF/CI of S5 & S6 gets divided by (Gm1/Gm2) when referred to input
Vos1
S1
S4
Vi
+
Vo
+
Gm2
Vos2
C1
S3
S2
Vi
-
C2
S5
S6
RL
RL
Vo
-
Gm1
• S3-S6 closed
• S1-S2 open

20. Comparison
– 20 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Differential input is amplified by Gm1 to establish an imbalance at the
output and AC coupled to the input of Gm2
• Gm2 starts regeneration with this imbalance
• S3-S6 open
• S1-S2 closed
Vos1
S1
S4
Vi
+
Vo
+
Gm2
Vos2
C1
S3
S2
Vi
-
C2
S5
S6
RL
RL
Vo
-
Gm1

21. Potential Problems
– 21 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Very complicated → slow conversion speed
• C1 and C2 and their parasitics add loading to the output
• Finite on-resistance of S5 & S6 cannot completely break PFB
• CF/CI imbalance of S5 & S6 can trigger regeneration
Vos1
S1
S4
Vi
+
Vo
+
Gm2
Vos2
C1
S3
S2
Vi
-
C2
S5
S6
RL
RL
Vo
-
Gm1

22. Razavi’s Comparator
– 22 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Even more complicated!
S1
S4
Vi
+
Vo
+
Gm2
C1
S3
S2
Vi
-
C2
S5
S6
RL
RL
Vo
-
Gm1
S7
S8
S10
S9

23. – 23 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Overdrive Recovery

24. Overdrive Recovery Test
– 24 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
A small input (±0.5 LSB) is applied to the comparator input in a cycle right
after a full-scale input is applied; the comparator should be able to resolve
to the right output in either case → memoryless
Φ
Vo
+
Vo
-
Vi
Vo
Vi = VFS Vi = -LSB/2
Φ
Vo
+
Vo
-
Vi
Vo
Vi = VFS Vi = LSB/2
“0” “1”
Case I Case II

25. Passive Clamp
– 25 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Limit the output swing
with diode clamps →
signal-dependent Ro
• Clamps add parasitics
to the PA output
M1 M2
M3 M4
Vi
+
Vi
-
M6
M5
Vo
+
Vo
-

26. Active Reset
– 26 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Kill PA gain with a
crowbar switch →
time-dependent Ro
• Switch adds parasitics
to the PA output
M1 M2
M3 M4
Vi
+
Vi
-
M5
Vo
+
Vo
-
Φ

27. PA Autozeroing
– 27 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
A
Vos
Φ1
Φ2
Φ2'
Vi
Vo
C
• Two-phase operation, Φ2 phase is used for offset storage
• Autozeroing switch Φ2' also resets and removes the PA memory
M1 M2
M3 M4
Vi
+
Vi
-
M5
Vo
+
Vo
-
Φ2'
M6

28. – 28 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
CMOS Preamplifier

29. Pull-Up
– 29 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• NMOS pull-up suffers from body effect, affecting gain accuracy
• PMOS pull-up is free from body effect, but subject to P/N mismatch
• Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion,
well, etc.) don’t track transistors; but it is fast!
M1 M2
Vi
+
Vi
-
Vo
+
Vo
-
Pull-up
 
 L
1
mL
m1
V
L
W
L
W
g
g
A
:
up
pull
diode
NMOS






 
 L
1
p
n
mL
m1
V
L
W
L
W
μ
μ
g
g
A
:
up
pull
diode
PMOS






L
m1
V R
g
A
:
up
pull
Resistor






30. To Obtain More Gain
– 30 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
M1 M2
M3 M4
Vi
+
Vi
-
Vo
+
Vo
-
Ip Ip
I
 
 3
1
p
p
n
m3
m1
V
L
W
L
W
I
2
I
2
I
μ
μ
g
g
A













• Ip diverts current away
from PMOS diodes (M3
& M4), reducing (W/L)3
• Higher gain w/o CMFB
• Needs biasing for Ip
• M3 & M4 may cut off for
large Vin, resulting in a
slow recovery

31. Bult’s Preamp
– 31 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• NMOS diff. pair loaded
with PMOS diodes and
PMOS latch (PFB)
• High DM gain, low CM
gain, good CMRR
• Simple, no CMFB
• (W/L)34 > (W/L)56
needs to be ensured
for stability
Ref: K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in
1-mm2,” JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.
M1 M2
M7
M3 M4
Vi
+
Vi
-
Vo
+
Vo
-
M5 M6

32. DM
– 32 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Vid gm1Vid ro1
1
gm3
ro3
-1
gm5
ro5
Vod
3
r
g
//r
//r
//r
g
1
//
g
1
g
A
:
gain
DM o1
m1
o5
o3
o1
m5
m3
m1
dm
V 




















M1 M2
M7
M3 M4
Vi
+
Vi
-
Vo
+
Vo
-
M5 M6

33. CM
– 33 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
 
 
    
 
 
 
cm m1
V
m1 o7 m3 m5 m3 m5 o7
g 1 1 1
CMgain: A / /
1 2g r g g 2 g g r

Vic
gm1Vgs1
2ro7
1
gm3
1
gm5
Voc
Vgs1
M1 M2
M7
M3 M4
Vi
+
Vi
-
Vo
+
Vo
-
M5 M6

34. Song’s Preamp
– 34 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• NMOS diff. pair loaded
with PMOS diodes and
resistors
• High DM gain, low CM
gain, good CMRR
• Simple, no CMFB
• Gain not well-defined
Ref: B.-S. Song et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in
Symp. VLSI Circuits, 1999, pp. 79-80.
M1 M2
M5
M4
M3
Vi
+
Vi
-
Vo
+
Vo
-
RL RL
X

35. Song’s Preamp
– 35 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
  

 
cm m1
V
m1 o5 m3
m3 o5
g 1
A
1 2g r g
1
2g r
Vid gm1Vid ro1
ro3 RL
Vod
Vic
gm1Vgs1
2ro5
1
gm3
Voc
Vgs1
DM CM
 
L
m1
L
o3
o1
m1
dm
V
R
g
//R
//r
r
g
A






36. – 36 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
CMOS Latch

37. Static Latch
– 37 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Active pull-up and pull-
down → full CMOS
logic levels
• Very fast!
• Q+ and Q- are not well
defined in reset mode
(Φ = 1)
• Large short-circuit
current in reset mode
• Zero DC current after
full regeneration
• Very noisy
M6
M5
M7
Q+
Q-
Φ
Vi
+
Vi
-
M1 M2
M3 M4

38. Semi-Dynamic Latch
– 38 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Diode divider disabled
in reset mode → less
short-circuit current
• Pull-up not as fast
• Q+ and Q- are still not
well defined in reset
mode (Φ = 1)
• Zero DC current after
full regeneration
• Still very noisy
M6
M5
M7
Φ
Φ
M8
Vi
+
Vi
-
M1 M2
M3 M4
Q+
Q-

39. Current-Steering Latch
– 39 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Constant current
→ very quite
• Higher gain in
tracking mode
• Cannot produce
full logic levels
• Fast
• Trip point of the
inverters
M1 M2
M5
Vi
+
M6
Vi
-
M4
M3
M7
Φ
M8
Φ Φ
RL RL
Q+
Q-

40. Dynamic Latch
– 40 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
• Zero DC current in
reset mode
• Q+ and Q- are both
reset to “0”
• Full logic level after
regeneration
• Slow
• No seed voltage
Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC, vol. 20, pp.
775-779, issue 3, 1985.
M4
M3
Φ
Vi
+
Vi
-
M7 M8
M5 M6
M1
Q+
Q-
M2
M9 M10 Φ
Φ
Φ

41. Modified Dynamic Latch
– 41 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
Ref: T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,”
JSSC, vol. 30, pp. 166-172, issue 3, 1995.
Φ
Vi
+
Vi
-
M7 M8
M5 M6
M1
Q+
Q-
M2
M9 M10 Φ
Φ
Φ
M4
M3
• Zero DC current in
reset mode
• Q+ and Q- are both
reset to “0”
• Full logic level after
regeneration
• Slow
• No seed voltage

42. Cho’s Comparator
– 42 –
Data Converters Comparator Professor Y. Chiu
EECT 7327 Fall 2014
M1R and M2R added to set the comparator threshold
   
   
 
 
 

   
 
 
 

   
 
 
i R
1 i t R t
i R
2 i t R t
W W
G k V V V V
L L
W W
G k V V V V
L L
 
 
 
R
th R R
i
W
V = V V
W

M2R
M1R
Φ
Vi
+
Vi
-
M7 M8
M5 M6
M1
Q+
Q-
M2
M9 M10 Φ
Φ
Φ
M4
M3
VR
-
VR
+