VTU 15CS32 ADE Notes Module-1

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Kishore Kumar R RLJIT Page 1
Module-1
FET
TOPICS:
Chapter 1:
1.1 JFET
1.2 MOSFET
1.3 Biasing MOSFETs
1.4 Differences between JFET and MOSFET
1.5 Applications of FET
1.6 CMOS Device

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Junction Field effect Transistor:
 It is three terminal device
 Voltage applied at one terminal controls the current through other two terminals.
Classification of JFETS:
JFET is classified into two types,
i) N-channel JFET ii) P-channel JFET
Construction of N-channel JFET: Symbol
 A piece of N-type semiconductor is sandwiched between two pieces of P-type
Semiconductors, therefore two P-N junctions are formed.
 Ohmic contacts are made at top and bottom of the channel, and these contacts are referred
as Drain (D) and Source (S).
 Both P-type layers are connected together and form gate (G) terminal.
 Depletion layers are formed around each P-region.
Construction of P-channel JFET: Symbol
 A piece of P-type semiconductor is sandwiched between two pieces
of N-type Semiconductors; therefore two P-N junctions are formed.
 Ohmic contacts are made at top and bottom of the channel, and these
contacts are referred as Drain (D) and Source (S).
 Both N-type layers are connected together and form gate (G)
terminal.
 Depletion layers are formed around each N-region.

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JFET Biasing:
JFET can be biased in two ways
1. JFET with Zero Gate-Source Voltage
2. JFET with Negative Gate-Source Voltage
JFET with Zero gate-Source voltage:
Operation:
 Gate terminal is directly connected to source, and keeping gate to source voltage VGS to
zero.
 Drain-Source Voltage VDS is equal to supply voltage VDD.
 VDD supply attracts free electrons to flow from source to drain, this establishes current
through the channel.
 IDSS is drain current when VGS=0
 N-channel behaves as a resistive element between its drain and source terminals.
 Because of flow of current through the channel, there is a voltage drop across the channel
resistance, which reverse biases two PN-Junctions, because of reverse biasing, the width
of the depletion region increases.
 Depletion region is wider near drain-region than the source region because drain current
and channel resistance establish more reverse bias voltage at PN junction near drain
region than source region.
ID Versus VDS for VGS=0V:
Figure below shows ID versus VDS for VGS=0, as shown in the figure, ID increases linearly
with increase in VDS and becomes constant when VDS is greater than pinch-off voltage(VP).

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Pinch-off Condition:
When VDS reaches VP, the value ID does not change with further increase in the value of
VDS, this condition is called as Pinch-off condition. This happens because depletion layers
expand when VDS=VP, the depletions layers are almost touching, this results in reduction of
channel width, therefore ID remains constant for VDS ≥VP. in the figure, VP separates two
operating regions of JFET
i) Horizontal region is called saturation region (JFET acts as current source in saturation region)
ii) Almost- vertical region is called Ohmic region (JFET acts as resistor in Ohmic region)
JFET with negative Gate-Source voltage:
Operation: When negative voltage is applied to the gate, the width of depletion region increases,
therefore pinch-off phenomenon occurs at lower values of VDS. As the value of VGS becomes
more negative the value of saturation current decreases, the negative gate to source voltage at
which ID becomes zero is called as gate –source cut off voltage VGS(off).
Output characteristics of an N-channel JFET:

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Drain current of JFET:
The relation between output current ID in saturation region for a given value of input VGS
is given as ID =IDSS (1-VGS/Vp)2
Transfer characteristics of N-channel JFET:
Output characteristics of P-channel JFET:
MOSFET:
MOSFET is abbreviated as metallic oxide semiconductor filed effect transistor, MOSFET
is also three terminal device, three terminals are
1) Drain (D)
2) Source (S)
3) Gate (G)

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MOSFET is classified into two types i) DE-MOSFET ii) E-MOSFET
N-Channel DE-MOSFET:
Construction: Symbol:
 Two highly doped N-regions (N+) are diffused into a lightly doped P-type
semiconductor, this p-region is called substrate.
 Source and drain terminals are formed by connecting metal contacts to two N+ regions as
shown in figure. Two N+ regions are linked by an channel called N-channel
 A thin layer of silicon dioxide (sio2) is deposited on top of the N-channel, sio2 is
insulator.
 The gate terminal is connected to a metal contact surface but remains insulated from N-
channel by sio2 layer.
P-channel DE-MOSFET construction:
Construction: Symbol:
 Two highly doped p-regions (p+) are diffused into a lightly doped N-type semiconductor,
this N-region is called substrate.
 Source and drain terminals are formed by connecting metal contacts to two P+ regions as
shown in figure. Two P+ regions are linked by an channel called N-channel
 A thin layer of silicon dioxide (sio2) is deposited on top of the P-channel, sio2 is insulator.
 The gate terminal is connected to a metal contact surface but remains insulated from P-
channel by sio2 layer.

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DE-MOSFET Biasing:
DE-MOSFET can be biased in three ways
i) DE-MOSFET with negative gate voltage
ii) DE-MOSFTE with Positive gate voltage
iii) DE-MOSFET with Zero gate voltage
DE-MOSFET with Zero gate voltage:
DE-MOSFET with Negative gate voltage:
Operation:
 A positive voltage (VDD) is applied between
the drain and source terminals that is VDS is
positive.
 The positive voltage at the drain terminal
attracts free electrons to flow from source to
drain, these electrons flow through channel,
hence there is flow of current through the
channel.
 The current increases with increase in VDS and
after a certain value of VDS it becomes
constant, this current is referred as IDSS.
Operation:
 When negative voltage is applied to gate, it
repels free electrons from the channel towards
P-type substrate; holes in p-type substrate are
attracted towards gate.
 Repelled electrons recombine with holes in P-
substrate, this recombination reduces the
number of free electrons in N-channel,
therefore drain current ID decreases with
increase in value of negative voltage, the
more the negative gate voltage, smaller the
drain current.

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DE-MOSFET with Positive Gate Voltage:
Enhancement and depletion regions:
 As the application of positive gate voltage increases the value of drain current, the region
of positive gate-source voltage is called as Enhancement region.
 The region of negative gate-source voltage is called depletion region.
Output characteristics curve of N-channel DE-MOSFET:
Transfer characteristic curves of N-channel DE-MOSFET:
Operation:
 When positive voltage is applied to the
gate, it attracts additional electrons from p-
type substrate, hence number of free
electrons will increase, increase number of
free electrons increases drain current.
 Drain current increases with increase in
positive voltage at gate.

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Enhancement MOSFET:
 E-MOSFET is abbreviated as Enhancement MOSFET.
 E-MOSFET operates only in enhancement region, and has no depletion region.
Construction of E-MOSFET:
E-MOSFET with VGS=0:
 Two highly doped N-regions (N+) are
diffused into lightly doped P-type
semiconductor, this p-region is called as
substrate.
 The source and drain terminals are
formed by connecting metal contacts to
two N+ regions as shown in figure.
 The channel between two N+ regions is
absent, a thin layer of silicon di-oxide is
deposited on top of the region between
Drain and source, Gate terminal is also
formed by connecting metal contact to
the region between drain and source.
Operation:
 When VGS=0 and positive voltage is applied to
Drain, there is no flow of drain current as there is
no channel available for flow of drain current.
Hence E-MOSFETs are normally called as OFF
MOSFETS, they do not conduct when VGS=0

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E-MOSFET with Positive VGS:
Output characteristics of N-channel E-MOSFET:
As shown in the figure, the value of VDS at which drain current saturates is given by VDS(sat), the
value of VDS(sat) increases with increase in VGS.
Transfer Characteristics of N-channel E-MOSFET:
Operation:
 When VGS is positive, it attracts free
electrons in P-type substrate, and holes
are repelled away from the edge of sio2
layer as shown in figure.
 When positive voltage of VGS is
increased, more and more electrons are
attracted towards surface of sio2 layer,
the electrons touching sio2 layer forms
a thin layer between source and drain,
this layer forms a channel between
drain and source, when this layer exists
free electrons can flow easily from the
source to drain, these free electrons
lead to flow of current between source
and gate, this current is called as Drain
current (ID). when positive VGS
increases ID increases.

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Threshold Voltage:
The minimum positive gate-source voltage (VGS) that leads to flow of drain current is
called as threshold voltage and is denoted by VT.
Drain current of E-MOSFET:
When VGS <VT  ID=0
VGS >VT  ID = K(VGS - VT)2
where K =ID(ON) / (VGS(ON) - VT)2
Explain Pinching Phenomenon in E-MOSFET:
Give differences between JFET and MOSFET
JFET MOSFET
JFETS operate only in depletion mode only MOSFETs can operate in both depletion
mode and Enhancement mode
Input resistance of JFET is lower than that
of MOSFET
Input resistance of MOSFETs is much
higher than that of JFETs.
Drain resistance(rd) of JFETs is higher than
that of MOSFETs
Drain resistance(rd) of MOSFETs is lower
than that of JFETs
Output characteristic curves of JFET are
more FLAT than that of MOSFETs
Output characteristic curves of MOSFET
are not FLAT
Leakage gate current in JFETs is much
higher than that of MOSFETs
Leakage current in MOSFET is much
smaller than that of JFETs
JFETs are not easier to construct. MOSFETs are easier to construct and are
used more widely than JFETs
Pinching phenomenon refers to the reduction
in the width of the channel near the drain
region with increase in drain-source voltage

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Biasing DE-MOSFETs:
There are two biasing circuits for DE-MOSFETS
1. Fixed-Bias Circuit
2. Voltage – Divider Bias Circuit
Fixed –Bias Circuit:
Problem: Determine VGS and drain current and drain-source voltage in the figure below,
given that saturation drain current is 8mA and pinch-off voltage is -2V
Sol) Given values VDD= 18v, IDSS=8mA, VGG=2v, VP= -2v RD = 0.4KΩ VGS=VGG=2v
Drain current ID = IDSS( 1-VGS/VP)2
Drain–source voltage VDS =VDD-IDRD
= 8mA (1-2/(-2))2
= 32mA = 18-32mA×0.4KΩ
= 5.2V
 Drain resistor RD, Drain supply voltage (VDD) and gate
supply voltage (VGG) are biasing components, positive
voltage VGG is applied between gate and source.
Operating point: DC drain current (ID) and drain-source
voltage VDS are collectively referred to as operating point, it
is represented as
Q (IDQ, VDSQ)
Applying KVL to Drain-source Loop we get
VDD-IDRD-VDS=0
VDS = VDD-IDRD
Hence Q ( IDQ,VDSQ) = [ IDSS(1-VGS/VP)2
, VDD-IDRD]
In feed-back bias VGS= VGG

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Voltage-Divider Biased DE-MOSFET:
Problem: Design a voltage divider bias network using a DE-MOSFET with supply voltage
VDD= 16v, IDSS = 10mA, and VP=-5v, to have quiescent drain current of 5mA and gate
voltage of 4v. (Assume drain resistor RD to be four times the source resistor RS)
Sol)
Given values,
VDD = 16v, RD =4RS, IDSS=10mA, VP=-5V IDQ = 5mA VG=4v
RD=? , RS=? R1=? R2 = ?
Drain current ID=IDSS(1-VGS/VP)2
5mA= 10mA(1-VGS/(-5))2
VGS = -1.5V
Drain resistor RD, source resistor RS R1and R2, Drain supply voltage VDD and
gate supply voltage VGG are biasing components,
In this circuit, drain current ID = IDSS (1-VGS / VP)2
Gate voltage VG = VDD (R2/ R1+R2)
Gate-source voltage  VGS = VG-VS
= VG – IS RS
= VG - ID RS (IS = ID)
Drain-source Voltage  apply KVL to DS Loop
VDD = IDRD+ISRS+VDS
VDD= IDRD+IDRS+VDS ( ID=IS)
VDS = VDD – ID(RD+RS)
Hence operating point of this circuit
Q(IDQ,VDSQ) = [IDSS (1-VGS / VP)2
, VDD – ID(RD+RS)]

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VGS=VG-VS To find R1 and R2
=VG-IDRS VG = VDD (R2 / R1 + R2)
-1.5 = 4- 5mA RS 4 = 16 (R2/R1+R2)
RS = 1.1kΩ R1 = 3R2
Since RD = 4RS choose R2=1KΩ hence R1=3KΩ
RD = 4.4KΩ
Hence the values of all resistors are determined
Biasing E-MOSFETS:
There are two ways of biasing for E-MOSFET
1. Feed-Back Bias
2. Voltage –Divider Bias
Feed-Back Biased E-MOSFET:
Graphical Method to find operating point of Feedback biased E-MOSFET:
Step1: draw transfer characteristics of E-MOSFET
Step2:draw a load line using equation VGS=VDD-IDRD 1
Put ID=0 in equation 1 VGS=VDD hence point (VDD,0) lies on x-Axis
Put VGS=0 in equation 1 ID=VDD/RD, hence point (0,VDD/RD) line son y-axis
Load line is obtained by joining points (VDD,0) and (0,VDD/RD) as shown in above figure, the
point of intersection between DC load line and curve gives value of VDSQ and IDQ
Drain-Gate loop: Drain-source Loop
Apply KVL to DG loop Apply KVL to DS Loop
VDD=IDRD+IGRG+VGS VDD=IDRD+VDS
VGS = VDD-IDRD (IG=0) VDS = VDD - IDRD
In this circuit VGS =VDS
Hence Operating point of this circuit Q(IDQ,VDSQ) is
Q [K(VGS-VT)2
, VDD-IDRD]

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Voltage –Divider biased E-MOSFET:
Graphical method to determine VDSQ, IDQ, VGSQ:
Applications of FET:
Buffer Amplifier: Since JFET has high input resistance and Low output resistance, it can be
used as Buffer amplifier.
Low-Noise Amplifiers: FETs are Low-noise devices, hence they are used as Low-noise
amplifiers.
Drain current:
ID = K(VGS-VT)2
Drain –source Voltage:
Applying KVL to DS loop, we get
VDD=IDRD+VDS+ISRS
VDD=IDRD+VDS+IDRS (ID=IS)
VDS = VDD-ID(RD+RS)
Hence operating point Q(IDQ,VDSQ) =[K(VGS-VT)2
, VDD-ID(RD+RS)]
Gate voltage VG = VDDR2/R1+R2
Gate-source voltage VGS = VG-IDRS
Step1: Draw Transfer characteristics of E-MOSFET
Step 2: Draw a load line using equation VGS = VG-IDRS
1
Put ID=0 in equation 1 we get VGS=VG the point (VG,0)
lie son x-axis
Put VGS=0 in equation we get ID=VG/RS the point (0,
VG/RS) lies on y-axis
Load line is obtained by joining the points (VG,0) and
(0,VG/RS)
The intersection point of Load-line and curve give VGSQ
and IDQ
Step3: the value of VDSQ is obtained by using equation
VDSQ=VDD-IDQ(RD+RS)

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Analog Switch:
FETs can be used as Analog Switch
FET as Multiplexer:
Operation:
Input signals are applied to drain terminals of JFET, control inputs are applied to gate
terminals of JFETs, when control input of any FET is made 0 and control inputs of all other
FETs are made more negative, the input of FET with control input 0 will be transferred to output,
inputs of all other FETs are blocked since their control inputs are negative.
Current Limiter:
FET can be used current limiter in saturation since current remains constant in this region.
Operation:
When VGG is not applied to FET, it operates in saturation region,
and acts as closed switch.
When VGG is applied, FET operates in cut-OFF region and acts as
open switch.

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CMOS Devices:
CMOS is abbreviated as complementary metallic oxide semiconductor, CMOS device
uses both P-type and N-type E-MOSFETs.
CMOS Inverter: Simplified Diagram of CMOS
Operation:
Case(1) : When Vin is HIGH
When input voltage is HIGH, that is equal to VSS , gate to source voltage of VGS2 of P-
channel E-MOSFET is 0 hence Q2 is OFF, gate-source voltage (VGS1) of N-channel E-MOSFET
is equal to VSS, hence N-channel E-MOSFET is ON, the equivalent circuit of CMOS inverter
when Vin=HIGH is shown in figure B
Hence when Vin =HIGH Vout = 0
Case (2) when Vin is LOW
When input voltage is LOW, that is equal to 0 , gate to source voltage of VGS2 of P-
channel E-MOSFET is -VSS hence Q2 is ON, gate-source voltage (VGS1) of N-channel E-
MOSFET is equal to 0, hence N-channel E-MOSFET is ON, the equivalent circuit of CMOS
inverter when Vin=LOW is shown in figure below

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Hence when Vin =HIGH Vout = 0
Advantages of CMOS devices:
 Power consumption is very Low.
 Input resistance is very high
 Small in size
Disadvantage: CMOS devices offer
Important Questions
1. Explain working of N-channel DE-MOSFET with help of neat diagram. (JUL-17) (12 M)
2. With circuit diagram, explain any two applications of FET (JAN-17)(6 M)
3. Design a voltage Divider bias network using a DE-MOSFET with supply voltage VDD=16v,
IDSS=10mA and VP=5v to have a quiescent drain current of 5mA and gate voltage of 4v (Assume
Drain resistor RD to be four times the source resistor RS and R2 = 1KΩ) (JAN-17)(8 M)
4. Explain construction and working principle N-channel E-MOSFET
5. with Neat diagram explain how CMOS can be used as inverting switch
6. Give differences between JFET and MOSFET
7. Explain Voltage-divider biased E-MOSFET.
8. Determine VGS and drain current and drain-source voltage in the figure below, given that
saturation drain current is 8mA and pinch-off voltage is -2V
9. Explain working of N-channel DE-JFET with help of neat diagram

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Chapter -2
OP-AMP
Operational Amplifier: An operational amplifier is popularly known as OP-AMP
Circuit Representation of OP-AMP:
 An OP-AMP is two input and one output device, it has two power supplies
 The (+) input is non-inverting input.
 The (-) input is inverting input.
Voltage gain of OP-AMP (Ad):
It is defined as ratio of output voltage to input voltage
Ad = Vout / Vd
Where Ad  differential input voltage, Vd  differential input voltage Vd = V1-V2
Ideal OP-AMP versus Practical OP-AMP:
Ideal OP-AMP Practical OP-AMP
1. input resistance is very high 1. input resistance Ri= ∞
2. output resistance is very Low 2. output resistance Ro =0
3. gain Ad is very high 3. Gain Ad = ∞
Thevenin’s Equivalent Model of Practical OP-AMP:

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Thevenin’s Equivalent Model of Ideal OP-AMP:
Performance Parameters of an OP-AMP:
The following are the performance parameters of an OP-AMP
1. Bandwidth
2. Slew Rate
3. Open-Loop Gain
4. Common-Mode Rejection ratio (CMRR)
5. Power supply Rejection Ration (PSRR)
6. Input Resistance
7. Output Resistance
8. Settling Time
9. Offsets and Offset Drifts
Bandwidth of an OP-AMP:
It is defined as Range of frequencies OP-AMP can amplify.
Frequency response of an OP-AMP:
Bandwidth of OP-AMP = fu
As shown in figure Gain falls after fu(cut –off frequency) at the rate of 6dB per octave or 20 dB
per decade

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Slew Rate:
It is defined as rate of change of output with time, it is denoted by SR
SR = ∆Vout / ∆t
When the input signal of an OP-AMP is large and frequency is high, distortion occurs in output
signal, this distortion is called as Slew-Rate distortion
SR = 2πfmax VP where fmax  highest frequency of input signal
Vp peak voltage of input signal
Open-loop gain:
Common mode gain:
Common-Mode Rejection Ratio:
It is ratio of differential gain (Ad) to common mode gain (ACM)
CMRR = Ad / ACM
CMRR in decibels = 20 log10(Ad/ACM)
Ability of OP-AMP to reject to noise signals which appear as common input for an op-amp is
called as common-mode rejection ratio.
Power Supply rejection Ratio:
It is defined as ratio of change in power supply voltage to change in output voltage
PSRR = ∆V/ ∆Vout
Input Resistance:
It is resistance measured at either inverting terminal or non-inverting terminal while the
other input terminal is grounded, it is denoted as Ri
Output Resistance:
It is resistance measured between output terminal of OP-AMP and the ground, it is
denoted as Ro.
Settling time:
It is defined as the time taken by the OP-AMP output to settle within a specified
percentage of final value.
Open-Loop gain is differential gain in the absence of feedback
A(OL) = Vout/Vd
When same voltage is applied to both input terminals of an OP-
AMP, It is said to be operating in Common mode configuration,
VCM is common Mode input, the ratio of output voltage to the
common mode input VCM is called as common mode voltage gain
ACM
ACM = Vout / VCM

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OFFSETs:
There are four OFFSET parameters of an OP-AMP
1. Output OFFSET Voltage
2. Input OFFSET Voltage
3. Input OFFSET Current
4. Input Bias Current
Output OFFSET Voltage:
The practical OP-AMP some output voltage even though both input terminals are
grounded, such an output voltage is called output OFFSET voltage. It is denoted as Voo.
Input OFFSET Voltage:
The differential input voltage that exists between two input terminals of an OP-AMP
even though both inverting and non-inverting terminals are grounded is called as input offset
voltage, it is denoted as ‘VIO.
Input OFFSET Current:
It is difference between two input bias currents IB1 and IB2 flowing towards the inputs of
an OP-AMP, it is denoted as IIO. IIO = IB1 – IB2
Input Bias Current:
It is average of two bias currents IB1 and IB2
IB = (IB1+IB2 ) / 2

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Offset Drifts:
The rate of change of offset parameters per unit change in temperature is called as Offset
drifts
∆VIO / ∆T  drift in input offset voltage (µV/0c)
∆IIO / ∆T  drift in input offset current (pA/0c)
∆IB / ∆T  drift in input Bias current (pA/0c)
∆VOO / ∆T  drift in output offset voltage (µV/0c)
Applications of OP-AMP: following are the applications of OP-AMP
1. Peak-detector circuit
2. Comparator
3. Non-linear Amplifier
4. Filter
5. Voltage-current converter
6. Current-voltage converter
Peak-Detector Circuit:
Peak- detector circuit produces a voltage at the output equal to peak voltage of input
signal, the above figure shows positive peak amplitude of the input signal.
Operation:
When a sine signal is applied at the input of op-amp 1, During positive cycle, the
output of op-amp1 is also positive, which makes diode forward biased, hence capacitor starts
charging, it charges to Vp. the voltage across capacitor Vp is applied as input to OP-AMP 2
which is voltage follower, hence the voltage VP appears at the output of second OP-AMP.
Note: this circuit can be made to detect the negative peak by reversing the direction of diode.
Comparator:
 It is a circuit which compares a input signal voltage (Vin) at one input of OP-AMP with
reference voltage (VRef) at the other input.
 Comparator produces either positively saturated or negatively saturated output voltage
depending up on whether the value of voltage applied at the one terminal is more or less
positive than the voltage applied at the other terminal.

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Non-Inverting Comparator:
Inverting Comparator:
Non-Inverting Zero-Crossing Detector:
In this comparator, the input voltage is applied to non-inverting terminal, and inverting
terminal is grounded (Vref=0),
When Vin voltage is greater than zero, output voltage vout is equal to Vsat,
When Vin voltage is less than zero, output voltage vout is equal to -Vsat,

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Transfer characteristics of Non-inverting Zero-Crossing Detector:
Inverting Zero-Crossing Detector:
In Inverting Zero-Crossing detector, input voltage Vin is applied to inverting terminal and
non-inverting terminal is grounded.
When Vin>0 Vout = -Vsat
When Vin<0 Vout = +Vsat
Transfer Characteristics of Inverting Zero-Crossing Detector:
When Vin >0 Vout = +Vsat
When Vin <0 Vout = -Vsat

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Inverting Comparator with Hysteresis:
Operation:
Case (1) when Vout = +Vsat
When output voltage is equal to positive saturation voltage, Vout = +Vsat, The voltage at
non-inverting input is V+ = VsatR1 / R1+R2, this voltage is called Upper trigger voltage VUT
VUT= VsatR1 / R1+R2
When Vin>VUT Vout = -Vsat
When input voltage becomes more positive than Vut the output changes from +Vsat to -Vsat
Case (2) When Vout = -Vsat
When Vout = -Vsat, the voltage atnon- inverting terminal is V+ = –VsatR1/R1+R2, this voltage is
called as Lower trigger voltage VLT, VLT = –VsatR1/R1+R2
When Vin becomes slightly less than lower trigger voltage (VLT) , the output changes
from –Vsat to +Vsat
When Vin < VLT Vout = +Vsat
Hysteresis of Inverting comparator:
When Vin of inverting comparator exceeds VUT, its output switches from +Vsat to -Vsat,
when Vin goes below VLT, the output switches from –Vsat to +Vsat, Hysteresis Voltage (VH) is
equal to difference between VUT and VLT.
VH = VUT - VLT
= (Vsat R1 / R1+R2) - (-Vsat R1 / R1+R2)
VH = 2(Vsat R1 / R1+R2)

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Non-Inverting Comparator with Hysteresis:
Input voltage is applied to non-inverting input terminal of OP-AMP
Upper trigger voltage VUT= Vsat R1/R2
Lower Trigger Volatge VLT= -Vsat R1/R2
Operation:
Case(1): When Vout= -Vsat
When Vout=-Vsat, and if Vin becomes greater than upper trigger voltage VUT= Vsat R1/R2,
output changes from –Vsat to +Vsat
Case(2): When Vout =+Vsat
When Vout=+Vsat, and if Vin becomes more negative than Lower trigger voltage
VLT= -Vsat R1/R2, output changes from +Vsat to -Vsat.
Hysteresis of non-inverting comparator:
Hysteresis VH = VUT-VLT
= ( Vsat R1/R2) – (-Vsat R1/R2)
VH = 2VsatR1/R2

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Window Comparator:*********
In Window Comparator, there are two reference voltages called Lower and upper trip
points, UTP (Upper Trip Point) LTP (Lower Trip Point)
A1  Inverting Comparator A2 Non-Inverting Comparator
Operation:
Case 1: When Vin < LTP
When Vin<LTP output of A1 is +Vsat, hence D1 is forward Biased, output of A2 is –
Vsat hence D2 is reverse Biased, the output of A1 is connected to output hence output voltage is
equal to +Vsat.
When Vin < LTP Vout = +Vsat
Case 2 : When Vin >UTP
When Vin>UTP, output of A1 is –Vsat, output of A2 is +Vsat, hence D1 and D2 are
reverse and forward biased respectively, the output of A2 is connected to Vout
When Vin > UTP Vout = -Vsat
Case 3: When LTP < Vin <UTP
When Vin is greater than LTP and Less than UTP, outputs of both OP-AMPs are –Vsat,
hence both diodes are reverse biased, hence output of neither op-amp is connected to Vout,
hence Vout is zero
When LTP < Vin < UTP Vout = 0
Transfer characteristics of Window-Comparator:

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Non-Linear Amplifier:
An amplifier in which gain is very large for weak input signals, and very small for large
input signals is referred to as Non-Linear Amplifier.
Operation:
 For small values of input signal, diodes acts as open circuit and gain is high due to
minimum feedback.
 For Large values of input signal, diodes conduct and offer very small resistance and thus
gain is Low.
Application of Non-Linear Amplifier:
As shown in figure, output of Bridge is connected to Non-linear amplifier, for large
variations of bridge output nonlinear amplifier produces small variations which can be measured
using Milli-Voltmeter. If bridge output is connected directly to Milli-voltmeter, the large
variations of bridge output cannot be measured in it, hence Non-Linear amplifier can be used
between bridge and Milli-Voltmeter.

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Relaxation Oscillator:
An Oscillator which produces Non-Sinusoidal output is called as Relaxation Oscillator.
Operation:
Assume initial output of OP-AMP is at +Vsat, hence voltage at non-inverting terminal is
V+ = +VsatR1 / R1+R2, when Vsat is applied to capacitor it starts charging, when capacitor
voltage exceeds the voltage at non-inverting terminal output of OP-AMP changes from +Vsat to
–Vsat.
Now, Vout = --Vsat, the voltage appearing at non-inverting input is –VsatR1 / R1+R2,
when –Vsat is applied capacitor starts discharging, when capacitor voltage becomes more
negative than the voltage at non-inverting input, the output switches from –Vsat to +Vsat.
The charging and discharging of capacitor continues and cycle repeats to produce
rectangular output waveform as shown in the figure.
Time period of output waveform T = 2RCln(1+B/1-B)
B Feed-back Fraction B= R1/R1+R2
Current to Voltage Converter:

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Current –Voltage converter converts the input current into proportional Output Voltage.
It has zero input impedance, and Zero Output impedance.
Output Voltage:
Vout = -- Ii ×R
Input Impedance : Zi = R / 1+AOL
Output Impedance: Zout = Ro / 1 + AOL where Ro  output impedance of OP-AMP
Voltage to current Converter:
Voltage –current converter converts an input voltage into proportional output current, the
voltage across resistor R1 is applied to inverting terminal, voltage across R1 is proportional to
output current.
Output current Iout = Vin/R1
Input impedance of circuit  Zin = Ri [(1+AOL) R1/R1+R2]
Output impedance of Circuit  Zout = R1 [(1+AOL)R1/R1+R2]
Filter:
A filter is a circuit that is designed to pass a specified band of frequencies and rejects all
signals outside that band.
Classification of Filters:
The filters are classified as i) Active Filters ii) Passive Filters
Passive Filters: Passive Filters uses only passive elements such as resistors, inductors, and
capacitors
Active Filters: Active filters use active elements such as OP-AMP along with resistors,
inductors and capacitors

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Order of Filter:
 Order of filter is an indication of number of R-C sections used in filter.
 First order filter uses one section of R and C
 Second order filter uses two sections of R and C
First-Order-Low-Pass Filter:
The above figure shows first order low-pass filter, and frequency response of low pass filter,it
uses single section of resistor and capacitor, Low-pass filter allows frequencies from 0Hz to
upper cut-off frequency FH, it rejects frequencies above fH, Bandwidth of Low-pass filter BW=fH
Operation:
At low frequencies, the reactance of capacitor (Xc) is much larger than the resistance
value, hence applied input signal appears at the output.
At High frequencies, the reactance of capacitor (Xc) becomes much smaller than
resistance, Hence applied input signal does not appear at the output.
Cut-Off Frequency of Low pass Filter:
The frequency at which reactance of capacitor is equal to resistance value, that frequency
is called as upper-cut off frequency, it is denoted by fH or fC, the gain at cut-off frequency is
equal to 0.707, fC = 1/2πRC
First –order Low-Pass Filter with gain :

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First-Order High-Pass Filter:
The above figure shows first-order High-pass filter, and frequency response of high pass
filter, it uses single section of resistor and capacitor, high pass filter allows only frequencies
above a lower cut-off frequency, (fL)and rejects the frequencies from 0Hz to fL. the frequency at
which gain is 0.707 is called as Lower cut –off frequency.
Operation:
At low frequencies, reactance of capacitor (Xc) is much larger than the resistance value
and therefore applied input signal does not appear at the output.
At high frequencies, the reactance of capacitor (Xc) is much smaller than the resistance
value, hence applied input signal appears at the output, the cut-off frequency of high pass filter is
given by fc=fL= 1/2πRC
First order High-pass filter with gain:

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Second-order Filters:
Second order filters have two sections of R and C
In the above figure if Z1=Z2=R and Z3=Z4=C we get second order low-pass filter
If Z1=Z2=C and Z3=Z4=R we get second order High –pass filter
Cut-off frequency is given as fc= 1/2πRC
Voltage-Gain Av = 1+R2/R1
Problem: Refer to comparator of circuit shown below, determine state of LED1 and LED2
(whether ON or OFF) when switch SW-1 is in (a) position –A and (b) position B, assume diodes
D1 and D2 to have forward biased voltage drop equal to 0.7v each.
Sol) when switch SW-1 is in position-A, voltage appearing at non-inverting input is 0.7V that is
voltage at non inverting terminal is more positive with respect to voltage at inverting input,
therefore op-amp output is +Vsat, hence LED-1 is ON and LED-2 is OFF
when switch SW-1 is in position-B, voltage appearing at non-inverting input is -0.7V that
is voltage at non inverting terminal is more negative with respect to voltage at inverting input,
therefore op-amp output is --Vsat, hence LED-1 is OFF and LED-2 is ON

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Problem:
Refer to relaxation oscillator circuit shown below, determine peak-peak to amplitude and
frequency of the square wave output given that saturation output voltage of op-amp is + 12.5v at
power supply voltage of + 15v.
Sol) Given values R1=47KΩ R2= 10KΩ R=10KΩ Vsat = 12.5v C=0.01µF
feedback factor B = R1/R1+R2 = (47KΩ) / (47KΩ + 10KΩ) = 0.825
Time-period T = 2RCln[(1+B)/(1-B)] = 2 10KΩ×0.01µF×ln[(1+0.825) / (1-0.825)] = 0.469ms
Frequency f = 1/T = 1/0.469ms = 2.13 KHz
Peak to peak amplitude of output = 2Vsat = 2×12.5v = 25v
Important Questions
1. Explain performance parameters of OP-AMP (JAN 2017) (8M)
2. Explain the working of any two applications of operational amplifier (JUL-17)(4 M)
3. Explain the working of Relaxation oscillator with neat diagram.
4. Explain inverting comparator with hysteresis.
5. With the help of neat diagram explain the operation of window comparator.
6. Explain the operation of non-linear amplifier.
7. Explain peak detector circuit
8. Explain operation of first order Low-pass filter