15CS44 MP & MC module 5

15CS44 Microprocessors & Microcontrollers
Kishore kumar R RLJIT Page 1
Module-5
Introduction to ARM Instruction Set
Topics:
5.1 Data Processing Instructions
5.2 Branch Instructions
5.3 Software Interrupt Instructions
5.4 Program Status Register Instructions
5.5 Coprocessor Instructions
5.6 Loading Constants

5.1 Data processing Instructions:
 Data processing instructions process the data in registers.
 Data processing instructions can process one operand using Barrel Shifter
 If suffix “S” is used in instruction, flags get updated.
The following are the data processing instructions
1. Move Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Comparison Instructions
5. Multiply Instructions
MOV instructions:
There are two Move instructions
1. MOV
2. MVN
MOV:
This instruction copies the value of “N” into destination register Rd
N  Register or Immediate Value
Syntax: MOV {<cond>} {S} Rd, N
Operation: Rd =N
E.g. MOV r3, r5 ; it copies r5 value to r3
MOV r2, #0x00000008 ; it copies immediate value 0x00000008 to r2, 0x indicates
hexadecimal value
MVN:
This instruction complements the “N” value and moves the complemented value into register
Syntax: MVN {<cond>} {S} Rd, N
Operation: Rd = ~N
E.g. PRE: r1= 0x11111111 r2=0x11110000
MVN r1,r2; r1= ~ r2
POST: r1=0x00001111 r2=0x11110000

Barrel Shifter:
 Barrel shifter can be used to shift one operand before it enters ALU
 Barrel shifter can perform four different operations
The below table shows barrel shifter operations
In the above figure barrel shifter shifts register Rm before it enters ALU.
Example: PRE: r5=5 r7 = 8
MOV r7, r5, LSL #1; r7= r5*2
POST: r5=5 r7=10
In the above example, r5 value is shifted left one position by barrel shifter and shifted value is
moved to r7
Arithmetic Instructions:
These instructions are used to perform addition and subtraction of 32-bit signed and unsigned
values.
Syntax: <instruction>{<cond>} {S} Rd, Rn, N
the following are the different arithmetic instructions
Instruction operation
ADC (add two 32-bit values and carry) Rd = Rn + N + carry
ADD (add two 32-bit values) Rd = Rn + N
RSB(Reverse subtract of two 32-bit numbers) Rd=N-Rn
RSC (reverse subtract with carry) Rd = N-Rn-!(CF)
SBC (Subtract with carry) Rd= Rn-N-!(CF)
SUB (subtract two 32-bit values) Rd=Rn-N

Example for Subtraction:
Example for subtraction:
In the below example, r2 value is subtracted form r1 and result is stored in r0.
PRE : r0 = 0x000000 r1 = 0x0000002 r2= 0x00000001
SUB r0, r1, r2
POST: r0 = ox00000001 r1= 0x00000002 r2= 0x00000001
E.g. in the below example SUBS instruction, subtracts immediate value 0x0000001 from
contents of r1 and the result ox00000000 is stored in register r1, since result is zero, zero flags
sets, capital letter Z indicates ZF=1
Example for RSB:
RSB subtracts r1 from constant value 0 and the result 0xffffff89 is stored in r0
Using Barrel shifter for with Arithmetic Instructions:
In the below example, r1 is first shifted one location to the left and shifted value (r1×2) is added
with r1 and the result 0x0000000f is stored in register r0

Logical Instructions:
These instructions perform bitwise logical operations on the two source registers.
Syntax: <instruction> {<cond>} {S} Rd, Rn, N
the following table shows different Logical instructions
Example for OR instruction:
OR instruction performs OR operation on r1 and r2 and stores result in r0
PRE: r0= 0x00000000 r1=0x02040608 r2=0x10305070
ORR r0, r1, r2
POST: r0= 0x12345678 r1=0x02040608 r2=0x10305070
Example for BIC instruction:
BIC instruction complements r2 value and performs AND operation between r1 and ~r2 and
stores the result in r0 ( r0 = r1 AND ~r2) here ~r2 is complemeted value of r2
PRE : r0= 0b0000 r1=0b1111 r2=0b0101
BIC r0, r1, r2
POST: r0=0b1010 r1=0b1111 r2=0b0101
Comparison Instructions:
Comapre instructions are used to compare or test a register with 32-bit value and update
the cpsr flag register accoring to result

Syntax: <instruction> {<cond>} Rn, N
Instruction operation
CMN (Compare Negated) Rn+N
CMP (compare) Rn-N
TEQ (Test for equality of two 32-bit values) Rn^N
TST (Test bits of a 32-bit value) Rn&N
Example for CMP instruction:
The value of r0 and r9 is 4, CMP performs R0-r9 =0, result is zero hence zero flag sets , capital
letter Z indicates ZF=1
Multiply Instructions:
These instructions multiply the contents of two registers and stores result in another
register.
Syntax: MLA {<cond>} {S} Rd, Rm, Rs, Rn
MUL {<cond>} {s} Rd, Rm, Rs
Instruction Operation
MLA (Multiply & Accumulate) Rd= (Rm×Rs) + Rn
MUL (Multiply) Rd=Rm×Rs
Example: MUL multiplies register r1 and r2 and places result in r0
PRE: r0 = 0x00000000 r1 = 0x00000002 r2 = 0x00000002
MUL r0, r1, r2 ; r0 = r1×r2
POST: r0 = 0x00000004 r1 = 0x00000002 r2 = 0x00000002

Long Multiply Instructions:
 These instructions produce 64-bit result
 64-bit result is stored in two registers RdLo ad RdHi, RdLo holds lower 32-bits result,
RDHi holds higher 32-bit result.
Syntax: <instruction> {<cond>} {S} RdLo, RdHi, Rm, Rs
The following are different Long Multiply Instructions
SMLAL (signed multiply accumulate long) [RdHi,RdLo] = [RdHi, RdLo] + (Rm×Rs)
SMULL (signed multiply long) [RdHi, RdLo] = Rm×Rs
UMLAL (unsigned multiply accumulate long) [RdHi, RdLo] = [RdHi, RdLo] + (Rm×Rs)
UMULL (unsigned multiply long) [RdHi, RdLo] = Rm×Rs
Example: UMULL multiplies r2 and r3 and places result into register r0and r1, r0 contains lower
32-bits result and r1 contains higher 32-bits result
PRE: r0=0x00000000 r1=0x00000000 r2=0xf00000002 r3=0x00000002
UMULL r0, r1, r2, r3; r2×r3 = 0xf0000002 × 0x00000002 = 0x1e0000004
POST: r1=0x00000001 r0=0xe0000004
5.2 Branch Instructions:
 Branch instructions change the flow of execution, or are used to call a routine.
 PC (program counter) points to new value when flow of execution changes.

Example: B forward branches to label forward
B forward
ADD r1,r2,#4
ADD R0,R6,#2
ADD R3, R7, #4
Forward
Sub r1,r2,#4
Example: B backward branches to label backward.
backward
ADD r1,r2,#4
SUB r1, r2, #4
ADD r4, r6, r7
B backward
Example for Brach with Link (BL):
BL is similar to B instruction but BL moves return address (address of next instruction) to Link
register (lr), in this example BL calls subroutine.
BL subroutine ; branch to subroutine
CMP r1,#5
MOVEQ r1, #0
.
.
.
Subroutine
<subroutine code>
MOV Pc, lr ; return by moving PC= lr
Load-Store Instructions:
Load-Store instructions transfer data between memory and processor registers, there are
three types of Load-Store instructions
1. Single- register Transfer
2. Multiple-register Transfer
3. Swap
Single-register transfer instructions:
These instructions are used to transfer data between single register and memory location.
Syntax: <LDR> {<cond>} {B} Rd, addressing1
<STR> {<cond>} {B} Rd, addressing1

The following table shows different single register transfer instructions
LDR (Load word into a register from memory) Rd mem32[address]
STR (store word in memory from a register) Rd mem32{address]
LDRB (Load byte into register from memory) Rd mem8[address]
STRB (store byte in memory from a register) Rdmem8[address]
Example:
LDR r0, [r1] ;this instruction loads 32-bit data to r0 from memory location pointed by r1
LDRB r0,[r1] ; it loads 8-bit data to r0 from memory location pointed by r1
STR r0, [r1] ; it stores 32-bit data of r0 in memory location pointed by r1
Single – Register Load- Store Addressing Modes:
 Load-Store instructions use different modes for addressing memory.
 Addressing modes use three different indexing methods
1. Pre-index with write-back
2. Pre-index
3. Post-index
Pre-index with write back:
This method calculates memory address by adding base register and offset, and data
from that address is transferred to register Rd, and updates the base register with new address.
Rd mem [base register + offset] and base register= base register +offset
Example: In this instruction r0 is Rd and r1 is base register #4 is offset, it moves the data from
memory location pointed by r1+4 to register r0 and r1 is updated with r1+4
PRE: r0=0x00000000
r1=0x00090000
mem32[0x00090000]=0x01010101
mem32[0x00090004]=0x02020202
LDR r0,[r1, #4]! ; r0 mem32[r1+4] r1=r1+4
POST: r0=0x02020202
r1=0x00090004
Pre-index method:
This method calculates memory address by adding base register and offset, and
data from that address is transferred to register Rd, base register does not get updated

Example:
PRE: r0=0x00000000
r1=0x00090000
mem32[0x00090000]=0x01010101
mem32[0x00090004]=0x02020202
LDR r0,[r1, #4]! ; r0 mem32 [r1+4] r1 does not update
POST: r0=0x02020202
r1=0x00090000
Post-Index Method:
This method first transfer data from memory location pointed by base register to Rd then
base register is updated.
Rd mem [base register] and base register= base register +offset
Example:
PRE: r0=0x00000000
r1=0x00090000
mem32[0x00090000]=0x01010101
mem32[0x00090004]=0x02020202
LDR r0,[r1, #4]! ; r0 mem32[r1] r1=r1+4
POST: r0=0x01010101
r1=0x00090004
Summary of indexing methods:

Single-register Load-store addressing1
modes
Single register Load-Store addressing Half-word, signed Half-word, Signed Byte:
These instructions are used store and load Half-words (signed & unsigned) and bytes
(signed & unsigned)
Syntax: LDR {<cond>} SB Rd, addressing2
LDR {<cond>} H Rd, addressing2
LDR {<cond>} SH Rd, addressing2
STR {<cond>} H Rd, addressing2
Addressing2
Modes:
LDRH (load halfword into register from memory location) Rd mem16[address]
STRH (store half word in memory from register) Rd mem16[address]
LDRSB (load signed byte into register from memory) Rd  sign extend (mem8 [address])
LDRSH (load signed halfword into a register from memory) Rd sign extend (mem16[address])

Types of STRH instructions:
Multiple-Register Transfer Instructions:
These instructions are used to transfer data between multiple registers and memory,
Syntax:<LDM> {<cond>} <addressing mode> Rn{!}, <registers>{^}
<STM> {<cond>} <addressing mode> Rn{!}, <registers>{^}
The following table shows the addressing modes of Load-Store multiple instructions
Example 1:
Before the execution of instruction LDMIA r0!, {r1-r3}the contents of registers and
memory locations are
PRE condition:

LDMIA r0!,{r1-r3} loads the data from memory location 0x80010 to r1 and from location
0x80014 to r2 and from 0x80018 to r3 after every data transfer r0 values gets incremented by 4.
POST condition:
Example 2.
Before the execution of instruction LDMIB r0!, {r1-r3}the contents of registers and
memory
locations are
PRE condition:
LDMIA r0!,{r1-r3} loads the data from memory location 0x80014 to r1 and from location
0x80018 to r2 and from 0x8001c to r3, before every data transfer r0 values gets incremented by
4.
POST condition:

Load –Store multiple pairs:
Store Multiple Load Multiple
STMIA LDMDB
STMIB LDMDA
STMDA LDMIB
STMDB LDMIA
The table shows Load-store multiple pairs, if store instruction stores multiple registers in
memory, then paired Load instruction can be used to reload the data to registers.
Example: STMIB stores the contents of registers r1-r3 in memory, by using LDMDA registers
r1-r3 contents can be reloaded back from memory.
Before STMIB execution
r0 = 0x00009000 r1 = 0x00000009 r2= 0x00000008 r3=0x00000007
STMIB r0!, {r1-r3}
MOV r1, #1
MOV r2, #2
MOV r3, #3
After STMIB execution and before LDMDA execution
r0 =0x0000900C r1=0x00000001 r2= 0x00000002 r3=0x00000003
LDMDA r0!, {r1-r3}
After LDMDA execution:
r0 =0x00009000 r1=0x00000009 r2= 0x00000008 r3=0x00000007
LDMDA instruction reloaded the old values of registers r1 to r3
Stack operations:
 ARM uses Load, Store instructions for stack operations
 Load multiple instruction is used to remove data from stack
 Store multiple instructions are used to place data in stack.
 Stack is either Ascending (A) or descending (D) , Ascending stack grows up, Descending
stack grows down.
 When we uses full stack (F), the stack pointer SP points to last item on the stack.
 When we use empty stack (E), SP points the location (empty location) after the last item.

Addressing Modes for Stack operations:
Addressing Mode Description POP PUSH
FA Full Ascending LDMFA STMFA
FD Full descending LDMFD STMFD
EA Empty ascending LDMEA STMEA
ED Empty descending LDMED STMED
Example:
STMFD pushes registers r1 and r4 onto stack, after pushing both registers SP points to last item.
PRE: r1=0x00000002 r2=0x00000003 SP=0x00080014
STMFD SP!, {r1,r4}
Example:
STMED STMFD pushes registers r1 and r4 onto stack, after every push SP gets updated, after
pushing both registers SP points to location(empty location) after last item.

SWAP Instruction:
This instruction swaps the contents of memory with contents of a register.
Syntax: SWP {B} {<cond>} Rd, Rm, [Rn]
Example: SWAP instruction loads a word from memory into register r0 and stores r1 value in
memory location
`
5.3 Software Interrupt Instruction:
SWI instruction is used to cause an interrupt and call operating system routine.
Syntax: SWI {<cond>} SWI_number
SWI Software interrupt LR= address of instruction following SWI
SPSR = CPSR
PC=vectors+08
CPSR mode = SVC
CPSR I=1 (mask IRQ interrupts)
when processor executes an SWI instruction, it sets program counter PC to OFFSET
0x08 vector table, and changes processor mode to supervisor mode, SWI_number is used to call
particular OS routine.
Example:
SWI calls OS routine with SWI number 0x123456
PRE: CPSR = nzcVqift_USER
PC=0x00008000
lr=0x003fffff

0x00008000 SWI 0x123456
POST: CPSR=nzcVqIft_SVC
SPSR=nzVqift_USER
PC=0x00000008
lr=0x00008004
5.4Program Status register Instructions:
ARM has two instructions to control program status register (PSR)
1. MRS
2. MSR
MRS: This instruction transfers contents of either CPSR or SPSR into a register
MSR: This instruction transfers contents of register to CPSR or SPSR.
Syntax: MRS {<cond>} Rd, <CPSR | SPSR>
MSR {<cond>} <CPSR|SPSR>_<fields>, Rm
MSR {<cond>} <CPSR|SPSR>_<fields>, #immediate
MRS Copy CPSR to general purpose register Rd=CPSR
MSR Copy general purpose register to CPSR CPSR [field] =Rm
MSR Move an immediate value to CPSR CPSR[field] = immediate
Example: MSR first copies CPSR into r1, BIC instruction clears bit 7 of r1, register r1 is then
copied back into CPSR which enables IRQ bits
PRE: CPSR = nzcvqIFT_SVC
MRS r1, cpsr
BIC r1, r1, #0x80
MSR CPSR_C, r1
POST: CPSR = nzcvqiFt_SVC
5.5Coprocessor Instructions:
 These instructions are used for coprocessors
 Coprocessor instructions include data processing instructions, register transfer, memory
transfer instructions.

In syntax. CP represents coprocessor number between p0 to p15, Cn, Cm, Cd are registers of
coprocessor
E.g. MRC p15, 0, r10, C0, C0, 0
5.6Loading Constants:
ARM provides two pseudo instructions to move 32-bit value into a register.
Syntax: LDR Rd, =constant
ADR Rd, label
LDR loads 32-bit constant to register, ADR instruction writes a relative address into a register
LDR Load constant pseudo-instruction Rd=32-bit constant
ADR Load address pseudo-instruction Rd=32-bit relative address
Example:
LDR loads 32-bit constant 0Xff00ffff into register r0
LDR r0, [PC ,#constant_number -8-{PC}]
.
.
.
Const_number
DCD 0xff00ffff

Important Questions
1. With an example, explain the following instructions with an example
i) MOVN ii) LDMB
2. Explain the following instructions
i) ADC ii) ADD iii) RSB iv) RSC v) SBC vi) SUB
3. Explain multiple-register transfer instructions
4. Explain how stack operations can be carried out using Load-Store multiple instructions
5. Explain following instructions i) AND ii) ORR iii) EOR iv) BIC
6. Explain SWAP instruction with an example.
7. Explain following comparison instructions with an example.
i) CMN ii) CMP iii) TEQ iv) TST
8. Explain MUL and UMULL instructions with an example
9. Explain software interrupt instruction with an example.
10. Explain MSR and MRS instructions with an example
11. Explain LDMIA instruction with an example.
12. Explain pre-index with write-back and post index with an example.
13. Explain barrel shifter with suitable example.

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