Metal Oxide Semiconductor Field Effect Transistors

1. MOSFET
Metal Oxide Semiconductor Field Effect Transistors

2. September 17, 2007 2
Typically L = 1 to 10 µm, W = 2 to 500 µm, and the thickness of the oxide
layer is in the range of 0.02 to 0.1 µm.
Field Effect (MOS) Transistor

3. Different types of FETs
 Metal-Semiconductor FET (MESFET)

4. Basic MOSFET (n-channel)
 The gate electrode is
placed on top of a very
thin insulating layer.
 There are a pair of small
n-type regions just under
the drain & source
electrodes.
 If apply a +ve voltage to
gate, will push away the
‘holes’ inside the p-type
substrate and attracts the
moveable electrons in the
n-type regions under the
source & drain
electrodes.

5. Basic MOSFET (n-channel)
 Increasing the +ve gate
voltage pushes the p-
type holes further away
and enlarges the
thickness of the created
channel.
 As a result increases the
amount of current which
can go from source to
drain — this is why this
kind of transistor is
called an enhancement
mode device.

6.  Cross-section and circuit symbol of an n-type
MOSFET.

7. September 17, 2007 7
The enhancement-type NMOS transistor with a
positive voltage applied to the gate.
An n channel is
induced at the top
of the substrate
beneath the gate.
Operation

8. September 17, 2007 8
vGS
> Vt ,
small vDS
applied.
the channel
conductance
is proportional
to vGS
- Vt
,
and is
proportional
to (vGS
- Vt)
vDS
.
Triode Region

9. September 17, 2007 9
The induced
channel acquires
a tapered shape
and its
resistance
increases as vDS
is increased.
vGS
> Vt
.
Saturation Region

10. September 17, 2007 10
Derivation of the iD
- vDS
characteristic of the
NMOS transistor.

11. September 17, 2007 11
Increasing vDS
beyond vDSsat
causes the channel
pinch-off point to move slightly away from the
drain, thus reducing the effective channel length
(by ∆L).

12. September 17, 2007 12
Enhancement-type NMOS transistor operated with vGS
> Vt
.
Drain current iD
versus vDS

13. I-V Characteristics of MOSFET

14. ECE 663
Drain current for REALLY small VD
( )
( )[ ]
( )TGD
DTGinD
DDTGinD
VVV
VVVC
L
Z
I
VVVVC
L
Z
I
−<<
−≈




−−=
µ
µ
2
2
1
Linear operation
Channel Conductance:
)( TGin
VD
D
D VVC
L
Z
V
I
g
G
−µ=
∂
∂
≡
Transconductance:
Din
VG
D
m VC
L
Z
V
I
g
D
µ=
∂
∂
≡

15. ECE 663
In Saturation
 Channel Conductance:
 Transconductance:
( )2
2
TGinD VVC
L
Z
satI −µ=
0=
∂
∂
≡
GVD
D
D
V
I
g
( )TGin
VG
D
m VVC
L
Z
V
I
g
D
−µ=
∂
∂
≡

16. MOSFET Output Curves
 A family of curves
representing the V-I
characteristics of
transistors.
 A plot of drain
current, ID, as a
function of drain-to-
source voltage, VDS,
for several values of
VGS.

17. September 17, 2007 17
iD
- vGS
characteristic for an enhancement-type NMOS transistor
in saturation (Vt
= 1 V and k’n
(W/L) = 0.5 mA/V2
).

18. September 17, 2007 18
The MOSFET parameter VA
is typically in the range of 30 to 200 V.
Effect of vDS
on iD
in the saturation region.

19. Ideal Output Characteristics of MOSFET

20. Ideal Transfer Characteristics of MOSFET

21. Voltage-Dependent Resistor
 In the ON state, the MOSFET channel can be viewed as a
resistor.
 Since the mobile charge density within the channel
depends on the gate voltage, the channel resistance is
voltage-dependent.

22. Comparison: BJT vs. MOSFET
 In a BJT, current (IC) is limited by diffusion of carriers from
the emitter to the collector.
 IC increases exponentially with input voltage (VBE), because the
carrier concentration gradient in the base is proportional to
 In a MOSFET, current (ID) is limited by drift of carriers from
the source to the drain.
 ID increases ~linearly with input voltage (VG), because the
carrier concentration in the channel is proportional to (VG-VTH)
In order to understand how MOSFET design parameters affect
MOSFET performance, we first need to understand how a MOS
capacitor works...
TBE VV
e /

23. Types of MOSFET

24. Subthreshold Conduction

25. CMOS Circuit

26. September 17, 2007 26
Cross section of a CMOS integrated circuit. Note that
the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is
also possible in which an n-type body is used and the n
device is formed in a p well.

27. Fabrication and Layout Slide 27
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF

28. Fabrication and Layout Slide 28
CMOS Inverter
A Y
0
1
VDD
A Y
GND
A Y

29. Fabrication and Layout Slide 29
CMOS Inverter
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y

30. Fabrication and Layout Slide 30
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y