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Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-1
Introduction to CMOS RF Integrated Circuits Design
VII. Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-2
Outline
Outline
•Functionality
•Figures of Merit
•PA Design
Classical Design (Class A, B, C)
High-Efficiency Design (Class E, F)
•Matching Network
•Linearity
•T/R Switches
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-3
PAs
PAs and
and TRs
TRs Switching in Transceiver
Switching in Transceiver
Rx
Z
Z
Z
BPF
T/R
Switch
Matching
Networks
PA Tx
Rx
Z
Z
Z
BPF
T/R
Switch
Matching
Networks
PA Tx
Z
Z
Z
BPF
T/R
Switch
Matching
Networks
PA Tx
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-4
Functionality of
Functionality of PAs
PAs
•To Amplify and Deliver Required Signal Power to
Antenna at Frequency of Interest
•To Achieve Desired Output Power with Maximum Power
Efficiency
•To Provide Output Impedance Matching to Antenna
•To Have Clean Spectrum Not to Affect Receivers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-5
Figures of Merit of
Figures of Merit of PAs
PAs
•Frequency
•Output Power
•Power Efficiency
•Linearity (P-1dB, IIP3, ACPR)
•Conversion Gain
•Spur
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-6
L
p
p
o
L
amp
o
L
rms
o
o
R
v
R
v
R
v
P
8
2
2
,
2
,
2
, 



Output Power
Output Power
•For a Load of 50 Ohm, Need an Output Amplitude of 10 V to Achieve
an Output Power of 1W!
•For a Low Supply, Need Small Load for Large Output Power, i.e. A
3.3-V Output Amplitude Can Only Deliver 1W to a Load of 5 Ohm!
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-7
PA IMN
5  50 
•Need an Output Impedance Matching to Convert 50 Ώ to
a Smaller Load!
•As Supply and Load Decrease, PA Would Need to
Deliver Much Larger Current
•Loss Due to Parasitic (R, L) Becomes Significant =>
Low Efficiency!
Output Power
Output Power
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-8
DC
in
o
DC
o
in
o
P
P
P
P
PAE
P
P
P
P
A





•With a High Power Gain AP, Drain Efficiency η is Approximately
the Same as Power-Added Efficiency PAE
Power Gain and Efficiency
Power Gain and Efficiency
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-9
Linearity
Linearity
•1-dB Compression Point
•Intermodulation Intercept Point IIP3
•Conventional Definition and Measurement Not
Sufficient Because Most PAs Operate Near 1-dB
Compression Point for Maximum Efficiency => Higher-
Order Distortion Becomes Significant and Needs to Be
Included => Adjacent-Channel Power Rejection ACPR
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-10
Output Spectrum

ACPR
Adjacent
Adjacent-
-Channel Power Rejection (ACPR)
Channel Power Rejection (ACPR)
•A Modulated Signal is Applied to Include High-Order
Distortion
•ACPR is Defined and Measured as the Power of the
Adjacent Channel Relative to the Carrier
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-11
Output Power ~ 0 – 35 dBm
Efficiency ~ 30 – 60 %
Gain > 20 dB
Linearity, IMD - 30 dBc
Linearity, ACPR - 25 dBc
Spurs < - 50 dBc
Supply Voltage ~ 1.8 V
Current > 300 mA
Typical Figures of Merit
Typical Figures of Merit
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-12
Linear Power Amplifiers
Linear Power Amplifiers
•Linear Relationship between Input and Output Signals
•Critical for Applications with Non-Constant Envelope Modulation
Scheme
•Classical Linear PAs Include Class-A, Class-B, and Class C
•Classification is Made Based on Conduction Angle, Defined as the
Fraction of Period when Active Device is On
Original Signal
Spectrum
Spectrum at output of
nonlinear PA
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-13
Non
Non-
-Linear Power Amplifiers
Linear Power Amplifiers
Constant envelop
modulation
Nonconstant envelop
modulation
GMSK
FSK
BPSK
QPSK
QAM
Nonlinear PA
High Efficiency
Linear PA
Low Efficiency
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-14
)
2
/
cos(
)
2
/
(
)
2
/
sin(
sin
4
1
)
2
/
cos(
1
sin
















DC
o
o
P
P
P
0
180
360

100%
78%
50%

C
B
A
Class
Conduction Angle
Conduction Angle
REF: H. Kraus, et al, Solid State Radio Engineering, Wiley, 1980
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-15
Conduction Angle
Conduction Angle
REF: H. Kraus, et al, Solid State Radio Engineering, Wiley, 1980
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-16
Class
Class-
-A Power Amplifiers
A Power Amplifiers
DD
V
 
θ
IN
v
 
θ
OUT
v
 
θ
D
v
RFC
 
θ
OUT
i
 
θ
D
i
DD
V
 
θ
D
v
RFC
 
θ
D
i
 
θ
OUT
v
 
θ
OUT
i
 
θ
IN
v
TH
V
 
θ
D
v
DD
V
θ
θ
 
θ
OUT
v
0 θ
 
θ
D
i
θ
0 θ
 
θ
OUT
i
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-17
Class
Class-
-A Power Amplifiers
A Power Amplifiers
•Single Transistor as Amplifier to Minimize Loss and Maximize
Efficiency
•Transistor Always Conducts => Conduction Angle is 360 Degrees
•Highest Linearity
•Lowest Efficiency
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-18
Class
Class-
-A Power Amplifiers
A Power Amplifiers
•RF Choke LC Provides Constant Bias Current Source
While Doubling Output Voltage and Efficiency (as
Compared to Resistive Load)
•Capacitor Cb Blocks DC Current from Flowing to the
Output => No DC Power Consumption for the Load
•Resonant Tank Filters Harmonics Due to Non-
Linearity to Obtain Single Tone at Output
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-19
Class
Class-
-A Power Amplifiers
A Power Amplifiers
•For Resistive Load, Maximum Output Voltage is Limited
to VDD
•For Inductive Load, Maximum Output Voltage is Increased
to 2VDD
For Same Loading and Same Supply, Output Power is Increased
By 4 Times and Efficiency is Increased By 2 Times
For Same Loading and Same Output Power, Supply Can Be
Reduced By 2 Times
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-20
%
25
4
2
max
,
max
,
max
,
max
,
max
,






DC
o
B
DD
ave
D
DD
DC
B
DD
o
o
o
P
P
I
V
I
V
P
I
V
I
V
P

id
IB
t
vo
VDD/2
t
Po
PDC
t
Class
Class-
-A PA with Resistive Load
A PA with Resistive Load
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-21
%
50
2
2
max
,
max
,
max
,
max
,
max
,






DC
o
B
DD
ave
D
DD
DC
B
DD
o
o
o
P
P
I
V
I
V
P
I
V
I
V
P

id
IB
t
vo
VDD
t
Po
PDC
t
Class
Class-
-A PA with Inductive Load
A PA with Inductive Load
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-22
DD
V
 
θ
IN
v
 
θ
OUT
v
 
θ
D
v
 
θ
OUT
i
 
θ
1
D
i
 
θ
IN
v
T
V
θ
0 θ
 
θ
1
D
i
 
θ
2
D
i
0 θ
 
θ
2
D
i
 
θ
OUT
v
0 0 θ
 
θ
OUT
i
R
V
R
V
P DD
om
RFout
2
2
2
2


R
V
π
π
I
θ
d
θ
I
π
I om
D
π
D
DC
2
2
sin
2
1 2
0


 
785
.
0
4
4
2
2
2





π
π
DD
om
DD
om
om
DC
RFout
Drain
V
V
π
V
R
V
R
V
P
P
η
Class
Class-
-B Power Amplifiers
B Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-23
•Two Transistors as Push-Pull Amplifier
•Transistors Conduct Only HALF CYCLE => Conduction Angle is 180
Degrees
•Higher Efficiency Compared to Class-A
•Compromised Linearity
•Due to Speed Limitation of PMOS, Two NMOS Can Be Used In
Parallel with Their Currents Combined By a Transformer
Class
Class-
-B Power Amplifiers
B Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-24
%
78
4
4
2
max
,
max
,
,
max
,
max
,
max
,
2
2












DC
o
DD
ave
D
DD
DC
DD
ave
D
L
DD
o
o
o
P
P
R
V
I
V
P
R
V
I
R
V
I
V
P
L
L
Class
Class-
-B Power Amplifier
B Power Amplifier
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-25
DD
V
 
θ
IN
v
 
θ
OUT
v
 
θ
D
v
RFC
 
θ
OUT
i
 
θ
D
i
 
θ
IN
v
TH
V
θ
 
θ
D
i
θ
0 θ
 
θ
OUT
i
 
θ
OUT
v
0
 
2
cos
1
sin






RFout
P
   
2
2
2 cos
sin
sin
4
1


 





DC
RFout
Drain
P
P
η

Class
Class-
-C Power Amplifiers
C Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-26
Class
Class-
-C Power Amplifiers
C Power Amplifiers
•Transistor Conducts Much Less Than Half of
Cycle => Conduction Angle is Close to Zero
Degree
•Higher Efficiency Compared to Class-A and
Class-B
•Much Degraded Linearity
•Lower Output Power
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-27
Non
Non-
-Linear Power Amplifiers
Linear Power Amplifiers
•Operate Active Devices as Switches Instead of Amplifying
Linear Devices
•Highly Non-Linear
•Highest Efficiency (~ 100%)
•Most Suitable for Applications with Constant-Envelope
Modulation
•For Linear Applications, Need Linearization Techniques
•Includes Class-E, Class-F
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-28
Non
Non-
-Linear Power Amplifiers
Linear Power Amplifiers
•In Practice, Efficiency is Limited to ~ 60% Due to:
•High Speed => Not Too Large Device Size => Finite
Turn-On Resistance of the Switch
•Finite Turn-On Transition Times
•Low-Q Inductors => Off-Chip Inductors or Bond
Wires
•For High Output Power, Device Stress is Critical
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-29
 Switch mode
 Approaching 100%
efficiency
DD
V
 
θ
IN
v
 
θ
D
v
 
θ
D
i
 
θ
OUT
v
 
θ
OUT
i
1
C
1
L
DD
V
 
θ
OUT
v
1
C
1
L
 
θ
D
v
 
θ
OUT
i
 
θ
IN
v
θ
 
θ
D
v
θ
 
θ
D
i
θ
 
θ
OUT
v
0
Class
Class-
-E Power Amplifiers
E Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-30
•Operate Active Device as Switch To Minimize Power
Loss and Maximize Efficiency (~ 100%) :
•Small Transition Times Between ON and OFF
•Small Voltage when Conducting Current
•Small Current when Sustaining Large Voltage
•Change of Voltage with Time is Close to Zero when
Starting Conducting
•Parasitic Capacitance of Device Can Be Conveniently
Absorbed in Cd
Class
Class-
-E Power Amplifiers
E Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-31
 
 
o
DD
opt
DD
o
d
DD
r
P
V
R
V
P
C
V
L
2
2
2
2
2
58
.
0
4
2
4










.
OFF ON OFF ON OFF
vin
id
vds
t
t
t
Class
Class-
-E Power Amplifiers
E Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-32
 L3C3 tuned to the 2nd or 3rd
harmonics
 Peak efficiency
 88% for 3rd harmonics peaking
 85% for for 2nd harmonics
peaking.
DD
V
 
θ
IN
v
 
θ
OUT
v
 
θ
D
v
RFC
 
θ
OUT
i
 
θ
D
i
3
L
3
C
 
θ
IN
v
TH
V
θ
 
θ
D
v
DD
V
θ
 
θ
D
i
θ

 
θ
OUT
v
0
1
L 1
C
Class
Class-
-F Power Amplifiers
F Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-33
•Employ Harmonics to Simulate a Square Waveform to Minimize
Transition Times and thus to Reduce Loss
•A Parallel Tank Lr3Cr3 is Included to Obtain a Third-Order
Harmonic and to Add to the Fundamental to Approximate a Square
Wave
Class
Class-
-F Power Amplifiers
F Power Amplifiers
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-34
Challenges for CMOS
Challenges for CMOS PAs
PAs
•Trade-Off Among All Parameters
•Speed
•Device Size
•Current and Output Power
•Supply Voltage
•Loss and Efficiency
•Device Stress
•Low-Q On-Chip Inductors => Off-Chip Inductors or Bond Wires
for Inductors in Resonant Tanks and Matching Network
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-35
Linearization Techniques
Linearization Techniques
•Critical for Both High Efficiency and High Linearity
•Use Non-Linear Power Amplifiers (Class E and/or F) for High
Efficiency
•Use Linearization Techniques to Improve Linearity:
•Feed-Forward
•Envelope Elimination and Restoration
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-36
AP
AP
1/AP
vin vo
vy
vx
-
+
-
+
Feed
Feed-
-Forward Techniques
Forward Techniques
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-37
in
y
x
o
in
y
in
x
y
x
o
v
A
v
A
v
v
A
v
v
A
v
v
A
v
v
v
A
v
v
A
v
v
v
v
v
v
in
v
v
v















Feed
Feed-
-Forward Techniques
Forward Techniques
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-38
Feed
Feed-
-Forward Techniques
Forward Techniques
•Open Loop Without Feedback => Unconditional Stability
•Limited Linearity Improvement Due to:
Gain Mismatches
Phase Mismatches
Errors of Subtractors
•Can Be Extended to Nested Feed-Forward Loops to
Improve Linearity at A Cost of More Complexity
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-39
Av1
PA
vin
vo
vy
vx
Envelope Detector
Limiter
VDD
Envelope Elimination and Restoration (EER)
Envelope Elimination and Restoration (EER)
Techniques
Techniques
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-40
Envelope Elimination and Restoration (EER)
Envelope Elimination and Restoration (EER)
Techniques
Techniques
•Decompose Input Signal into An Envelope and a Phase-
Modulated Signal, both of which are Amplified
Separately and Recombined
•Constant-Envelope High-Frequency Phase-Modulated
Component is Generated by “Eliminating” from Input’s
Envelope Using a Limiter and then Applied as Input to a
High-Efficiency Switching PA
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-41
Envelope Elimination and Restoration (EER)
Envelope Elimination and Restoration (EER)
Techniques
Techniques
•Non-Constant Low-Frequency Envelope Can Be Extracted
by an Envelope Detector, Amplified by a Switching Supply
Voltage, and then “Recombined” with RF Phase-
Modulated Component By Modulating the PA’s Supply
Voltage
•Achieve Linearization without Sacrificing Efficiency
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou VII-42
Envelope Elimination and Restoration (EER)
Envelope Elimination and Restoration (EER)
Techniques
Techniques
•Operating Frequencies of the Two Paths are Quite
Different
•Suffer from Phase and Gain Mismatches => Limited
Linearity Improvement
•Power Consumption Can Be High => Power
Efficiency Can Be Degraded

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Lecture-7-PA.pdf

  • 1. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-1 Introduction to CMOS RF Integrated Circuits Design VII. Power Amplifiers
  • 2. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-2 Outline Outline •Functionality •Figures of Merit •PA Design Classical Design (Class A, B, C) High-Efficiency Design (Class E, F) •Matching Network •Linearity •T/R Switches
  • 3. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-3 PAs PAs and and TRs TRs Switching in Transceiver Switching in Transceiver Rx Z Z Z BPF T/R Switch Matching Networks PA Tx Rx Z Z Z BPF T/R Switch Matching Networks PA Tx Z Z Z BPF T/R Switch Matching Networks PA Tx
  • 4. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-4 Functionality of Functionality of PAs PAs •To Amplify and Deliver Required Signal Power to Antenna at Frequency of Interest •To Achieve Desired Output Power with Maximum Power Efficiency •To Provide Output Impedance Matching to Antenna •To Have Clean Spectrum Not to Affect Receivers
  • 5. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-5 Figures of Merit of Figures of Merit of PAs PAs •Frequency •Output Power •Power Efficiency •Linearity (P-1dB, IIP3, ACPR) •Conversion Gain •Spur
  • 6. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-6 L p p o L amp o L rms o o R v R v R v P 8 2 2 , 2 , 2 ,     Output Power Output Power •For a Load of 50 Ohm, Need an Output Amplitude of 10 V to Achieve an Output Power of 1W! •For a Low Supply, Need Small Load for Large Output Power, i.e. A 3.3-V Output Amplitude Can Only Deliver 1W to a Load of 5 Ohm!
  • 7. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-7 PA IMN 5  50  •Need an Output Impedance Matching to Convert 50 Ώ to a Smaller Load! •As Supply and Load Decrease, PA Would Need to Deliver Much Larger Current •Loss Due to Parasitic (R, L) Becomes Significant => Low Efficiency! Output Power Output Power
  • 8. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-8 DC in o DC o in o P P P P PAE P P P P A      •With a High Power Gain AP, Drain Efficiency η is Approximately the Same as Power-Added Efficiency PAE Power Gain and Efficiency Power Gain and Efficiency
  • 9. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-9 Linearity Linearity •1-dB Compression Point •Intermodulation Intercept Point IIP3 •Conventional Definition and Measurement Not Sufficient Because Most PAs Operate Near 1-dB Compression Point for Maximum Efficiency => Higher- Order Distortion Becomes Significant and Needs to Be Included => Adjacent-Channel Power Rejection ACPR
  • 10. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-10 Output Spectrum  ACPR Adjacent Adjacent- -Channel Power Rejection (ACPR) Channel Power Rejection (ACPR) •A Modulated Signal is Applied to Include High-Order Distortion •ACPR is Defined and Measured as the Power of the Adjacent Channel Relative to the Carrier
  • 11. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-11 Output Power ~ 0 – 35 dBm Efficiency ~ 30 – 60 % Gain > 20 dB Linearity, IMD - 30 dBc Linearity, ACPR - 25 dBc Spurs < - 50 dBc Supply Voltage ~ 1.8 V Current > 300 mA Typical Figures of Merit Typical Figures of Merit
  • 12. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-12 Linear Power Amplifiers Linear Power Amplifiers •Linear Relationship between Input and Output Signals •Critical for Applications with Non-Constant Envelope Modulation Scheme •Classical Linear PAs Include Class-A, Class-B, and Class C •Classification is Made Based on Conduction Angle, Defined as the Fraction of Period when Active Device is On Original Signal Spectrum Spectrum at output of nonlinear PA
  • 13. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-13 Non Non- -Linear Power Amplifiers Linear Power Amplifiers Constant envelop modulation Nonconstant envelop modulation GMSK FSK BPSK QPSK QAM Nonlinear PA High Efficiency Linear PA Low Efficiency
  • 14. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-14 ) 2 / cos( ) 2 / ( ) 2 / sin( sin 4 1 ) 2 / cos( 1 sin                 DC o o P P P 0 180 360  100% 78% 50%  C B A Class Conduction Angle Conduction Angle REF: H. Kraus, et al, Solid State Radio Engineering, Wiley, 1980
  • 15. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-15 Conduction Angle Conduction Angle REF: H. Kraus, et al, Solid State Radio Engineering, Wiley, 1980
  • 16. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-16 Class Class- -A Power Amplifiers A Power Amplifiers DD V   θ IN v   θ OUT v   θ D v RFC   θ OUT i   θ D i DD V   θ D v RFC   θ D i   θ OUT v   θ OUT i   θ IN v TH V   θ D v DD V θ θ   θ OUT v 0 θ   θ D i θ 0 θ   θ OUT i
  • 17. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-17 Class Class- -A Power Amplifiers A Power Amplifiers •Single Transistor as Amplifier to Minimize Loss and Maximize Efficiency •Transistor Always Conducts => Conduction Angle is 360 Degrees •Highest Linearity •Lowest Efficiency
  • 18. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-18 Class Class- -A Power Amplifiers A Power Amplifiers •RF Choke LC Provides Constant Bias Current Source While Doubling Output Voltage and Efficiency (as Compared to Resistive Load) •Capacitor Cb Blocks DC Current from Flowing to the Output => No DC Power Consumption for the Load •Resonant Tank Filters Harmonics Due to Non- Linearity to Obtain Single Tone at Output
  • 19. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-19 Class Class- -A Power Amplifiers A Power Amplifiers •For Resistive Load, Maximum Output Voltage is Limited to VDD •For Inductive Load, Maximum Output Voltage is Increased to 2VDD For Same Loading and Same Supply, Output Power is Increased By 4 Times and Efficiency is Increased By 2 Times For Same Loading and Same Output Power, Supply Can Be Reduced By 2 Times
  • 20. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-20 % 25 4 2 max , max , max , max , max ,       DC o B DD ave D DD DC B DD o o o P P I V I V P I V I V P  id IB t vo VDD/2 t Po PDC t Class Class- -A PA with Resistive Load A PA with Resistive Load
  • 21. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-21 % 50 2 2 max , max , max , max , max ,       DC o B DD ave D DD DC B DD o o o P P I V I V P I V I V P  id IB t vo VDD t Po PDC t Class Class- -A PA with Inductive Load A PA with Inductive Load
  • 22. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-22 DD V   θ IN v   θ OUT v   θ D v   θ OUT i   θ 1 D i   θ IN v T V θ 0 θ   θ 1 D i   θ 2 D i 0 θ   θ 2 D i   θ OUT v 0 0 θ   θ OUT i R V R V P DD om RFout 2 2 2 2   R V π π I θ d θ I π I om D π D DC 2 2 sin 2 1 2 0     785 . 0 4 4 2 2 2      π π DD om DD om om DC RFout Drain V V π V R V R V P P η Class Class- -B Power Amplifiers B Power Amplifiers
  • 23. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-23 •Two Transistors as Push-Pull Amplifier •Transistors Conduct Only HALF CYCLE => Conduction Angle is 180 Degrees •Higher Efficiency Compared to Class-A •Compromised Linearity •Due to Speed Limitation of PMOS, Two NMOS Can Be Used In Parallel with Their Currents Combined By a Transformer Class Class- -B Power Amplifiers B Power Amplifiers
  • 24. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-24 % 78 4 4 2 max , max , , max , max , max , 2 2             DC o DD ave D DD DC DD ave D L DD o o o P P R V I V P R V I R V I V P L L Class Class- -B Power Amplifier B Power Amplifier
  • 25. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-25 DD V   θ IN v   θ OUT v   θ D v RFC   θ OUT i   θ D i   θ IN v TH V θ   θ D i θ 0 θ   θ OUT i   θ OUT v 0   2 cos 1 sin       RFout P     2 2 2 cos sin sin 4 1          DC RFout Drain P P η  Class Class- -C Power Amplifiers C Power Amplifiers
  • 26. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-26 Class Class- -C Power Amplifiers C Power Amplifiers •Transistor Conducts Much Less Than Half of Cycle => Conduction Angle is Close to Zero Degree •Higher Efficiency Compared to Class-A and Class-B •Much Degraded Linearity •Lower Output Power
  • 27. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-27 Non Non- -Linear Power Amplifiers Linear Power Amplifiers •Operate Active Devices as Switches Instead of Amplifying Linear Devices •Highly Non-Linear •Highest Efficiency (~ 100%) •Most Suitable for Applications with Constant-Envelope Modulation •For Linear Applications, Need Linearization Techniques •Includes Class-E, Class-F
  • 28. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-28 Non Non- -Linear Power Amplifiers Linear Power Amplifiers •In Practice, Efficiency is Limited to ~ 60% Due to: •High Speed => Not Too Large Device Size => Finite Turn-On Resistance of the Switch •Finite Turn-On Transition Times •Low-Q Inductors => Off-Chip Inductors or Bond Wires •For High Output Power, Device Stress is Critical
  • 29. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-29  Switch mode  Approaching 100% efficiency DD V   θ IN v   θ D v   θ D i   θ OUT v   θ OUT i 1 C 1 L DD V   θ OUT v 1 C 1 L   θ D v   θ OUT i   θ IN v θ   θ D v θ   θ D i θ   θ OUT v 0 Class Class- -E Power Amplifiers E Power Amplifiers
  • 30. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-30 •Operate Active Device as Switch To Minimize Power Loss and Maximize Efficiency (~ 100%) : •Small Transition Times Between ON and OFF •Small Voltage when Conducting Current •Small Current when Sustaining Large Voltage •Change of Voltage with Time is Close to Zero when Starting Conducting •Parasitic Capacitance of Device Can Be Conveniently Absorbed in Cd Class Class- -E Power Amplifiers E Power Amplifiers
  • 31. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-31     o DD opt DD o d DD r P V R V P C V L 2 2 2 2 2 58 . 0 4 2 4           . OFF ON OFF ON OFF vin id vds t t t Class Class- -E Power Amplifiers E Power Amplifiers
  • 32. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-32  L3C3 tuned to the 2nd or 3rd harmonics  Peak efficiency  88% for 3rd harmonics peaking  85% for for 2nd harmonics peaking. DD V   θ IN v   θ OUT v   θ D v RFC   θ OUT i   θ D i 3 L 3 C   θ IN v TH V θ   θ D v DD V θ   θ D i θ    θ OUT v 0 1 L 1 C Class Class- -F Power Amplifiers F Power Amplifiers
  • 33. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-33 •Employ Harmonics to Simulate a Square Waveform to Minimize Transition Times and thus to Reduce Loss •A Parallel Tank Lr3Cr3 is Included to Obtain a Third-Order Harmonic and to Add to the Fundamental to Approximate a Square Wave Class Class- -F Power Amplifiers F Power Amplifiers
  • 34. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-34 Challenges for CMOS Challenges for CMOS PAs PAs •Trade-Off Among All Parameters •Speed •Device Size •Current and Output Power •Supply Voltage •Loss and Efficiency •Device Stress •Low-Q On-Chip Inductors => Off-Chip Inductors or Bond Wires for Inductors in Resonant Tanks and Matching Network
  • 35. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-35 Linearization Techniques Linearization Techniques •Critical for Both High Efficiency and High Linearity •Use Non-Linear Power Amplifiers (Class E and/or F) for High Efficiency •Use Linearization Techniques to Improve Linearity: •Feed-Forward •Envelope Elimination and Restoration
  • 36. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-36 AP AP 1/AP vin vo vy vx - + - + Feed Feed- -Forward Techniques Forward Techniques
  • 37. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-37 in y x o in y in x y x o v A v A v v A v v A v v A v v v A v v A v v v v v v in v v v                Feed Feed- -Forward Techniques Forward Techniques
  • 38. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-38 Feed Feed- -Forward Techniques Forward Techniques •Open Loop Without Feedback => Unconditional Stability •Limited Linearity Improvement Due to: Gain Mismatches Phase Mismatches Errors of Subtractors •Can Be Extended to Nested Feed-Forward Loops to Improve Linearity at A Cost of More Complexity
  • 39. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-39 Av1 PA vin vo vy vx Envelope Detector Limiter VDD Envelope Elimination and Restoration (EER) Envelope Elimination and Restoration (EER) Techniques Techniques
  • 40. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-40 Envelope Elimination and Restoration (EER) Envelope Elimination and Restoration (EER) Techniques Techniques •Decompose Input Signal into An Envelope and a Phase- Modulated Signal, both of which are Amplified Separately and Recombined •Constant-Envelope High-Frequency Phase-Modulated Component is Generated by “Eliminating” from Input’s Envelope Using a Limiter and then Applied as Input to a High-Efficiency Switching PA
  • 41. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-41 Envelope Elimination and Restoration (EER) Envelope Elimination and Restoration (EER) Techniques Techniques •Non-Constant Low-Frequency Envelope Can Be Extracted by an Envelope Detector, Amplified by a Switching Supply Voltage, and then “Recombined” with RF Phase- Modulated Component By Modulating the PA’s Supply Voltage •Achieve Linearization without Sacrificing Efficiency
  • 42. Introduction to CMOS RF Integrated Circuits Design Fall 2012, Prof. JianJun Zhou VII-42 Envelope Elimination and Restoration (EER) Envelope Elimination and Restoration (EER) Techniques Techniques •Operating Frequencies of the Two Paths are Quite Different •Suffer from Phase and Gain Mismatches => Limited Linearity Improvement •Power Consumption Can Be High => Power Efficiency Can Be Degraded