1. Fan Yang
2151 Oakland Rd, San Jose, CA, 95131
CELLL:(949)562-8011 | LinkedIn: http://www.linkedin.com/in/jamesfanyang | Email: fyang13@uci.edu
SUMMARY
• Seeking for an Entry-Level opportunity in RF Circuit Design/Test, and available now.
• Deeply understanding RF concepts, system and components, especially Front-End: Mixer, LNA and BPF.
• Familiar with different Modulation and Wireless Standards: WiFi, Bluetooth, GSM, CDMA, LTE etc.
• Experienced in Operational Amplifier (Op-amp), ADC, Phase Lock Loop (PLL), and RF Receiver Design.
• Proficiency in C++ and hands-on experience with lab equipment.
EDUCATION
University of California, Irvine 09/2014-06/2016
Master of Science in Electrical Engineering, RF circuit and IC design GPA: 3.42/4.0
Southwest Jiaotong University 09/2009-06/2013
Bachelor of Science in Engineering, Optical Communication direction GPA: 3.1/4.0
EXPERIENCE
Design and Validation of a Passive Mixer-First Receiver 02/2016-03/2016
• Mixer-First structure, antenna directly to passive mixer, is used to lower power and increase linearity;
• A quadrature passive mixer is implemented to achieve a higher impedance matching range;
• Baseband LNA consists of a fully differential pair and CMFB is applied to stabilize the output;
• Analysis the theoretical impedance, noise etc. and simulate the design in Cadence;
• Set signal 205MHz and LO 200MHz, in CMOS process, achieve conversion gain 38.94dB, Noise Figure
3.8127dB. Plot S11 in Smith Chart and get the value -27.43dB at 200MHz;
• Plot a Two-tone IM3 with input sinusoid at 201MHz and 202MHz and analysis the nonlinearity of circuit.
A 2.5 GB/s Clock-data Recovery (CDR) Circuit Design for SONET OC-48 Application 01/2016- 03/2016
• Current Mode Logic (CML) is used as basic cell to gain broader band and reduce duty cycle distortion;
• Design Data Input Buffer, Clock Signal Tune Buffer and Output Buffer to increase the circuit fan-out
capability, maintain the output swing and match the impedance;
• Hogge Phase Detector is applied to compare the phase difference due to its linearity and less jitter;
• Design the VCO using LC topology, because of high-Q and better performance in high frequency range;
PMOS varactor is adopt to realize tuning the frequency range by varying the transistor size;
• Choose reasonable transistor size of VCO to balance common mode swing and phase noise;
• Transconductance (Gm) Cell and Low Pass Filter (LPF) convert the differential voltage to control voltage
of VCO. Build a linear mode in Cadence to verify the linearity of whole loop and simulate in Matlab to
achieve open-loop and close-loop frequency response.
Design and Test of A 12-Bit Successive Approximation Register ADC Chip 03/2015-12/2015
• Design a 12 Bit SAR ADC in ami 0.6um process and realize the accuracy in 1.2 mV at around 100MHz;
• Use positive triggered D Flip-Flop to compose SAR logic and register, design a DAC using both resistor
string and capacitors to balance performance and area;
• Multi-stage preamplifier and dynamic latch to compile the comparator, in order to achieve enough accuracy;
• Finish all the schematic, layout and chip frame design, pass LVS in Cadence and tape out in factory;
• Design and print a PCB test bench to validate the chip function and test performance in lab environment.
SKILL
Software: Cadence Design Software/Virtuoso Layout Editor, L-edit, Altium Designer, ExpressPCB, Matlab;
Familiar Lab Equipment: Vector Network Analyzer, Oscilloscope, Power Meters, Logic Analyzer, etc.