This document discusses the design of a 3-bit flash analog-to-digital converter (ADC). It begins by introducing flash ADCs and their advantages of high speed. A flash ADC uses 2n-1 comparators in parallel to convert an analog input to an n-bit digital code. The document then describes modeling a 3-bit flash ADC in VHDL, including the design of comparators using inputs A and B, and outputs for equal and greater signals. It also covers the use of a priority encoder. Finally, the document discusses another design approach to reduce power consumption by using fewer comparators.

1. Design Flash ADC
3bit

2. Why we used ADC?
 What is the main types of ADC?
Which design we will use ?

3. Model 1 Digital
(VHDL)
Model 2 with minimum
power
Flash ADC

4. Model1 Design Flash ADC
concept of Flash ADC:
The flash ADC is a fastest speed
compared to other ADC architectures.
The flash ADC is also known as the
parallel ADC because of its parallel
architecture.

5. • it is used for high-speed and very large
bandwidth applications such as radar
processing, digital oscilloscopes

6. Flash ADC block diagram

7. The Main component of flash ADC
design:

8. • these architecture needs 2n -1
comparators for a n-bit ADC; for example,
a set of 7 comparators is used for 3-bit
flash ADC. Each comparator has a
reference voltage that is provided by an
external reference source.
• For instance, a 6-bit flash ADC needs 63
comparators, but 1023 comparators are
needed for a 10-bit flash ADC

10. The design of comparator:
• Ai, Bi : Inputs to be compared
• Ein = "1" : It indicates that A and B in previous
comparison are equal to each other
• Gin = "1" : It indicates that A is greater than B in previous
comparison
• Eout= "1" : It indicates that the inputs are equal to each
other
• Gout= "1" : It indicates that A is greater than B

12. • in the design the operation of comparator
to be greater than values only then we
will use the Gout equation only and will be
• Gout=Gin+AiBi′
Note that

13. The design of Priority
Encoder:

14. VHDL Simulation

15. VHDL Simulation

16.  That compare between normal design of
flash and another analogue design to get
lowest power consumption
Resolution and circuit complexity causing
high power consumption are the major
problems with Flash ADC, and these have
limited its application despite its speed of
conversion, which is the fastest among all
types of Analog to Digital Converters”.
Model2 “Design Flash ADC
with Low power ”

17. Two comparators were successfully used
instead of seven which resulted in 92%
reduction in power consumption.
Old design New design
2n-1 2n-3

19. Reference
• [1] Design & Implementation of Low Power 3-bit Flash ADC in
0.18µm CMOS, Pradeep Kumar, Amit Kolhe, international Journal
of Soft Computing and Engineering (IJSCE)ISSN: 2231-2307,
Volume-1, Issue-5, November 2011.
• [2] https://en.wikipedia.org/wiki/Comparator
• [3] http://www.electronics-tutorials.ws/combination/comb_4.html
• [4] Design of a new 3-bit Flash Analog to Digital Converter
(ADC)E. O. Ogunti and F. J. OmotayoDepartment of
Electrical/Electronic Engineering Federal University of Technology,
Akure, Nigeria