SlideShare a Scribd company logo
1 of 1
Download to read offline
PRADEEP C PRASAD
Phone: +1 (520) 328 5148 | Email: pradeepcp032@email.arizona.edu
PROFESSIONAL SUMMARY
Actively seeking full time opportunities in software development and verification starting from May 2016
EDUCATION
UNIVERSITY OF ARIZONA
Master of Science in Electrical and Computer Engineering August 2014 – May 2016
M.S.RAMAIAH INSTITUTE OF TECHNOLOGY.
Bachelor of Engineering in Telecommunication Engineering August 2009– May 2013
 University affiliated: Visvesvaraya Technological University, Belgaum
TECHINICAL STRENGTH
Programming Languages:
 Proficient: C, C++, Data structures using C and C++, Java.
 Familiar: VHDL and Verilog, Basics of Embedded Linux programming, MATLAB, HTML5, OPEN MP, MPI.
 Scripting: Familiar with Shell scripting and Python,
Tools: Xilinx, Micro vision IDE – Keil, Wireshark, WinSCP, Putty, Microsoft Visual studio and Code blocks, NetBeans, eclipse.
Familiar Operating systems: Windows, OS X, Ubuntu.
SUBJECTS TAKEN
Computer Aided Logic Design, Computer Architecture, Computer networks, Digital control, Engineering of Computer based Systems
Cyber Security, Automatic control Systems, Distributed computing systems, Semiconductor processing.
ACADEMIC PROJECTS
Designed a new cache design by comparing the Hierarchies of different levels of caches to that of single level and designing one
that meets the advantages of both: The purpose of this project is to analyze different cache hierarchies and to design one that includes
the benefits of both multilevel and single-level cache. Simple Scalar was used to run simulations with various cache setups to see the
differences in performance as different parameters are changed. Various benchmarks, such as mcf, parser, and applu, will be used to
find the main advantages of both single-level cache and multi-level cache.
Multiple Biometric Parameter Based Intrusion Detection System: Development of an anomaly based intrusion detection system
which continuously uses different biometric features to authenticate the user of the computer/information system: In this project
the device drivers of the keyboard were manipulated using C++ and a software was created in such a way that even if a malicious user
was to hack into the system by the way he types using the keyboard the software determines whether he or she is the default user or not
and locks the system down and notifies the user.
Critical path Calculator and High Level Synthesis Tool: Written in C++ to calculate the critical path using the Depth First search
algorithm (DFS) for a given pseudo C code, this tool is highly useful in finding the frequency of operations if the given code is
implemented in hardware. The main aim of the project was to develop a high level synthesis tool which can generate Verilog code for
the given high level sequential code written in C-like language. Implemented a high level Machine Synthesis tool capable of converting
a High Level State Machine.
Force Directed Scheduling Tool: Developing a tool using C++ that can convert a C-like behavioral description into a scheduled high-
level statement machine implemented in Verilog.
Developed a DNS server On UBUNTU using BIND software: Built DNS server using scripts in Ubuntu by editing DNS cache and
rebinding the DNS server name. This project explains how the DNS cache memory works and methods that can be used to hack a DNS
server cache in local server by rebinding.
Designing a GUI for the VTR simulator: Design and development of GUI using Java as the base language for VTR CAD tool that
can generate architecture files, configuration files, parse the parameters from output files and show on panel and can run benchmarks
with specified architecture file.
Tic TAC Toe: Implemented a tic TAC toe game using Java as the base language
Simulation and Comparison of the Speed of an Armature controlled DC motor using PID Controller and a Fuzzy Logic
Controller in Simulink: The DC motor is modelled and converted as a subsystem in SIMULINK for both the controllers. The simulation
and development of the PID controller is implemented w.r.t the mathematical model of a DC motor using trial and error method. The
Parameters in the PID are tested with the MATLAB/SIMULINK program.

More Related Content

What's hot (20)

Lavina Chandwani Resume
Lavina Chandwani ResumeLavina Chandwani Resume
Lavina Chandwani Resume
 
Resume_Akshay_Deshpande
Resume_Akshay_DeshpandeResume_Akshay_Deshpande
Resume_Akshay_Deshpande
 
Rajendra Cv
Rajendra CvRajendra Cv
Rajendra Cv
 
RESUME_SaranyaNagaraj_A
RESUME_SaranyaNagaraj_ARESUME_SaranyaNagaraj_A
RESUME_SaranyaNagaraj_A
 
Updated Resume - Tanmay Chaturvedi
Updated Resume - Tanmay ChaturvediUpdated Resume - Tanmay Chaturvedi
Updated Resume - Tanmay Chaturvedi
 
Nagaraj belur
Nagaraj belurNagaraj belur
Nagaraj belur
 
Resume_Prathamesh_Ghanekar
Resume_Prathamesh_GhanekarResume_Prathamesh_Ghanekar
Resume_Prathamesh_Ghanekar
 
Shrilesh kathe 2017
Shrilesh kathe 2017Shrilesh kathe 2017
Shrilesh kathe 2017
 
Resume
ResumeResume
Resume
 
oyedele_resume_updated
oyedele_resume_updatedoyedele_resume_updated
oyedele_resume_updated
 
cv_anudeep
cv_anudeepcv_anudeep
cv_anudeep
 
Phanidhar Gorrepati
Phanidhar GorrepatiPhanidhar Gorrepati
Phanidhar Gorrepati
 
Resume_Apple1
Resume_Apple1Resume_Apple1
Resume_Apple1
 
ApoorvJoshi_Resume
ApoorvJoshi_ResumeApoorvJoshi_Resume
ApoorvJoshi_Resume
 
Gopi manohar Resume
Gopi manohar ResumeGopi manohar Resume
Gopi manohar Resume
 
Marek Suplata Projects
Marek Suplata ProjectsMarek Suplata Projects
Marek Suplata Projects
 
vamshiresume
vamshiresumevamshiresume
vamshiresume
 
PrathikR_Resume
PrathikR_ResumePrathikR_Resume
PrathikR_Resume
 
KamalTeja_CV
KamalTeja_CVKamalTeja_CV
KamalTeja_CV
 
RESUME
RESUMERESUME
RESUME
 

Viewers also liked

Reference letter Kanwaldeep Kaur
Reference letter Kanwaldeep KaurReference letter Kanwaldeep Kaur
Reference letter Kanwaldeep KaurKanwaldeep Kaur
 
Nota de Prensa N° 005-2016-DREM.M
Nota de Prensa N° 005-2016-DREM.MNota de Prensa N° 005-2016-DREM.M
Nota de Prensa N° 005-2016-DREM.MGREM Moquegua
 
開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk
開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk
開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalkBIGLOBE Tech Talk
 
презентація 27.02
презентація 27.02презентація 27.02
презентація 27.02novoarhnvk1
 
Ciclos termodinámica
Ciclos termodinámicaCiclos termodinámica
Ciclos termodinámicaErrer Coiler
 
Polymer chemistry
Polymer chemistryPolymer chemistry
Polymer chemistryPichai Mpm
 
テストエンジニアと組織構造 @Cybozu
テストエンジニアと組織構造 @Cybozuテストエンジニアと組織構造 @Cybozu
テストエンジニアと組織構造 @CybozuJumpei Miyata
 
Cosmic Adventure 4.7-8 Positioning & Timing in Classical Physics
Cosmic Adventure 4.7-8 Positioning & Timing in Classical PhysicsCosmic Adventure 4.7-8 Positioning & Timing in Classical Physics
Cosmic Adventure 4.7-8 Positioning & Timing in Classical PhysicsStephen Kwong
 

Viewers also liked (14)

Presupuesto
PresupuestoPresupuesto
Presupuesto
 
Reference letter Kanwaldeep Kaur
Reference letter Kanwaldeep KaurReference letter Kanwaldeep Kaur
Reference letter Kanwaldeep Kaur
 
Nota de Prensa N° 005-2016-DREM.M
Nota de Prensa N° 005-2016-DREM.MNota de Prensa N° 005-2016-DREM.M
Nota de Prensa N° 005-2016-DREM.M
 
Vinothkumar_Pandian
Vinothkumar_PandianVinothkumar_Pandian
Vinothkumar_Pandian
 
David De Palma Resume
David De Palma ResumeDavid De Palma Resume
David De Palma Resume
 
Presupuesto
PresupuestoPresupuesto
Presupuesto
 
開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk
開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk
開発エンジニアがChefで テスト駆動サーバー設定してみた #biglobetechtalk
 
55555
5555555555
55555
 
презентація 27.02
презентація 27.02презентація 27.02
презентація 27.02
 
Ciclos termodinámica
Ciclos termodinámicaCiclos termodinámica
Ciclos termodinámica
 
20160914 te engineer
20160914 te engineer20160914 te engineer
20160914 te engineer
 
Polymer chemistry
Polymer chemistryPolymer chemistry
Polymer chemistry
 
テストエンジニアと組織構造 @Cybozu
テストエンジニアと組織構造 @Cybozuテストエンジニアと組織構造 @Cybozu
テストエンジニアと組織構造 @Cybozu
 
Cosmic Adventure 4.7-8 Positioning & Timing in Classical Physics
Cosmic Adventure 4.7-8 Positioning & Timing in Classical PhysicsCosmic Adventure 4.7-8 Positioning & Timing in Classical Physics
Cosmic Adventure 4.7-8 Positioning & Timing in Classical Physics
 

Similar to RESUME_SW (20)

resume19_new5
resume19_new5resume19_new5
resume19_new5
 
KatherineYekhilevsky_2015
KatherineYekhilevsky_2015KatherineYekhilevsky_2015
KatherineYekhilevsky_2015
 
JustinCellonaResumeUpdated
JustinCellonaResumeUpdatedJustinCellonaResumeUpdated
JustinCellonaResumeUpdated
 
jidesh_res_updated
jidesh_res_updatedjidesh_res_updated
jidesh_res_updated
 
Dipak_Desai_Resume
Dipak_Desai_ResumeDipak_Desai_Resume
Dipak_Desai_Resume
 
Resume
ResumeResume
Resume
 
Rohan resume
Rohan resumeRohan resume
Rohan resume
 
Amruth_Kumar_Juturu_Resume
Amruth_Kumar_Juturu_ResumeAmruth_Kumar_Juturu_Resume
Amruth_Kumar_Juturu_Resume
 
CV_Serhiy_Medvedyev_2015
CV_Serhiy_Medvedyev_2015CV_Serhiy_Medvedyev_2015
CV_Serhiy_Medvedyev_2015
 
Resume_Basith
Resume_BasithResume_Basith
Resume_Basith
 
Updated_resume
Updated_resumeUpdated_resume
Updated_resume
 
Rashmi_Resume
Rashmi_ResumeRashmi_Resume
Rashmi_Resume
 
VenutoResume
VenutoResumeVenutoResume
VenutoResume
 
Julio andradecv
Julio andradecvJulio andradecv
Julio andradecv
 
CV - Mohsan Raza Ali - Development Manager
CV - Mohsan Raza Ali - Development ManagerCV - Mohsan Raza Ali - Development Manager
CV - Mohsan Raza Ali - Development Manager
 
jeevanreddy-nwplm
jeevanreddy-nwplmjeevanreddy-nwplm
jeevanreddy-nwplm
 
Gajendra_RESUME
Gajendra_RESUMEGajendra_RESUME
Gajendra_RESUME
 
_SOMANATH_
_SOMANATH__SOMANATH_
_SOMANATH_
 
SHIRAS,JANHAVI
SHIRAS,JANHAVI SHIRAS,JANHAVI
SHIRAS,JANHAVI
 
Rachit_HMI_Development_resume
Rachit_HMI_Development_resumeRachit_HMI_Development_resume
Rachit_HMI_Development_resume
 

RESUME_SW

  • 1. PRADEEP C PRASAD Phone: +1 (520) 328 5148 | Email: pradeepcp032@email.arizona.edu PROFESSIONAL SUMMARY Actively seeking full time opportunities in software development and verification starting from May 2016 EDUCATION UNIVERSITY OF ARIZONA Master of Science in Electrical and Computer Engineering August 2014 – May 2016 M.S.RAMAIAH INSTITUTE OF TECHNOLOGY. Bachelor of Engineering in Telecommunication Engineering August 2009– May 2013  University affiliated: Visvesvaraya Technological University, Belgaum TECHINICAL STRENGTH Programming Languages:  Proficient: C, C++, Data structures using C and C++, Java.  Familiar: VHDL and Verilog, Basics of Embedded Linux programming, MATLAB, HTML5, OPEN MP, MPI.  Scripting: Familiar with Shell scripting and Python, Tools: Xilinx, Micro vision IDE – Keil, Wireshark, WinSCP, Putty, Microsoft Visual studio and Code blocks, NetBeans, eclipse. Familiar Operating systems: Windows, OS X, Ubuntu. SUBJECTS TAKEN Computer Aided Logic Design, Computer Architecture, Computer networks, Digital control, Engineering of Computer based Systems Cyber Security, Automatic control Systems, Distributed computing systems, Semiconductor processing. ACADEMIC PROJECTS Designed a new cache design by comparing the Hierarchies of different levels of caches to that of single level and designing one that meets the advantages of both: The purpose of this project is to analyze different cache hierarchies and to design one that includes the benefits of both multilevel and single-level cache. Simple Scalar was used to run simulations with various cache setups to see the differences in performance as different parameters are changed. Various benchmarks, such as mcf, parser, and applu, will be used to find the main advantages of both single-level cache and multi-level cache. Multiple Biometric Parameter Based Intrusion Detection System: Development of an anomaly based intrusion detection system which continuously uses different biometric features to authenticate the user of the computer/information system: In this project the device drivers of the keyboard were manipulated using C++ and a software was created in such a way that even if a malicious user was to hack into the system by the way he types using the keyboard the software determines whether he or she is the default user or not and locks the system down and notifies the user. Critical path Calculator and High Level Synthesis Tool: Written in C++ to calculate the critical path using the Depth First search algorithm (DFS) for a given pseudo C code, this tool is highly useful in finding the frequency of operations if the given code is implemented in hardware. The main aim of the project was to develop a high level synthesis tool which can generate Verilog code for the given high level sequential code written in C-like language. Implemented a high level Machine Synthesis tool capable of converting a High Level State Machine. Force Directed Scheduling Tool: Developing a tool using C++ that can convert a C-like behavioral description into a scheduled high- level statement machine implemented in Verilog. Developed a DNS server On UBUNTU using BIND software: Built DNS server using scripts in Ubuntu by editing DNS cache and rebinding the DNS server name. This project explains how the DNS cache memory works and methods that can be used to hack a DNS server cache in local server by rebinding. Designing a GUI for the VTR simulator: Design and development of GUI using Java as the base language for VTR CAD tool that can generate architecture files, configuration files, parse the parameters from output files and show on panel and can run benchmarks with specified architecture file. Tic TAC Toe: Implemented a tic TAC toe game using Java as the base language Simulation and Comparison of the Speed of an Armature controlled DC motor using PID Controller and a Fuzzy Logic Controller in Simulink: The DC motor is modelled and converted as a subsystem in SIMULINK for both the controllers. The simulation and development of the PID controller is implemented w.r.t the mathematical model of a DC motor using trial and error method. The Parameters in the PID are tested with the MATLAB/SIMULINK program.