1. RM Yegammai
+91 9962809650
E-mail: sindhu.sypna@gmail.com
Profile Summary
Automation Test Engineer, having 2 years and seven months of experience in design and development of
Automated Test Software using NI-LabVIEW, NI Test Stand and also in the design and development of test
Fixtures (Bed of Nail Fixture), DFT Analysis and System Testing for products under various domains .
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Total Experience : 2 Years and Seven months.
Present Company : Sanmina Corporation.
Duration : Feb 2013 till date.
Present Role : ATE Engineer.
Technical Summary
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High Proficiency in NI LabVIEW 201x (CLAD Certified), NI TestStand 201x. 
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Experience in embedded C based Arduino IDE coding.
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Expertise in CAD and Schematic DFT analysis using tools like Test Sight and Valor 8.
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Experience in test strategy designing using tools like Test Way. 
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Worked in design tools Cadence Allegro 16.3 for Personalized PCBA schematic designing. 
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Expertise in handling track recording tools like Agile and good knowledge in Medical
documentation process. 
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Worked in Perl Script to automate Cypress PSoC Programmer. 
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Handled and automated devices like DMM, Programmable power supply and Oscilloscope. 
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Hands on experience in Boundary Scan technology. 
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Hands on experience with protocols like RS232, SPI, I2C and USB. 
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Expertise in design and development of Test Fixture, ATE BOM preparation, Remote support
in Factory for test software Installation and trouble shooting. 
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Experienced in functional, device level, integration level and system level testing. 
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Experienced in Test planning, test scenarios & test cases design. 
Technical Skills
Operating System Windows XP, 7.
Languages and Tools
NI LabVIEW 201x ,NI TestStand , Test Sight, Test Way, Cadence
Allegro 16.3, ,Valor 8.x,embedded C, Agile, Perl.
Protocols RS232, SPI, I2C, UART and USB
Instruments and Cards Used
PSoc Programmer, BeeProg Debugger, ATMega2560,
Programmable Oscilloscope & Power Supplies, DAQ and DMM.

2. Industry project experience
Project 8
Generalized Data Acquisition module Design.
Domain : Industrial.
Environment : Cadence Allegro and Arduino IDE software.
Product :
A Common DAQ module that carries 16 Relay Module, 16 DIO, 8 Analog IO
and I2C, SPI Interface.
Responsibilities: Project Lead
 Part Identification for Schematic design.
 Concept and schematic design Implementation for Relay driving using ULN ICs, Analog Output measurement,
Digital Pin configuration and measurement. 
 Coding in embedded C platform for Atmega 2560 Controller. 
 User friendly command window instruction to call PCBA functions from various platforms. 
 C protocol driver coding.
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Project 7
Chip Security Card Swipe device - Test coverage analysis.
Domain : Industrial.
Environment : Test Way, Test Sight, Valor.
DUT
: The DUT in this case is three boards – Main PCBA, Transceiver PCBA and
Antenna PCBA of a security card swipe machine.
Responsibilities: ATE Engineer.
 Schematic analysis for testability.
 BSCAN coverage analysis. Identifying alternate resource with 1149.1 standard JTAG compatibility for ICs
without 1149.1 standard to increase test coverage.
 Importing PCB data to the tool and generating tool understandable format of BOM file.
 Classifying the component and generating Model for ICs by identifying the operation of each particular Pin.
 Performing DFT analysis and identifying the accessible nets through Reports.
 Suggesting different test strategy to increases the coverage of testing in cost effective way.
Project 6
Test System Tester – Board level FCT.
Domain : Industrial.
Environment : NI LabVIEW 2011.
DUT
: The DUT in this case is two board – which is used to validate the tester
system which in turns used to validate the heat co-efficient of mobile battery
Responsibilities: ATE Engineer.
 To test and validate the Temperature Sensor and EEPROM Using I2C interface. 
 Mechanical concept designing for test fixture that can gets adapted to PCBA of different form factor.
 Communicating with vendors for hardware procurement. 
 To test and validate the communication between both the boards, by programming the EEPROM with PCBA
serial number in one and polling for serial number from other one.
 The trace resistance at maximum current setting is measured by shorting the Force and Sense net. The
programmable power supply measure for voltage and current from which indirectly trace resistance is
derived. 
 To call the dll of the tester functionalities that in turns test the mobile battery. 
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3. Project 5
Next Generation Drive Assembly EOL - Test Software.
Domain :: Medical.
Environment : NI LabVIEW 2011.
DUT
: Design and develop FCT Test Software for Next generation Drive Assembly
Unit - Parallel DUT (Configurable Max – 8) testing.
Responsibilities: ATE Engineer.
 Requirement analyze and define test cases. 
 Implemented Customer Specific XML Based Database integrated with test software to log Test results.
 Test Software User Interface design. 
 Architectural design—determines the software framework. 
 Initially proposed to use TestStand for Parallel Testing – Due to Limitation of customer provided 64bit dll,
Teststand option was dropped and implemented in LabVIEW ADE. 
 Detailed test software design and coding of Test cases as well as report formatting.
 Unit testing and debug of test software – whether it meets the specified requirements and finds any errors
present in the code. 
 Test Software Installation at Client Location remotely and Validation for Gage R&R. 
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Project 4
Circuit Simulation System - Schematic DFT.
Domain : Industrial.
Environment : Valor 8, Test Sight, PDF Viewer.
DUT
: The DUT is circuit simulation software system which accommodate n
number of logic gates, FPGA and DDR.
Responsibilities: ATE Engineer.
 Performed DFT analysis using Test Sight and generated reports for accessible Nets. 
 Analyzed and Priorities the criticality of Inaccessible nets by referring Schematics. 
 Classified the nets that gets covered in different stages of testing and derived the net percentage of test
coverage. 
 Identified the devices 1149.1 compliance and JTAG chain for BSCAN test sequencing. 
 Prescribed the test strategy for testing the PCBA in efficient way. 
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Project 3
Sleep Monitoring device – System Testing.
Domain : Medical.
Environment : Agile.
DUT : Functional testing for Sleep Monitoring device.
Responsibilities: ATE Engineer.
 Supported to upgrade the device from Industrial Product to Medical product by proper documentation. 
 Maintained track record for documentation using Agile. 
 Preparation of test report, User Manual Design Documents and Validation Documents. 
 Standardized the format for Gauge R & R report. 
Project 2
Contactless Connectivity Module – System Level Testing.
Domain : Industrial.
Role : ATE Engineer.
Environment : NI LabVIEW 2012, NI TestStand 2013, Cadence Allegro 16.3.

4. DUT :
Contactless Power & Data connectivity module. Each TX & RX Module has a
Unidirectional Power link & Data link. Power link is based on Inductively
Coupled Power Transfer. Data link is based on 2.4 GHz RF Technology
supporting different protocols. (GPIO, Analog, IO Link etc.)
Responsibilities: Module Lead Engineer.
 Requirement analysis for programming the Nordic and Cypress controller. 
 Concept design for programming test fixture and hardware procurement. 
 Personalized PCBA designing using Cadence Allegro for Level shifting, Variable Gain Amplification, current
sensing and Relay Switching. 
 CE certification for the Tester to be launched in Europe. 
 Automated PSoC controller programming by Perl Scripting and Nordic controller programming by JTAG lines. 
 Maintained track record for the items purchased in this project. 
 Code Modules developed in NI LabVIEW and sequencing done with NI TestStand for two point calibration
of current. 
 Test Report generation and data logging. 
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Project 1
Board Level Functional Tester.
Domain :: Medical.
Role :: ATE Engineer.
Environment : NI LabVIEW 2011, MS Visio.
DUT
: The DUT in this case is three boards – Main PCBA, LED PCBA and
Interface PCBA of a bottle sterilization system.
Responsibilities: ATE Engineer.
 This fixture involves the measurement of Voltage and Impedance.
 To design mechanical concept for interconnecting PCBA.
 Test GUI designing and Architecture freezing.
 Hardware wiring concept designing and supervising.
 All the Signal generation to the unit is monitored by Agilent 34970A unit.
 Preparation of test report , User Manual Design Documents and Validation Documents
 Onsite Installation of Test software in customer place.
Academics
B.E - Electronics and Instrumentation
Engineering 2009-13 Anna University, Chennai 79%
Class XII 2008-09 Vidya Vikas Educational Institution 79%
Class X 2006-07 Chidambaram Chettiar Hr Sec School 89%
Personal Information
Name : Yegammai RM
Father’s Name : Ramanathan RM
Date of Birth : 30th
Sep 1991
Sex : Female
Marital Status : Single
Declaration
I hereby declare that the information above is true to the best of my knowledge.
Date : 17.8.2015
Place : Chennai. RM. Yegammai.