Batch of 2019 BITSG

1. Group: 86
Topic: 5
Group Members:
Akarsh Mishra
Jemin Mehul Mehta
Mayank Mathur
Sudhanshu Singh
Aditya Deven Mishra
Aditya Rathi

2. Block Diagram

3. State
Diagram

4. Sample Input Output
INPUT
OUTPUT

5. Additional Functionalities
1. Start/Stop button (to enable/disable the alarm)
2. Snooze button having options for snoozing for one minute or for two minutes.
3. Option for the user to switch between a 12 hour and 24-hour format with display.
4. A seven segment display to aid the user to set the alarm in the digital alarm clock.
5. The alarm clock has the provision to ring every day at the time set by the user.
6. The user can input the alarm time normally and does not need to have any knowledge of
binary or BCD numbers ( user friendly alarm clock)

17. Working Of The DIgital Alarm Clock(Group 86)
A 2 Hz (signal at every 1 second interval) square wave from an astable multivibrator is
applied as a clock signal to the S0 counter consisting of four negative edge triggered T-FF
which counts from 0 to 9 after every second. After 9, the values reset back to 0 for which an
AND gate has been used to check for the maximum values and reset it as it crosses the max
value. Whenever S0 (4 bits) crosses the 9th count, a clock signal has to be generated. This
clock signal is applied to the S1 counter consisting of three T-FF which counts from 0 to 5.
After it reaches 5 and S0 becomes 9, the next pulse will make both S1 & S0 zero.
When S1 (3 bits) becomes 000, a clock pulse is generated and applied onto the negative edge
triggered M0 T-FF. This is extended to M1 just like S1. And similar to S1 when M1 (also 3 bits)
becomes 000, a clock pulse is applied to H0 and then the output of H0 is applied to H1. Both H0
and H1 are 4 bit counters consisting of 4 JK-FF’s counting from 0 to 23.Similarly the input for the
days counter( two counters each containing 4 JK-FF’s) count the total number of days from 0 to
30.The hours and days counters are essentially a two decade decimal BCD counter. Like the S0
and S1 counters , the M0,M1,H0,H1,D0,D1 are also reset at appropriate times. As these
counters count in BCD, so BCD to seven segment converters have been used
appropriately(these components have been instantiated(present in a different Logisim file) and
their functionality has been used in the main circuit)
Each S0, S1, M0 & M1 counter's data is converted to 7 segment display format by IC 7448
and applied to a 7 segment display. So, the 7 segment displays show the time as it is stored
in the flip-flops.
The alarm module uses a magnitude comparator to compare the user defined time to the
time of the alarm clock( minutes , hours and days are compared). The time entered by the
user is shown in the 7 segment display and this input is connected to the magnitude
comparator. As explained earlier, the first 6 bits are dedicated to H0 and H1, the next 3 bits
are M1 and the last 4 bits are for M0. The magnitude comparator is connected to the input
entered by the user and the clock. The output of the equality output from the magnitude
comparator is given to the AND gate connected, along with the Start/Stop button. The input
from the Start/Stop switch(used to enable/disable the alarm clock) is given to the AND gate
which is then connected to the LED(Alarm). The Snooze function uses an adder which can
add 1 or 2 minutes as desired by the user to the M0 and extend the time for the alarm to
ring. When the times match the LED lights up for a minute if not switched off or snoozed.

18. At a point of time in digital electronics, it was realized that you needed to remember past values to
calculate new ones. For example, take our very own counters. You need to know what the previous
number was, so that you can count to the next one. Nly if you knew the previous number is 2 you can
say the next number is 3 right?
By definition, a circuit whose present output depends on present input and past output is called a
sequential circuit. Counters are sequential circuits. So a way had to be found to remember the previous
state. This led to the development of a latch. A latch is a simple circuit that “latches on” or stores 1 or 0.
As seen from the circuit, a latch has two NOR (complement of OR) gates the output of one given as input
of another. One output is always the complement of the other Q and Q’ It will soon be clear why this is
so and also why the inputs are named R & S. Assuming that you know the truth of NOR, let’s see how
the latch works.
Let’s assume the initial input of R and S is 1 and 0 respectively. If any one of the inputs for NOR is 1, the
output is 0. Since R is 1 in 1st
NOR, Q has to be zero. This Q is fed to the 2nd
NOR. Now since both Q and S
are zero, the output Q’ is 1 (notice Q and Q’ are complementary).
Now let’s make R = 0 so both R and S are 0. Since Q is 0 and S=0, output of 2nd
NOR is 1 and this Q’ = 1
makes the output of 1st
NOR 0 causing Q = 0. So both Q and Q’ “retain” their previous value or their
values haven’t changed. Now let’s make S= 1 and R=0.
Since S=1, Q’ becomes 0. Now Q’ and R are 0 making Q = 1. Now let’s again make both R and S zero. But
now Q = 1 and this causes Q’ to be 0. Since both Q’ and R are zero, Q = 1. Again the values are retained.
So when S = 1 & R = 0, Q = 1. This is called set because you are setting the value to 1. In digital
vocabulary, set means 1 and reset means 0. Again when S = 0 & R = 1, Q =0. This is reset because the
value of Q is resetted to 0. Q and Q’ are noticeably complimentary.
But what happens when both R and S are 1. This condition if forbidden because, such a state gives an
undesirable output.
This is called a latch based on NOR. A similar one with NAND looks like this

19. The working is almost similar only the inputs are different, you have complement of S and R which
means when S = 0 it is set state and when R = 0 as reset state.
When you want to change Q, you apply suitable values to S and R. But as long as b
Q’ don’t change (memory). Last assigned value of Q and Q’ are retained.
So the characteristics table for this latch is:
NOR latch
S R Q Q’
0 0 (memory)
1 0 1 0
0 1 0 1
1 1 (forbidden)
So, we have our basic memory device. But it isn’t good enough because S=0, R=0 has to be maintained
for memor condition. Any immediate change in S and R affects Q and Q’. We want the l
values only when we need them. This is where a clock signal comes. A clocked latch is called a flip
When the clock is ‘0’, irrespective of S & R, the 1
latch has S’, R‘ inputs. So if S’ and R’ are 1 (the notations are so used for our easier understanding only) it
is memory state. So as long as clock is low any change in S and R will not affect Q and Q’. This is clocking
concept.
The working is almost similar only the inputs are different, you have complement of S and R which
means when S = 0 it is set state and when R = 0 as reset state.
When you want to change Q, you apply suitable values to S and R. But as long as both S & R are 0, Q and
Q’ don’t change (memory). Last assigned value of Q and Q’ are retained.
So the characteristics table for this latch is:
NAND latch
S’ R’ Q
0 0 (forbidden)
(set) 1 0 0
(reset) 0 1 1
(forbidden) 1 1 (memory)
So, we have our basic memory device. But it isn’t good enough because S=0, R=0 has to be maintained
for memor condition. Any immediate change in S and R affects Q and Q’. We want the l
values only when we need them. This is where a clock signal comes. A clocked latch is called a flip
When the clock is ‘0’, irrespective of S & R, the 1st
and 2nd
NAND gates output 1. Remember a NAND
and R’ are 1 (the notations are so used for our easier understanding only) it
is memory state. So as long as clock is low any change in S and R will not affect Q and Q’. This is clocking
The working is almost similar only the inputs are different, you have complement of S and R which
oth S & R are 0, Q and
Q’
(forbidden)
1 (reset)
0 (set)
(memory)
So, we have our basic memory device. But it isn’t good enough because S=0, R=0 has to be maintained
for memor condition. Any immediate change in S and R affects Q and Q’. We want the latch to change
values only when we need them. This is where a clock signal comes. A clocked latch is called a flip-flop.
NAND gates output 1. Remember a NAND
and R’ are 1 (the notations are so used for our easier understanding only) it
is memory state. So as long as clock is low any change in S and R will not affect Q and Q’. This is clocking

20. When clock is high, the 1st
and 2nd
NAND output are complements of S and R and the usual functions of
NAND latch is carried out. This is called a S R flip flop.
S R Flip Flop
Clk S R Q Q’
0 X X (memory) X – don’t care or whatever value
1 0 0 (memory)
1 0 1 0 1
1 1 0 1 0
1 1 1 (forbidden)
Even after clocking the forbidden condition exists. Now let us analyze the characteristics table of S R flip-
flop. We don’t want both S = 1 and R = 1 because it is forbidden. We don’t need S = 0 and R = 0, because
we can use the clock for memory purposes. The essential required conditions are when S = 1 and R = 0
or S = 0 and R = 1. In both the essential conditions S and R are complements. So, if S and R are made to
be complements then we can effectively remove both the forbidden condition and the redundant
condition. So we take one input ‘D’ and we apply the same to ‘S’ and we complement D and apply that
to R.
And this is called the D flip flop. D stands for delay or data. It is more suited to be called Data flip flop
because, as long as the clock is high the value of D is obtained at Q. If clock is low the value of D doesn’t
affect Q and Q has the last retained value.
D flip flop
Clock D Q Q’
0 X (memory)
1 1 1 0
1 0 0 1

21. One should actually talk about JK flip flops before T flip flops but to talk about JK flip flop concepts one
has to also talk about master-slave configuration etc all of which is out of the scope of this article. For
sake of blunt knowledge, a T flip lop is a JK flip flop in which J = K. For now, the characteristics table of T
flip flop will be more than sufficient.
T flip flop
Clock T Q Q’
0 X (memory)
1 0 Q Q’ (no change)
1 1 Q’ Q (both outputs are complemented)
So when T = 1, Q is complemented. This complementing action is called toggling and so toggle – T flip
flop.
One more basic concept is triggering or how does the clock enable or disable the flip flop.
We saw that as long as clock remains high changes can occur. Such a change is called level triggering.
The change is triggered as long as the clock is in logic high level.
More complicated flip flop circuits have been developed (especially for high frequency applications) that
respond only to changes in the clock signal i.e., change from low to high or high to low. If a flip flop is
triggered by a change in clock from low to high it is called positive edge trigger. If a flip flop is triggered
by a change in clock from high to low it is called negative edge trigger.
Commercially available D flip-flop IC 7474 is positive edge triggered. Commercially available JK flip-flop
IC 7476 is negative edge triggered. Following are representations of the triggering often seen in IC
datasheets etc.

22. This might be useful to understand flip flop’s uses.

23. Billing (Group 86)
​
IC Number Function of the IC Number of IC’s Used
7448 BCD to 7 segment converter 12
7408 Quadra AND circuit 14
7404 Six Inverter circuit 2
7476 Dual JK Flip flop 17
7483 4 bit Full Adder 3
74HC688D 8 bit Magnitude comparator 2
7214 LED Matrix 3
7432 Dual OR Gate 7

24. ASSUMPTIONS:-
1) All gate delays are neglected
2) It is assumed that the clock signal frequency remains a constant
3) All components used are not defective and working properly
ADDITIONAL FUNCTIONALITY: -
1. Start/Stop button (to enable/disable the alarm)
2. Snooze button having options for snoozing for one minute or for two minutes.
3. Option for the user to switch between a 12 hour and 24-hour format with display.
4. A seven segment display to aid the user to set the alarm in the digital alarm clock.
5. The alarm clock has the provision to ring every day at the time set by the user.
6. The user can input the alarm time normally and does not need to have any knowledge of
binary or BCD numbers ( user friendly alarm clock)