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# Logic design alexander1 christopher

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ASSIGNMENT FOR 2012 BSCIT 1 SEMESTER ONE

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### Logic design alexander1 christopher

1. 1. 1. Convert the following hexadecimal numbers to base 10: a. 1458Answer;14516=(b)10Where b is the number of base 10;Therefore;1x162+4x161+5x1601X16X16+4X16+5X1256+64+5=32510b .A2C1Answer;A2C116=(b)10Where b is the number of base 10;Therefore;AX163+2X162+CX161+1X16010X16X16X16+2X16X16+12X16+1X140960+512+192+1=4166510Q2: Universal gate these are gate that are used to design other gates. They are gate that use toimplement other high gate. They are gate that are used to carry out or express Boolean expression. TheNAND gate is a universal gate in the sense that any Boolean function can be implemented by NANDgates.The NAND gates are one of the two basic logic gates (the other being NOR logic gates) from whichany other logic gates can be built. Due to this property, NAND and NOR gates are sometimes called"universal gates". However, modern integrated circuits are not constructed exclusively from a singletype of gate.A universal gate is a gate which can implement any Boolean function without need to use any othergate type. The NAND and NOR gates are universal gates.In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricateand are the basic gates used in all IC digital logic families. In fact, an AND gate is typicallyimplemented as a NAND gate followed by an inverter not the other way around!! Likewise, an ORgate is typically implemented as a NOR gate followed by an inverter not the other way around!!NAND Gate:
2. 2. The NAND gate represents the complement of the AND operation. Its name is an abbreviation ofNOT AND. The graphic symbol for the NAND gate consists of an AND symbol with a bubble on theoutput, denoting that a complement operation is performed on the output of the AND gate.The truth table and the graphic symbol of NAND gate is shown below;NAND Gate is a Universal Gate;To prove that any Boolean function can be implemented using only NAND gates, we will show thatthe AND, OR, and NOT operations can be performed using only these gates.Implementing an Inverter Using only NAND Gate;1. All NAND input pins connect to the input signal Agives an output A’.2. One NAND input pin is connected to the input signal A while all other input pins are connected tologic 1. The output will be A’.
3. 3. Implementing an AND using only NAND GATE;3. An AND gate can be replaced by NAND with its output complemented by a NAND gate inverter.Implementing OR Using only NAND Gates;4. An OR gate can be replaced by NAND with it’s input complemented by a NAND gate inverter.Thus ,the NAND gate is a unversal gate since it can implement the AND,OR and NOT functions.
4. 4. NOR Gate:The NOR gate represents the complement of the OR operation. Its name is an abbreviation of NOTOR. The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output,denoting that a complement operation is performed on the output of the OR gate.The truth table and the graphic symbol of NOR gate as showbelow;The truth table clearly shows that the NOR operation is the complement of the OR.NOR Gate is a Universal Gate:To prove that any Boolean function can be implemented using only NOR gates, we will show thatthe AND, OR, and NOT operations can be performed using only these gates.Implementing and inverter using NOR gate; 1. All NOR input pins connect to the input signal A gives an output A’. 2. One NOR input pin is connected to the input signal A while all other input pins are connected to logic 0. The output will be A’.
5. 5. Implementing OR Using only NOR Gates; 1. The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter.Implementing AND Using only NOR Gates; 2. The NAND gates is replaced by a NOR gate with all its inputs complemented by NOR gates inverters.1Thus, the NOR gate is a universal gate since it can implement the AND, OR andNOT functions.The reason why they are called universal gate; 1. Universal gates are the ones from which we can design other gates also. foreg. NAND and NOR gates. they help in forming the uniformity in the circuits. 2. NAND and NOR both are called as universal gate. You can built any circuit or design using either NAND or NOR, this will be so flexible to fabricate any circuit in a single chip 3. They are less expensive to construct5. Draw and explain the working of JK, S-R, and D flip flops.JK flip-flop
6. 6. A circuit symbol for a positive-edge-triggered JK flip-flopJK flip-flop timing diagramThe JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting theS = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is acommand to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop;and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to thelogical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, butrather, will hold the current state. To synthesize a D flip-flop, simply set K equal to thecomplement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop istherefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.The characteristic equation of the JK flip-flop is:and the corresponding truth table is: JK Flip Flop operation[28]Characteristic table Excitation tableJ K Qnext Comment Q Qnext J K Comment0 0 Q hold state 0 0 0 X No change0 1 0 reset 0 1 1X Set1 0 1 set 1 0 X 1 Reset1 1 Q toggle 1 1 X 0 No change
7. 7. S-R NOR latchAn SR latch, constructed from a pair of cross-coupled NOR gate (an animated picture). Red and blackmean logical 1 and 0, respectively.When using static gates as building blocks, the most fundamental latch is the simple S-R latch,where S and R stand for set and reset. It can be constructed from a pair of cross-coupledNORlogic gates. The stored bit is present on the output marked Q.While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constantstate, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then theQ output is forced high, and stays high when S returns to low; similarly, if R is pulsed high whileS is held low, then the Q output is forced low, and stays low when R returns to low. S-R Flip Flop operationCharacteristic table Excitation tableS R Qnext Action Q Qnext S R00 Q hold state 0 0 0 x01 0 reset 0 1 1 010 1 set 1 0 0 11 1 X not allowed 1 1 X 0The R = S = 1 combination is called a restricted combination or a forbidden state because, asboth NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination isalso inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition fromrestricted to keep). The output would lock at either 1 or 0 depending on the propagation timerelations between the gates (a race condition). In certain implementations, it could also lead to
8. 8. longer ringings (damped oscillations) before the output settles, and thereby result inundetermined values (errors) in high-frequency digital circuits. Although this condition is usuallyavoided, it can be useful in some applications.To overcome the restricted combination, one can add gates to the inputs that would convert(S,R) = (1,1) to one of the non-restricted combinations. That can be: Q = 1 (1,0) – referred to as an S-latch Q = 0 (0,1) – referred to as an R-latch Keep state (0,0) – referred to as an E-latchAlternatively, the restricted combination can be made to toggle the output. The result is the JKlatch.Characteristic: Q+ = RQ + RS or Q+ = RQ + SGated SR latchA gated SR latch circuit diagram constructed from NOR gates.A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second levelof NAND gates to the inverted SR latch (or a second level of AND gates to the direct SR latch).The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and asimple SR latch would transform into a gated SR latch with inverted enable).With E high (enable true), the signals can pass through the input gates to the encapsulated latch;all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output,i.e. the latch is transparent.With E low (enable false) the latch is closed (opaque) and remains in the state it was left the lasttime E was high.The enable input is sometimes a clock signal, but more often a read or write strobe.
9. 9. Gated S-R latch operation E/C Action 0 No action (keep state) Symbol for a gated SR latch 1 The same as non-clocked SR latchGated D latchA D-type transparent latch based on an SR NAND latchA gated D latch based on an SR NOR latchThis latch exploits the fact that, in the two active input combinations (01 and 10) of a gated SRlatch, R is the complement of S. The input NAND stage converts the two D input states (0 and 1)to these two input combinations for the next SR latch by inverting the data input signal. The lowstate of the enable signal produces the inactive "11" combination. Thus a gated D-latch may beconsidered as a one-input synchronous SR latch. This configuration prevents application of therestricted input combination. It is also known as transparent latch, data latch, or simply gatedlatch. It has a data input and an enable signal (sometimes named clock, or control). The wordtransparent comes from the fact that, when the enable input is on, the signal propagates directlythrough the circuit, from the input D to the output Q.
10. 10. Transparent latches are typically used as I/O ports or in asynchronous systems, or in synchronoustwo-phase systems (synchronous systems that use a two-phase clock), where two latchesoperating on different clock phases prevent data transparency as in a master–slave flip-flop.Latches are available as integrated circuits, usually with multiple latches per chip. For example,74HC75 is a quadruple transparent latch in the 7400 series. Gated D latch truth table E/C D Q Q Comment 0 X Qprev Qprev No change 1 0 0 1 Reset Symbol for a gated D latch 1 1 1 0 SetThe truth table shows that when the enable/clock input is 0, the D input has no effect on theoutput. When E/C is high, the output equals D.D flip-flopD flip-flop symbolThe D ﬂip-ﬂop is widely used. It is also known as a data or delay flip-flop.The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such asthe rising edge of the clock). That captured value becomes the Q output. At other times, theoutput Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, ora delay line.
11. 11. Truth table: Clock D Qnext Rising edge 0 0 Rising edge 1 1 Non-Rising X Q(X denotes a Dont care condition, meaning the signal is irrelevant)Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (whichignores the D and clock inputs), much like an S-R flip-flop. Usually, the illegal S = R = 1condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used asdescribed above. Inputs Outputs S R D > Q Q 0 1 X X 0 1 1 0 X X 1 0 1 1 X X 1 14-bit serial-in, parallel-out (SIPO) shift register
12. 12. These flip-flops are very useful, as they form the basis for shift registers, which are an essentialpart of many electronic devices. The advantage of the D flip-flop over the D-type "transparentlatch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, andsubsequent changes on the D input will be ignored until the next clock event. An exception isthat some flip-flops have a "reset" signal input, which will reset Q (to zero), and may be eitherasynchronous or synchronous with the clock.The above circuit shifts the contents of the register to the right, one bit position on each activetransition of the clock. The input X is shifted into the leftmost bit position.Classical positive-edge-triggered D flip-flopA positive-edge-triggered D flip-flopThis clever circuit consists of two stages implemented by S-R NAND latches. The input stage(the two latches on the left) processes the clock and data signals to ensure correct input signalsfor the output stage (the single latch on the right). If the clock is low, both the output signals ofthe input stage are high regardless of the data input; the output latch is unaffected and it storesthe previous state. When the clock signal changes from low to high, only one of the outputvoltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, thelower output becomes low; if D = 1, the upper output becomes low. If the clock signal continuesstaying high, the outputs keep their states regardless of the data input and force the output latchto stay in the corresponding state as the input logical zero remains active while the clock is high.Hence the role of the output latch is to store the data only while the clock is low.The circuit is closely related to the gated D latch as both the circuits convert the two D inputstates (0 and 1) to two input combinations (01 and 10) for the output S-R latch by inverting thedata input signal (both the circuits split the single D signal in two complementary S and Rsignals). The difference is that in the gated D latch simple NAND logical gates are used while inthe positive-edge-triggered D flip-flop SR NAND latches are used for this purpose. The role ofthese latches is to "lock" the active output producing low voltage (a logical zero); thus thepositive-edge-triggered D flip-flop can be thought of as a gated D latch with latched input gates.
13. 13. Q6. Give any two applications of a shift register. Answer 1. Very effective for sequence detectors. 2. Shift register are often used as the state register in a sequential device.Q7. Explain the working principle of a 4 bit Johnson counter with a neatdiagram. Answer.The demonstration above initially implements only the legitimate counting sequence of the Johnsoncounter. To allow for all possible illegal combinations and show how they get straightened out, we
14. 14. would need 66 separate images for the over lays, and each is about 6.5k bytes in size. That’s a bit muchto ask of many users. however, you can see the count correction gates operating at the bottom of thecounter, and see how they work. The D input to flip-flop C is not directly driven from the B output.Rather , A’ and C’ are added together, and that combination is NO Red with B’, as a result, improper bitsreaching flip-flop B get blocked, and flip-flop C can only take on the correct state to reinstate the correctshifting sequence. To see this in action, you can click on any of the individual flip-flops in the figure. Thiswill force a load of all remaining images and change the state of the selected flip-flop without applying aclock pulse. Then you can watch the behavior of the counter as it removes improper countingsequences. Remember that the download of the additional images may take some time, so please bepatient. You can only identify an illegal counting sequence because more than one output will be high(logic 1). Since each output is enabled by a transition from 0 to 1 or from 1 to 0 in a specific position inthe counter, more than one transition will produce more than one output, which is illegal in this context.Also note that in order to repeatedly invert the shifting bits as they start from flip-flop A, the E output isfed back to the A flip-flops D input. This shift does not constitute a second transition here; only when allbits are the same does this appear as a transition. Of course, these must necessarily be edge-triggeredflip-flops clocked simultaneously. The Reset inputs are asynchronous and override the clocking signal. Inaddition, the CMOS ICs that serve as the model for this demonstration change state on the rising edge ofthe clock, so this model does the same. The COUT signal is the Carry Out, which is a symmetrical squarewave at one-tenth of the incoming Clock signal frequency. It is quite suitable for clocking a secondcounter of the same type, to form a multiple-digit decimal counter.Q8. Explain temperature and weather forecast system with a neat circuit diagram.Answer;
15. 15. Hardware calibration is simply a matter of setting the offset voltage to the value listed in table 1 for youraltitude. A jumper on the input of the DS2438 allows the use of the DS2438 to measure the offset. Put thejumper in the A-C position and using the iButton Viewer for the DS2438, set the voltage to the tablevalue using the 25-turn pot. Once it’s set, put the jumper in the A-B position to read pressure. For altitudes in between the values listed in the table, simple interpolation will give accurateresults. An Excel spreadsheet will be also available online to calculate intermediate values. Software:Routines currently exist to measure the DS2438s Vad voltage. Once this voltage is measured, thepressure is calculated using: Press = slope * Vad + intercept Where the slope and intercept are thevalues listed in table 1 for your altitude. The prototype code I used had an external text file to store theslope and intercept values. This allows the user to edit the file to fine-tune the calibration if desired.