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1. VIDYA VIKAS INSTITUTE OF ENGINEERING MYSURU
PRESENTER:
MOHAMMED ADNAN KHAN (4VM20CS041) Subject:
BASIC ELECTRONICS
TOPICS:
FLIP-FLOP
MULTIPLEXER
DECODERS
Associated faculty:
PROF. ASHA R
[DEPT. OF ELECTRICAL AND ELECTRONICS ENGINEERING]

2. CONTENTS
FLIP-FLOP
SR FLIP-FLOP & JK
FLIP-FLOP
MULTIPLEXER
TYPES OF
MULTIPLEXER
ADVANTAGES
AND
APPLICATIONS OF
MULTIPLEXER
DECODER
TYPES OF
DECODER

3. 1) FLIP-FLOP
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information
which is also known as a BISTABLE MULTIVIBRATOR. The circuit can be made to change state by signals applied
to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic.
Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems.
Types of Flip-Flop :
 SR Flip-Flop
 JK Flip-Flop
 SR FLIP-FLOP
The R-S (Reset Set) flip flop is the simplest flip flop of all and easiest to understand. It is basically a device which has
two outputs one output being the inverse or complement of the other, and two inputs.
A pulse on one of the inputs to take on a particular logical state. The outputs will then remain in this state until a similar
pulse is applied to the other input. The two inputs are called the Set and Reset input (sometimes called the preset and
clear inputs).
SR flip-flop is a one-bit memory bi-stable device that has two inputs, one is labelled S, will SET the device (meaning
the output Q = 1), and other is labelled R, will RESET the device (meaning the output Q = 0). Then the SR - FFs are
made from latches and FFs respond only on specific times.

4. Now if Q = 0 and R = 1, then these are the states of inputs of gate B,
therefore the outputs of gate B is at 1 (making it the inverse of Q
i.e. 0). The output of gate B is connected to an input of gate A so
if S = 1, both inputs of gate A are at the logic 1 state. This means
that the output of gate A must be 0 (as was originally specified). In
other words, the 0 state at Q is continuously disabling gate B so
that any change in R has no effect. Also the 1 state at is
continuously enabling gate A so that any change S will be
transmitted through to Q. The above conditions constitute one of the
stable states of the device referred to as the Reset state since Q = 0.
Now suppose that the R-S flip flop in the Reset state, the S input goes to 0. The output of
gate A i.e. Q will go to 1 and with Q = 1 and R = 1, the output of gates B ( ) will go to 0 with
now 0 gate A is disabled keeping Q at 1. Consequently, when S returns to the 1 state it has
no effect on the flip flop whereas a change in R will cause a change in the output of gate B.
The above conditions constitute the other stable state of the device, called the Set state
since Q = 1.
Note that the change of the state of S from 1 to 0 has caused the flip flop to change from the Reset state to the Set
state. There is another input condition which has not yet been considered. That is when both the R and S inputs are
taken to the logic state 0. When this happens both Q and will be forced to 1 and will remain so far as long as R and S
are kept at 0. However when both inputs return to 1 there is no way of knowing whether the flip flop will latch in the
Reset state or the Set state. The condition is said to be indeterminate because of this indeterminate state great care
must be taken when using R-S flip flop to ensure that both inputs are not instructed simultaneously.

5. TRUTH TABLE
When NOR gate are used the R and S inputs are transposed
compared with the NAND version. Also the stable state when
R and S are both 0. A change of state is effected by pulsing
the appropriate input to the 1 state. The indeterminate state is
now when both R and S are simultaneously at logic 1. Table 3
shows this operation.

6.  JK FLIP-FLOP
The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can
occur when both inputs S and R are equal to logic level “1”. Due to this
additional clocked input, a JK flip-flop has four possible input combinations,
“logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop
is similar to that of an SR Bistable Latch as seen in the previous tutorial
except for the addition of a clock input
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S and
R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a
JK flip flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except
for the addition of a clock input. Both the S and the R inputs of the previous SR bistable
have now been replaced by two inputs called the J and K inputs, respectively after its
inventor Jack Kilby. Then this equates to: J = S and K = R. The two 2-input AND gates of the gated SR bistable have
now been replaced by two 3-input NAND gates with the third input of each gate connected to the outputs at Q and Q.
This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1” state to be
used to produce a “toggle action” as the two inputs are now interlocked. If the circuit is now “SET” the J input is
inhibited by the “0” status of Q through the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0”
status of Q through the upper NAND gate. As Q and Q are always different we can use them to control the input.
When both inputs J and K are equal to logic “1”, the JK flip flop toggles as shown in the following truth table.

7. TRUTH TABLE
Although this circuit is an improvement on the clocked SR flipflop it still suffers from timing problems called “race” if
the output Q changes state before the timing pulse of the clock input has time to go “OFF”. To avoid this the timing
pulse period ( T ) must be kept as short as possible (high frequency). As this is sometimes not possible with
modern TTL IC‟s the much mproved Master-Slave JK Flip-flop was developed.

8. 2) MULTIPLEXER
Multiplexer is a device that has multiple inputs and a single line output. The data select lines determine which input
is connected to the output. It is also called a data selector.Multiplexers are capable of handling both analog and
digital applications. In analog applications, multiplexers are made up of relays and transistor switches, whereas in
digital applications, the multiplexers are built from standard logic gates.
Multiplexer Types
Multiplexers are classified into four types:
 2-1 multiplexer (1select line)
 4-1 multiplexer (2 select lines)
 8-1 multiplexer(3 select lines)
 16-1 multiplexer (4 select lines)
Unlike encoder and decoder, there are n selection lines and 2^n input lines. So, there is a total of 2^n
possible combinations of inputs. A multiplexer is also treated as Mux

9.  2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1
selection line, i.e., S0 and single outputs, i.e., Y. On the basis of the
combination of inputs which are present at the selection line S0,
one of these 2 inputs will be connected to the output. The block
diagram and the truth table of the 2×1 multiplexer are given below.

10.  4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2
selection lines, i.e., S0 and S1 and single output, i.e., Y. On the basis of the
combination of inputs that are present at the selection lines S0 and S1, one of
these 4 inputs are connected to the output. The block diagram and the truth
table of the 4×1 multiplexer are given below.

11. 8 to 1 Multiplexer:
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3,
A4, A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single
output, i.e., Y. On the basis of the combination of inputs that are present
at the selection lines S0, S1, and S2, one of these 8 inputs are
connected to the output. The block diagram and the truth table of the
8×1 multiplexer are given below.

12. 16 to 1 Multiplexer:
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A0, A1, …,
A16, 4 selection lines, i.e., S0, S1, S2, and S3 and single output, i.e., Y.
On the basis of the combination of inputs that are present at the
selection lines S0, S1, and S2, one of these 16 inputs will be connected
to the output. The block diagram and the truth table of the 16×1

13. ADVANTAGES OF MULTIPLEXER:
 In multiplexer, the usage of a number of wires can be decreased.
 It reduces the cost as well as the complexity of the circuit
 The implementation of a number of combination circuits can be possible by using a multiplexer
 Mux doesn’t require K-maps & simplification
 The multiplexer can make the transmission circuit less complex & economical
 The dissipation of heat is less because of the analog switching current which ranges from 10mA to 20mA.
 The multiplexer ability can be extended to switch audio signals, video signals, etc.
 The digital system reliability can be improved using a MUX as it decreases the number of exterior wired
connections.
 MUX is used to implement several combinational circuits
APPLICATIONS:
Multiplexers are used in various applications wherein multiple-data need to be transmitted by using a single line.
Communication System : A communication system has both a communication network and a transmission system. By
using a multiplexer, the efficiency of the communication system can be increased by allowing the transmission of
data, such as audio and video data from different channels through single lines or cables.
Computer Memory : Multiplexers are used in computer memory to maintain a huge amount of memory in the
computers, and also to reduce the number of copper lines required to connect the memory to other parts of the
computer.
Telephone Network : In telephone networks, multiple audio signals are integrated on a single line of transmission with
the help of a multiplexer.
Transmission from the Computer System of a Satellite The multiplexer is used to transmit the data signals from the
computer system of a spacecraft or a satellite to the ground system by using a GSM satellite.

14. 3) DECODER
The combinational circuit that change the binary information into 2^N output lines is known as Decoders. The
binary information is passed in the form of N input lines. The output lines define the 2^N-bit code for the binary
information. In simple words, the Decoder performs the reverse operation of the Encoder. At a time, only one input
line is activated for simplicity. The produced 2^N-bit output code is equivalent to the binary information.

15. TYPES OF DECODER:
2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and
A1 and E and four outputs, i.e., Y0, Y1, Y2, and Y3. For each
combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 2 to 4
line decoder are given below

16.  3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8
line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6,
and Y7 and three outputs, i.e., A0, A1, and A2. This circuit has an enable input
'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 3 to 8 line
encoder are given below.

17.  4 to 16 line Decoder:
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……,
Y16 and four inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be
constructed using either 2 to 4 decoder or 3 to 8 decoder. There is the following
formula used to find the required number of lower-order decoders. Required
number of lower order decoders=m2/m1; m1 = 8; m2 = 16
Required number of 3 to 8 decoders = 16/8 = 2

18. THANK
YOU