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Totem Technologies for Analog, Memory, Mixed-Signal Designs

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Ansys
Ansys

Analog, mixed-signal and custom designs face unique challenges when it comes to power and reliability analysis. SRAM and FLASH memories are pushing the envelope to handle large designs, while mixed-signal and RF designs need concurrent analysis of large analog blocks with interspersed digital logic as well as substrate noise coupling. This presentation demonstrates how Totem, a single platform for Power Noise and Reliability, can be used to address the unique challenges for analog, mixed-signal and custom designs. Learn more on our website: https://bit.ly/1qk5Juj

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6/23/2014 © 2014 ANSYS, Inc. 1 Totem™ Technologies for Analog / Memory / Mixed-Signal Designs Design Automation Conference 2014
6/23/2014 © 2014 ANSYS, Inc. 2 Analog Mixed-Signal Trends & Challenges Technology Scaling High Analog + Digital Integration Increasing Sensor/IP usage Capacity Tighter Reliability Margins Concurrent Analog +Digital Analysis Sensor/IP Validation and Modeling >$60B Mobile Computing Automotive Electronics IoT/Connected Devices Key Market Drivers Technology Trends Challenges  Analog IC market expected to grow to $60B by 2015  Transition from discrete analog to analog subsystems  Complex verification and integration challenges
6/23/2014 © 2014 ANSYS, Inc. 3 Totem: ‘Power-Noise-Reliability’ Platform SRAM Flash DRAM IO (DDR, SerDes) Custom Digital Analog/RF
6/23/2014 © 2014 ANSYS, Inc. 4 Totem: Core Technologies Analysis Modeling • Support for complex analog and mixed signal designs • Transient analysis with ps resolution • EM/ESD analysis for advanced technology nodes • Transistor-level macro models • Multi-cycle Multi-mode models • Model roll up to SoC CMM Totem RedHawk Extraction • On-chip PG RLC + Substrate RC extraction • EM aware extraction
6/23/2014 © 2014 ANSYS, Inc. 5 Design Modeling PG Extraction + Simulation Totem Analysis Flow GDSII Vector Simulation Signal Only Net-list Totem Internal Model GUI Based Debug Layout Annotated Results
6/23/2014 © 2014 ANSYS, Inc. 6 Grid Weakness Check Resistance Bottleneck Grid Weakness View Layout View Missing VIA3 Missing VIA2 Short Path Trace • Grid weakness map is the normalized resistance of all transistor pins in the design • Highlight weakly connected transistors
6/23/2014 © 2014 ANSYS, Inc. 7 Case Study: Analog IP Analog Supply IR Map Metal3 strap not extended Layout View Gross Connectivity Issue Early layout analysis helps catch gross grid violations
6/23/2014 © 2014 ANSYS, Inc. 8 Dynamic Voltage Drop • Worst IR drop of transistor pins shown • Cross probe a list of transistor pins with the layout • Plot the currents/voltage of all transistors based on list Transistor Pin IR Drop View Transistor Pin Cross-Probe
6/23/2014 © 2014 ANSYS, Inc. 9 Substrate Noise Coupling Digital Core PLL Memories IN OUT Digital Core PLL/Analog block Device Threshold voltage modulation Level Functionality / performance issues in Analog & RF circuits Circuit Level Preventing integration of sensitive circuits System Level analog CPU Check/Sign-off Full-chip Noise PLL guard ring noise source victim Plan/Analyze Isolation Structures Check Noise Impact on Delay
6/23/2014 © 2014 ANSYS, Inc. 10 Chip Image Sensors: Key Challenges Substrate
6/23/2014 © 2014 ANSYS, Inc. 11 Chip Image Sensors: Key Challenges Substrate Digital Logic (Interface, Timing, Processing Output) ADC Analog to Digital Conversion Pixel Array Analog Signal Processing Substrate Noise Coupling • Digital Switching Noise • PG Grid Coupling • Substrate Noise Coupling
6/23/2014 © 2014 ANSYS, Inc. 12 Chip Image Sensors: Key Challenges Power Noise Analysis • Digital Logic (Vectored/Vectorless) • Analog (Vectored) • Substrate Noise (Digital +Analog) Substrate Digital Logic (Interface, Timing, Processing Output) ADC Analog to Digital Conversion Pixel Array Analog Signal Processing Substrate Noise Coupling • Digital Switching Noise • PG Grid Coupling • Substrate Noise Coupling
6/23/2014 © 2014 ANSYS, Inc. 13 BJT Poly R/TiN Metal R Mim/Mom Caps Diodes RF/Analog Design Support for Complex Structures BJT Device : Entire PNP Structure Emitter Base Collector Pdiff Ndiff BJT marker Layer
6/23/2014 © 2014 ANSYS, Inc. 14 Case Study: RF Analog Power EM Schematic of RF/Analog Part of Chip Narrow M2 straps carrying significant current causing EM violation M3/M2/M1 Layout View M3/M2/M1 EM Map
6/23/2014 © 2014 ANSYS, Inc. 15 Memory and Custom Digital Designs Complete Sign-off Flow Coverage/ Weakness Detection Sign-off Power Analysis Static DC Vectored Multi Cycle Multi State Signal EM Analysis VectorLess Transient Vectored Multi Cycle Multi State
6/23/2014 © 2014 ANSYS, Inc. 16 Large FPGA Chip Small Design Large Design Node Count 14M 321M Transistor Count 7M 228M Run Time 39mins 20h22m • Full-chip capacity • Large DRAM memories • Large FLASH memories • Embedded Big Analog, Small Digital blocks FPGA Faric with rows of SRAM, DSP blocks System Controller DDR Memory and Other IP Blocks IO IO Large Design Handling
6/23/2014 © 2014 ANSYS, Inc. 17 IP Modeling and Sign-off for SoC IP/Block Design Sign-off IP/Block IR, DvD, EM, ESD Sign-off Totem IP Enabled Full Chip Sign-off Full-chip DvD/EM/ESD Sign-off IP Boundary condition Sign-off RedHawk Model Creation Embedd ed Constrai nts IP Protection Physical + Electrical
6/23/2014 © 2014 ANSYS, Inc. 18 Case Study: IP Modeling Xtor Level Voltage Drop of Mem1(WRITE) Xtor Level Voltage Drop of Mem2(READ) Worst xtor drop ~ 210mV Worst xtor drop ~ 130mV Mem1 Mem2 Two instantiations of same memory macro Instance Level Voltage Drop Map SoC instantiating the hierarchical models generated using Totem
6/23/2014 © 2014 ANSYS, Inc. 19 Totem: Power-Noise-Reliability Custom, Analog & RF Designs Noise Coupling Coverage Reliability Usability IR Drop DvD Substrate Noise Power EM Signal EM ESD Mem/SRAM DDR/Serdes TCAM/DRAM Analog/RF Versatile GUI Layout Based Full-Chip Capacity Coverage Noise Reliability Usability

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Totem Technologies for Analog, Memory, Mixed-Signal Designs

  • 1. 6/23/2014 © 2014 ANSYS, Inc. 1 Totem™ Technologies for Analog / Memory / Mixed-Signal Designs Design Automation Conference 2014
  • 2. 6/23/2014 © 2014 ANSYS, Inc. 2 Analog Mixed-Signal Trends & Challenges Technology Scaling High Analog + Digital Integration Increasing Sensor/IP usage Capacity Tighter Reliability Margins Concurrent Analog +Digital Analysis Sensor/IP Validation and Modeling >$60B Mobile Computing Automotive Electronics IoT/Connected Devices Key Market Drivers Technology Trends Challenges  Analog IC market expected to grow to $60B by 2015  Transition from discrete analog to analog subsystems  Complex verification and integration challenges
  • 3. 6/23/2014 © 2014 ANSYS, Inc. 3 Totem: ‘Power-Noise-Reliability’ Platform SRAM Flash DRAM IO (DDR, SerDes) Custom Digital Analog/RF
  • 4. 6/23/2014 © 2014 ANSYS, Inc. 4 Totem: Core Technologies Analysis Modeling • Support for complex analog and mixed signal designs • Transient analysis with ps resolution • EM/ESD analysis for advanced technology nodes • Transistor-level macro models • Multi-cycle Multi-mode models • Model roll up to SoC CMM Totem RedHawk Extraction • On-chip PG RLC + Substrate RC extraction • EM aware extraction
  • 5. 6/23/2014 © 2014 ANSYS, Inc. 5 Design Modeling PG Extraction + Simulation Totem Analysis Flow GDSII Vector Simulation Signal Only Net-list Totem Internal Model GUI Based Debug Layout Annotated Results
  • 6. 6/23/2014 © 2014 ANSYS, Inc. 6 Grid Weakness Check Resistance Bottleneck Grid Weakness View Layout View Missing VIA3 Missing VIA2 Short Path Trace • Grid weakness map is the normalized resistance of all transistor pins in the design • Highlight weakly connected transistors
  • 7. 6/23/2014 © 2014 ANSYS, Inc. 7 Case Study: Analog IP Analog Supply IR Map Metal3 strap not extended Layout View Gross Connectivity Issue Early layout analysis helps catch gross grid violations
  • 8. 6/23/2014 © 2014 ANSYS, Inc. 8 Dynamic Voltage Drop • Worst IR drop of transistor pins shown • Cross probe a list of transistor pins with the layout • Plot the currents/voltage of all transistors based on list Transistor Pin IR Drop View Transistor Pin Cross-Probe
  • 9. 6/23/2014 © 2014 ANSYS, Inc. 9 Substrate Noise Coupling Digital Core PLL Memories IN OUT Digital Core PLL/Analog block Device Threshold voltage modulation Level Functionality / performance issues in Analog & RF circuits Circuit Level Preventing integration of sensitive circuits System Level analog CPU Check/Sign-off Full-chip Noise PLL guard ring noise source victim Plan/Analyze Isolation Structures Check Noise Impact on Delay
  • 10. 6/23/2014 © 2014 ANSYS, Inc. 10 Chip Image Sensors: Key Challenges Substrate
  • 11. 6/23/2014 © 2014 ANSYS, Inc. 11 Chip Image Sensors: Key Challenges Substrate Digital Logic (Interface, Timing, Processing Output) ADC Analog to Digital Conversion Pixel Array Analog Signal Processing Substrate Noise Coupling • Digital Switching Noise • PG Grid Coupling • Substrate Noise Coupling
  • 12. 6/23/2014 © 2014 ANSYS, Inc. 12 Chip Image Sensors: Key Challenges Power Noise Analysis • Digital Logic (Vectored/Vectorless) • Analog (Vectored) • Substrate Noise (Digital +Analog) Substrate Digital Logic (Interface, Timing, Processing Output) ADC Analog to Digital Conversion Pixel Array Analog Signal Processing Substrate Noise Coupling • Digital Switching Noise • PG Grid Coupling • Substrate Noise Coupling
  • 13. 6/23/2014 © 2014 ANSYS, Inc. 13 BJT Poly R/TiN Metal R Mim/Mom Caps Diodes RF/Analog Design Support for Complex Structures BJT Device : Entire PNP Structure Emitter Base Collector Pdiff Ndiff BJT marker Layer
  • 14. 6/23/2014 © 2014 ANSYS, Inc. 14 Case Study: RF Analog Power EM Schematic of RF/Analog Part of Chip Narrow M2 straps carrying significant current causing EM violation M3/M2/M1 Layout View M3/M2/M1 EM Map
  • 15. 6/23/2014 © 2014 ANSYS, Inc. 15 Memory and Custom Digital Designs Complete Sign-off Flow Coverage/ Weakness Detection Sign-off Power Analysis Static DC Vectored Multi Cycle Multi State Signal EM Analysis VectorLess Transient Vectored Multi Cycle Multi State
  • 16. 6/23/2014 © 2014 ANSYS, Inc. 16 Large FPGA Chip Small Design Large Design Node Count 14M 321M Transistor Count 7M 228M Run Time 39mins 20h22m • Full-chip capacity • Large DRAM memories • Large FLASH memories • Embedded Big Analog, Small Digital blocks FPGA Faric with rows of SRAM, DSP blocks System Controller DDR Memory and Other IP Blocks IO IO Large Design Handling
  • 17. 6/23/2014 © 2014 ANSYS, Inc. 17 IP Modeling and Sign-off for SoC IP/Block Design Sign-off IP/Block IR, DvD, EM, ESD Sign-off Totem IP Enabled Full Chip Sign-off Full-chip DvD/EM/ESD Sign-off IP Boundary condition Sign-off RedHawk Model Creation Embedd ed Constrai nts IP Protection Physical + Electrical
  • 18. 6/23/2014 © 2014 ANSYS, Inc. 18 Case Study: IP Modeling Xtor Level Voltage Drop of Mem1(WRITE) Xtor Level Voltage Drop of Mem2(READ) Worst xtor drop ~ 210mV Worst xtor drop ~ 130mV Mem1 Mem2 Two instantiations of same memory macro Instance Level Voltage Drop Map SoC instantiating the hierarchical models generated using Totem
  • 19. 6/23/2014 © 2014 ANSYS, Inc. 19 Totem: Power-Noise-Reliability Custom, Analog & RF Designs Noise Coupling Coverage Reliability Usability IR Drop DvD Substrate Noise Power EM Signal EM ESD Mem/SRAM DDR/Serdes TCAM/DRAM Analog/RF Versatile GUI Layout Based Full-Chip Capacity Coverage Noise Reliability Usability