This presentation highlights the new capabilities of RedHawk, the industry standard power noise and reliability sign-off solution that is FinFET ready. The new features include Distributed Machine Processing (DMP) for ultra large design simulation with sign-off accuracy, Chip Package Analysis (CPA) - the industry's first integrated chip-package co-simulation and co-analysis environment, and foundry certification for 16nm FinFET design. Learn more on our website: https://bit.ly/1t3lNZ1

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What’s New in RedHawk™ 2014
Design Automation Conference 2014

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RedHawk 2014
Industry Standard Power Noise Reliability Sign-Off
Industry Standard
Input Data
Foundry Certified
Collaterals
Package Layout RedHawk 2014 Totem™ IP Models
Connectivity,
Static IR
Power, Signal
EM
Dynamic
Voltage Drop
Rush Current
Substrate
Noise
ESD Integrity
Chip Power
Model
Impact on
Timing

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Best-in-Class Engines
Industry Standard Power Noise Reliability Sign-Off
VectorLess™ Statistical, RTL2GDS, Mixed-mode Sign-off Coverage
Integrated
Extraction,
Solver
Silicon Validated
Accuracy
On-die RLC, Package/PCB RLCK
APL, Pico-second Resolution
Scalable
Architecture
Native Stacked Die (3D, 2.5D), Distributed Full-chip Capacity

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Source: ARM FinFET study, 2013
FinFET Advantages:
• Improved performance
• Reduced power
• Higher device density
Technology Trends: FinFET Adoption

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FinFET Based Design Challenges
Reduced Noise Margins
Requirements for FinFET Based Design Power Noise Sign-off
• Capacity Ultra-large Design Modeling
• Reliability EM and ESD Accuracy
• Chip-Package-System Comprehensive and Accurate Noise Prediction
Reduced EM / ESD Tolerance Increased Temp. Effect

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FinFET Design Challenges: Power Noise
Higher Voltage Drop
IR + L di / dt
More Switching Current
(Higher Density)
Higher Peak Currents
(25% more)
More Complex and Higher
Grid Impedance
Reduced Supply Voltages
(<800mV)
• 100mV on 1V (10%) vs 150mV on 700mV (21%)
• Significantly lower tolerance for error
On-Chip Power Grid Circuits Package / PCB
Foundry Certification Switching Scenario Detailed Model
Exploding Capacity, Complexity and Accuracy Needs

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FinFET Design Challenges: EM Reliability
Degraded EM Limits Heightened EM Violations
(30% Less)
Increased Peak Current
(25% more)
Increased Self Heating
Power EM Post Thermal EM
Higher FinFET Temp
• Via and Wire EM limits routing / driver sizing
• Thermal impact on EM:
– 25ºC increase on FinFET degrades expected
lifetime by 3x to 5x on device and metal layers

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FinFET Design Challenges: ESD Reliability
Higher ESD Sensitivity
• Careful layout based ESD design planning
• ESD integrity as part of sign-off
Higher Device Sizes
Lack of Snapback
Device Support
Degraded Diode
Protection
Reduced Interconnect
Reliability

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FinFETs: Expanding Capacity Challenges
Discrete
Single core
Dual core
Quad-core
Multi-core
CPU + GPU,
DDR5, …
~1.5B+ nodes
~ 300M gates
~3B+ nodes
~500M nodes
~ 120M gates
~100M nodes
~50M nodes ~ 50M gates
~ 12M gates
Multi-CPU
Distributed
Hierarchical
Smart Caching

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DMP: Distributed Machine Processing
Capacity and Performance
Analysis Result
Exploration
Distributed
Simulation
• Distributed full-chip simulation with package and PCB impact
• Design split and simulated over the network with each partition full-chip aware
• Full flat accuracy with 2-3X performance gain
Chip + Package + PCB

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DMP Performance Benchmark
3X Performance Improvement from Prior Generation
RedHawk
(2009)
RedHawk
(2012)
RedHawk
(2012)
Hierarchical
RedHawk
(2014)
DMP
100+M Instance Design

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FinFET: Increased Noise Sensitivity
Chip
Team
Package
Team
Existing Approach
• Chip team needs to decipher and use package model
• No immediate feedback on package design issues

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FinFET: Increased Noise Sensitivity
Chip
Team
Package
Team
RedHawk-CPA
Simultaneous Package and Chip Voltage Drop Debug and Optimization

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RedHawk-CPA: Package-Aware Chip Signoff
Accuracy and Ease-of-Use
• Fully distributed, chip analysis ready, per bump parasitic network
• Automatic hook-up to chip layout maintaining pin-to-pin mapping
• Simultaneous chip-package design analysis and optimization
Distributed
19.2mV
Lumped
13.8mV

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RedHawk-CPA Performance
Size Runtime/Memory # Terminals
6 layers, 3 domains
Per Bump Resolution
10 min / ~15 GB 600
Package Extraction
RedHawk Simulation
No Package Lumped Package RedHawk-CPA
Simulation Time 53 min 51 min 58 min
Memory Usage 6.8 GB 6.9 GB 7.76 GB

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RedHawk-CPA Impact on DvD
• Ideal Voltage = 0.998V
• 3 simulation results
– Green No Pkg maxima @ 0.99V
– Blue Lump Pkg maxima @ 0.97V
– Red Dist Pkg maxima @ 0.93V
• Distribution of instance DvD shifts with
CPA R-L-C-K package
Instance Voltage
Number of Instances
Higher voltage drop

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Foundry Certified for FinFET Processes
Certified for TSMC 16N v1.0 and Intel Custom Foundry 14nm
• Resistance correlation including Middle-end and Back-end layers
• EM Rule handling
• IR/DvD extraction and analysis
Unique Metal Architecture
• Special metal layers
• Complex via structures and shapes
• Diffusion as interconnect structures
Enhanced Modeling
• Dummy devices
• Vertical resistance
• Double patterning
Complex EM, ESD
• Current-direction, metal topology based
• Width, temperature, self-heat, etc
• Pseudo-via, RMS, etc.

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RedHawk 2014
Industry Standard Power Noise Reliability Sign-Off
Connectivity Checks
Static Analysis
Power/SignalEM Vectorless
Dynamic
ESD Integrity In-rush Current
Chip Power Model
Impact on Timing
Reliability Power Noise
Gridcheck Vectorless Scan
RTL/Gate VCD
Applied Analysis
Distributed Pkg
(CPA)
Maximum Signoff Coverage!

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RedHawk 2014
Member of Elite Group of Best-in-Class Solutions
ANSYS Fluent™
• Aerodynamics
• Engine Combustion
• Thermal Management
ANSYS Mechanical™
• Static Structural
• Vibration and Stress
• Component Design
ANSYS HFSS™
• EMI/EMC Certification
• Wireless Connectivity
• Electric Motors, Battery
ANSYS RedHawk™
• RTL2GDS Power Noise
• Foundry Certified Reliability
• C-P-S Power, Signal, Thermal

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Related Presentations @ DAC2014
• System Power Analysis with Correlation Results for Advanced Processor Designs
• Silicon Correlation of RedHawk Dynamic Voltage Drop in High Power Density SoC
• Chip-Package-System Based Power Integrity Analysis Flow for 14nm Mobile Designs
• RedHawk-CPA: New Paradigm for Faster Chip-Package Convergence
• Achieving Power Noise Reliability Sign-off for FinFET based Designs