FABRICATION OF MONOLITHIC DIODES, RESISTORS, CAPACITORS & FETs

1. FABRICATION
OF MONOLITHIC
DIODES Mr .C.KARTHIKEYAN,
ASSISTANT PROFESSOR,
ECE, RMKCET

2. COMPLETE CROSS SECTIONAL VIEW OF THE CIRCUIT

3. High speed diode
APP: Digital IC
ADV: lowest storage time &
lowest forward voltage drop

4. stored charge device time &
high speed turn off among all

5. Highest breakdown voltage

6. Choice of the diode structure depends on the PERFORMANCE & APPLICATION
DESIGNED

7. SCHOTTKY BARRIER DIODE
1. 2 Contacts ~~ (i) RECTIFYING CONTACT ---- Metal semiconductor diode / schottky barrier diode
(ii) OHMIC CONTACT – Lead attached to a semiconductor device
3. The CONTACT POTENTIAL bet. the SC & the metal creates a BARRIER to the
flow of conduction electrons from SC to metal

8. CASE 1: Al – p type impurity is deposited on n type Si it is OHMIC CONTACT, NO pn Junction formed
Done by making n+ diffusions in the n regions near the surface of Al is deposited
CASE 2: Al is deposited directly upon n type Si a METAL SEMICONDUCTOR DIODE is formed
The V I Characteristics is Similar as pn junction but the physical mechanisms different & complicated
OPERATION:
FB –lowers the barrier & permits the e- flow from SC to METAL
 SCHOTTKY DIODE ~~~~ MAJORITY CARRIERS e- carry current
NEGLIGIBLE STORAGE TIME as e- flows from n type Si enter the Al at the contact surface and mix and are not
stored.
PN junction DIODE ~~~ MINORITY CARRIERS constitute current
Substantial diode ON to OFF.

9. DIFFUSED
RESISTOR
01.
EPITAXIAL
RESISTOR
PINCHED
RESISTOR
THIN FILM
RESISTOR
FABRICATION OF INTEGRATED RESISTORS
02.
03.
04.

10. The diffused resistor is formed in any one of the isolated regions of
epitaxial layer during base or emitter diffusion processes.
very economical
DIMENSIONS- surface geometry such as the length, width and the
diffused impurity profile
DIFFUSED RESISTOR

11. SHEET RESISTANCE

12. BASE RESISTOR EMITTER RESISTOR

13. EPITAXIAL RESISTOR
Large value of resistance by B & E resistor achieved
by using n-epitaxial collector region
SHEET RESISTANCE of epitaxial layer : 1-
10kΏ/sq.

14. PINCHED RESISTOR
The SHEET RESISTIVITY of SC region INCREASED by
REDUCING its EFFECTIVE CROSS ECTIONAL AREA

15. OPERATION OF PINCHED RESISTOR
•NO current flow through the n type material (dark region) due to diode at
contact 2 in reverse direction
•Small REVERSE SATURATION CURRENT flow through n type material
•By creating the n type region the EFFECTIVE CROSS SECTIONAL
AREA for the conduction is REDUCED & thus,
•RESISTANCE between 1 & 2 INCREASES

16. THIN FILM RESISTOR
•NiCr NICHROME – very thin film of thickness <1µm is vapour deposited
on the SiO2 layer
•Using MASKED ETCHING the desired geometry of thin film is achieved
to obtain suitable value of resistors
•OHMIC CONTACTS: Al metallization

17. CONSTRUCTION -THIN FILM RESISTOR

18. ADVANTAGES OF THIN FILM RESITORS OVER DIFFFUSED RESISTOR
•Less & small parasitic components ~~~HF behavior is better
•Values can be adjusted even after the fab. By cutting a part of resistor with a
LASER BEAM (laser trimming)
•Low temperature coefficient ~~~ more stable
•How to obtain HIGH VALUE thin film resistor:
•By depositing TANTALUM over SiO2 layer
•DISADVANTAGE: additional steps required in fab.

19. FABRICATION OF INTEGRATED CAPACITOR
•2 TYPES:
•JUNCTION CAPACITOR
•MOS & Thin Film capacitor

20. CONSTRUCTION --JUNCTION CAPACITOR
A parasitic cap C1 is formed due to the J1 bet n type epitaxial & substrate
Junction cap of RB diode as an element in monolithic IC
2 JUNCTIONS: J1 & J2 , C2 depends on junction Area, impurity
concentration of n type epitaxial layer and Voltage across the junction
C2 polarised when J2 is RB
EQUIVALENT CIRCUIT

21. CONSTRUCTION - MOS and Thin Film Capacitor
A parallel plate capacitor
SiO2 – dielectric
Heavily doped n+ at the lower plate & thin film of Al forms the upper plate
with SiO2 as dielectric

22. ADVANTAGES
Voltage rating exceeds thin film capacitor failed
Need voltage protection
Free from substrate parasitics it requires additional MASKING &
DEPOSITION steps
Al / Tantalum – cap plates, Al2O3 / Ta2O5 – dielectric material
Ta2O5 – large value capacitors
DISADVANTAGES
Circuit flexibility
Silicon Nitride offers high value capacitance
Higher dielectric constant

23. FABRICATION OF FET – (i) JFET CONSTRUCTION
Basic process – BJT config
Epitaxial layer – collector used as n-channel JFET
P+ gate formed in n channel by DIFFUSION / ION IMPLANTATION
n+ regions formed under the D& S contact – OHMIC CONTACT

24. (ii) MOSFET CONSTRUCTION
2 types: ENHANCEMENT , DEPLETION
Metallic gate is separated from semiconductor channel by SiO2 layer
SiO2 – high input resistance
Threshold voltage - 3-6 V
Power supply voltage – 12V for DRAIN supply

25. REDUCE THRESHOLD VOLTAGE BY 2 TECHNIQUES - 1. Si3N4
sandwiched bet 2 SiO2 layer
Provides necessary to prevent impurities top penetrate through SiO2
Dielectric constant Si3N4 – 7.5, SiO2- 4

26. 2. POLYSILICON GATE
Si3N4 coated on entire surface of p type wafer
Next etched away from the surface
P+ impurities are implanted in the exposed p sub– ISOLATION
Field oxide –SiO2 grown over P+ regions – Si3N4 region unaffected by
OXIDATION
Si3N4 removed by etching & SiO2 layer thermally grown
Polycrystalline Si – Polysilicon deposited over entire wafer
n+ source & drain regions formed by ion implantation
Thin oxide layer – allows penetration of dopants
Protective isolating SiO2 layer using –
PHOTO LITHOGRAPHIC PROCESS
Al is evaporated over entire wafer

27. 2 POINTS TO BE KNOWN
Self aligning property eliminates Cgs & Cgd – OVERLAP CAPACITANCE
NO ISOLATION rtequired

28. (iii) CMOS FAB
N type well/tub is diffused in p type substrate where
PMOS is fabricated
B1 tied to S1 connected to GND
B2 tied to S2 connected to VDD
Both source substrate (nmos & pmos) diode are RB
Isolation achieved

29. THANKS!!!