fab

1. nMOS fabrication
•1. Processing is carried out on a thin wafer cut from a single crystal of
silicon of high purity into which the required p-impurities are
introduced as the crystal is grown.

2. •2. A layer of silicon dioxide (Si02), typically 1 μm thick, is grown all over
the surface of the wafer to protect the surface, act as a barrier to dopants
during processing.

3. • 3. The surface is now covered with a photo resist which is deposited onto the
wafer and spun to achieve an even distribution of the required thickness.

4. • 4. The photo resist layer is then exposed to ultraviolet light through
a mask which defines those regions into which diffusion is to take
place together with transistor channels. Assume, for example, that
those areas exposed to ultraviolet radiation are polymerized
(hardened), but that the areas required for diffusion are shielded by
the mask and remain unaffected

5. • 5. These areas are subsequently readily etched away together with the
underlying silicon dioxide so that the wafer surface is exposed in the window
defined by the mask

6. • 6. The remaining photoresist is removed and a thin layer of Si02 (0.1
jlm typical) is grown over the entire chip surface and then polysilicon
is deposited on top of this to form the gate structure.

7. • 7. Further photo resist coating and masking allows the polysilicon to
be patterned (as shown in Step 6) and then the thin oxide is removed
to expose areas into which n-type impurities are to be diffused to
form the source and drain as shown.

8. • 8. Thick oxide (Si02) is grown over all again and is then masked with
photoresist and etched to expose selected arcs of the polysilicon gate
and the drain and source areas where connections (i.e. contact cuts)
are to be made.

9. • 9. The whole chip then has metal (aluminum) deposited over its
surface to a thickness typically of 1μm. This metal layer is then
masked and etched to form the required interconnection pattern.

10. CMOS fabrication
• The p-well Process:

12. • nWELL PROCESS:

13. • CMOS nWELL processing steps

14. • Cross sectional view of n-well CMOS inverter

15. • The Twin-Tub Process:
• Steps in processing a wafer

16. •Twin tub has the following steps
 Tub formation
 Thin oxide construction
 Gate formation
 Source and drain implantations
 Contact cut definitions
 Metallization

18. LATCH-UP IN CMOS CIRCUITS:
• Latch-up is a condition in which the parasitic components give rise to the
establishment of low-resistance conducting paths between VDD and VSS
with disastrous results. Careful control during fabrication is necessary to
avoid this problem.
• Latch-up may be induced by glitches on the supply rails or by incident
radiation.
• The mechanism involved may be understood by referring to Figure 2.21,
which shows the key parasitic components associated with a p-well
structure in which an inverter circuit.

20. • There are, in effect, two transistors and two resistances (associated with
the p-well and with regions of the substrate) which form a path between
VDD and VSS.
• If sufficient substrate current flows to generate enough voltage across
RS to turn on transistor T1, this will then draw current through Rp and, if
the voltage developed is sufficient, T2 will also turn on, establishing a
self-sustaining low-resistance path between the supply rails.
• If the current gains of the two transistors are such that β1 x β2 > 1, latch-
up may occur. Equivalent circuits are given in Figure 2.22.

21. Latchup
• Latchup: positive feedback leading to VDD – GND short
• Major problem for 1970’s CMOS processes before
it was well understood
• Avoid by minimizing resistance of body to GND / VDD
• Use plenty of substrate and well taps
Slide 21
n+
p substrate
p+
n well
A
Y
GND VDD
n+
p+
substrate tap
well tap
n+ p+
n well
Rsub
Rwell
Vsub
Vwell
Rsub
Rwell
Vsub
Vwell

25. Latch-up circuit for N-well process

26. Latchup Prevention
• Reducing the resistor values and reducing the gain of the
parasitic transistors are the basis for eliminating latch up.
This can be approached by
Latchup resistant CMOS process
 Layout techniques

27. Latch up resistant process (Layout techniques will be presented in the following
section) :
 Use of silicon starting-material with a thin epitaxial layer on top of a highly
doped substrate. This decreases the value of the substrate resistor.
 Retrograde well structure formed by a highly doped area at the bottom of
the well and by lightly doping on the top portion of the well. This preserves
good characteristics for the p-transistors and also reduces the well resistance
deep in the well.
Increasing holding voltage above VDD such that latchup will not occur.
 It is hard to reduce the betas (gains) of the bipolar transistors.

28. Internal Latchup Prevention Technique
• Reducing Rsubstrate and Rwell by substrate contact. The following rules
are presented to achieve this goal.
• • Every well must have a substrate contact of the appropriate type.
• • Every substrate contact should be connected to metal directly to a supply
pad.
Place substrate contacts as close as possible to the source connection of
transistors and connect them to supply rails (i.e., VSS for n-device, VDD for p-
devices).
 A very conservative rule would place one substrate contact for every supply
connection. A less conservative rule is to place a substrate contact for every
5-10 transistors or every 25-100μm.
 Lay out n- and p- transistors with packing of n-device toward VSS and
packing of p-device toward VDD

29. BICMOS
• A known deficiency of MOS technology lies in the limited
load driving capabilities of MOS transistors.
• This is due to the limited current sourcing and current
sinking abilities associated with both p- and n-transistors and
although it is possible